static void AppTaskStart (void *p_arg)
{
(void)p_arg;
BSP_Init(); /* Initialize BSP functions */
CPU_Init(); /* Initialize the uC/CPU services */
BSP_Tick_Init(); /* Start Tick Initialization */
Mem_Init(); /* Initialize memory managment module */
Math_Init(); /* Initialize mathematical module */
#if (OS_TASK_STAT_EN > 0)
OSStatInit(); /* Determine CPU capacity */
#endif
BSP_LED_Off(0);
#if (APP_CFG_SERIAL_EN == DEF_ENABLED)
App_SerialInit(); /* Initialize Serial communication for application ... */
#endif
APP_TRACE_INFO(("Creating Application Events...\n\r"));
AppEventCreate(); /* Create Application Events */
APP_TRACE_INFO(("Creating Application Tasks...\n\r"));
AppTaskCreate(); /* Create application tasks */
while (DEF_TRUE) { /* Task body, always written as an infinite loop. */
BSP_LED_Toggle(0);
OSTimeDlyHMSM(0, 0, 0, 100);
}
}
static void App_TaskStart (void *p_arg)
{
OS_ERR os_err;
(void)p_arg; /* See Note #1. */
BSP_Init(); /* Start BSP and tick initialization. */
BSP_Tick_Init(); /* Start Tick Initialization. */
BSP_UART_Init(BSP_UART_DEFAULT, /* Start UART Initialization */
BSP_BUSCLK,
9600);
BSP_LCD_Init(); /* Initialize the seven-segment display panel. */
#if OS_CFG_STAT_TASK_EN > 0u
OSStatTaskCPUUsageInit(&os_err); /* Compute CPU capacity with no task running */
#endif
#ifdef CPU_CFG_INT_DIS_MEAS_EN
CPU_IntDisMeasMaxCurReset();
#endif
APP_TRACE_INFO(("Creating Application Events...\n\r"));
App_ObjCreate(); /* Create Applicaton kernel objects. */
APP_TRACE_INFO(("Creating Application Tasks...\n\r"));
App_TaskCreate(); /* Create Application tasks. */
while (DEF_TRUE) { /* Task body, always written as an infinite loop. */
OSTimeDlyHMSM(0, 0, 2, 0,
OS_OPT_TIME_HMSM_STRICT, &os_err);
// BSP_UART_Send_String(BSP_UART_1,
// "Hello\n");
uart_printf("Hello world\n");
OSTimeDly(10, OS_OPT_TIME_HMSM_STRICT, &os_err);
uart_printf("os_err = %d\n", os_err);
// while (BSP_SW_Read (BSP_SW_1) != DEF_ON) {
// OSTimeDly(1, OS_OPT_TIME_HMSM_STRICT, &os_err);
// }
// BSP_LED_Toggle(BSP_LED_RED);
//
// BSP_UART_Send_String(BSP_UART_1,
// "Hello\n");
//
// while (BSP_SW_Read (BSP_SW_1) == DEF_OFF) {
// OSTimeDly(1, OS_OPT_TIME_HMSM_STRICT, &os_err);
// }
}
}
static void AppTask_1(void *p_arg)
{
(void)p_arg;
APP_TRACE_INFO(("AppTask_1\n\r"));
while (DEF_TRUE) { /* Task body, always written as an infinite loop. */
APP_TRACE_INFO(("Task1\n"));
OSTimeDlyHMSM(0, 0, 0, 100);
}
}
// Set additional data besides MIC data
// M0..M5 + X0 + X1
// Max 8 slots
// Make sure last 2 slots folowed mic data closely
static unsigned char Config_SP0_Out( unsigned char mic_num )
{
unsigned char err ;
if( flag_state_pwd ) return 0 ;
APP_TRACE_INFO(("\r\nConf FM36 Mic num = %d\r\n", mic_num));
err = DM_SingleWrite( FM36_I2C_ADDR, 0x22EB, mic_num ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
//select output data source slot
err = DM_SingleWrite( FM36_I2C_ADDR, 0x22C1 + mic_num, 0x1018 ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x22C2 + mic_num, 0x1019 ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
return err;
}
//Setup External Lin data input source
//From : SP0_RX, SP1_RX
static unsigned char Config_Lin( unsigned char lin_sp_index, unsigned char start_slot_index )
{
unsigned char err ;
if( flag_state_pwd ) return 0 ;
APP_TRACE_INFO(("\r\nConfig_Lin sp_index = %d, start_slot_index = %d\r\n", lin_sp_index, start_slot_index));
//Aux-Source
err = DM_SingleWrite( FM36_I2C_ADDR, 0x229A, lin_sp_index+1 ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
//Aux-in-L
err = DM_SingleWrite( FM36_I2C_ADDR, 0x229B, (lin_sp_index<<3) + start_slot_index ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
//Aux-in-R
err = DM_SingleWrite( FM36_I2C_ADDR, 0x229C, (lin_sp_index<<3) + start_slot_index + 1 ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
return err;
}
static void AppTask_2 (void *p_arg)
{
INT8U err;
(void)p_arg;
APP_TRACE_INFO(("AppTask_2\n\r"));
pSecureEventFlagGrp = OSFlagCreate(0x0, &err);
/* Enable Crypto clock */
CLK->AHBCLK |= CLK_AHBCLK_CRPTCKEN_Msk;
BSP_IntVectSet(BSP_INT_ID_CRYPTO, CRYPTO_IRQHandler);
BSP_IntEn(BSP_INT_ID_CRYPTO);
PRNG_ENABLE_INT();
while (1)
{
PRNG_Open(PRNG_KEY_SIZE_256, 0, 0);
bsp_printf("Start PRNG...\n");
PRNG_Start();
OSFlagPend(pSecureEventFlagGrp, 0x1, OS_FLAG_WAIT_SET_ANY, 0, &err);
dump_PRNG();
OSTimeDlyHMSM(0, 0, 0, 100);
}
}
void App_ProbeInit (void)
{
#if (APP_CFG_PROBE_OS_PLUGIN_EN == DEF_ENABLED)
OSProbe_Init();
OSProbe_SetCallback(App_ProbeCallback);
OSProbe_SetDelay(50);
#endif
#if (APP_CFG_PROBE_COM_EN == DEF_ENABLED)
APP_TRACE_INFO(("Initializing uC/Probe ... \n\r"));
ProbeCom_Init(); /* Initialize the uC/Probe communications module */
#if (PROBE_COM_CFG_RS232_EN == DEF_ENABLED)
ProbeRS232_Init(115200);
ProbeRS232_RxIntEn();
#endif
#if (PROBE_COM_CFG_TCPIP_EN == DEF_ENABLED)
ProbeTCPIP_Init();
#endif
#endif
#if (APP_CFG_PROBE_DEMO_INTRO_EN == DEF_ENABLED)
ProbeDemoIntro_Init();
#endif
}
unsigned char I2C_GPIO_Write_iM205 (unsigned char addr, unsigned char reg, unsigned char val )
{
unsigned char state, data;
#if OS_CRITICAL_METHOD == 3u /* Allocate storage for CPU status register */
OS_CPU_SR cpu_sr = 0u;
#endif
APP_TRACE_INFO(("\r\nI2C_GPIO_Write_iM205(0x%0X,0x%0X, 0x%0X)", addr, reg, val));
OS_ENTER_CRITICAL();
i2c_start(); //起始条件，开始数据通信
//发送地址和数据读写方向
data = (addr << 1) | 0; //低位为0，表示写数据
state = i2c_write_byte(data);
if(state != 0) {
i2c_stop();
OS_EXIT_CRITICAL();
//APP_TRACE_INFO(("\r\n write byte err1!"));
return 1;
}
//写入数据
state = i2c_write_byte( reg );
if(state != 0) {
i2c_stop();
OS_EXIT_CRITICAL();
//APP_TRACE_INFO(("\r\n write byte err2!"));
return 1;
}
i2c_restart();
//发送地址和数据读写方向
data = (addr << 1) | 0; //低位为0，表示写数据
state = i2c_write_byte(data);
if(state != 0) {
i2c_stop();
OS_EXIT_CRITICAL();
//APP_TRACE_INFO(("\r\n write byte err3!"));
return 1;
}
//写入数据
state = i2c_write_byte( val );
if(state != 0) {
i2c_stop();
OS_EXIT_CRITICAL();
//APP_TRACE_INFO(("\r\n write byte err4!"));
return 1;
}
i2c_stop(); //终止条件，结束数据通信
OS_EXIT_CRITICAL();
return 0;
}
int main ()
{
OS_ERR os_err;
BSP_Init();
CPU_Init();
OSInit(&os_err);
if(os_err != OS_ERR_NONE) {
APP_TRACE_INFO(("Error initialising OS. OsInit() returned with error %u\r\n", os_err));
}
OSTaskCreate((OS_TCB *)&AppTaskStartTCB,
(CPU_CHAR *)"App Task Start",
(OS_TASK_PTR ) AppTaskStart,
(void *) 0,
(OS_PRIO ) 5,
(CPU_STK *)&AppTaskStartStk[0],
(CPU_STK )(4096u / 10u),
(CPU_STK_SIZE) 4096u,
(OS_MSG_QTY ) 0,
(OS_TICK ) 0,
(void *) 0,
(OS_OPT )(OS_OPT_TASK_STK_CLR),
(OS_ERR *)&os_err);
if(os_err != OS_ERR_NONE) {
APP_TRACE_INFO(("Error creating task. OSTaskCreate() returned with error %u\r\n", os_err));
}
OSStart(&os_err);
if(os_err != OS_ERR_NONE) {
APP_TRACE_INFO(("Error starting. OSStart() returned with error %u\r\n", os_err));
}
while (DEF_TRUE) {
;
}
}
static void AppTaskObj1 (void *p_arg)
{
OS_ERR os_err;
OS_MSG_SIZE msg_size;
(void)p_arg;
while (DEF_TRUE) {
#if (OS_CFG_SEM_EN > 0u)
OSSemPend(&AppTaskObjSem,
0,
OS_OPT_PEND_BLOCKING,
0,
&os_err);
#endif
#if (OS_CFG_MUTEX_EN > 0u)
OSMutexPend(&AppTaskObjMutex,
0,
OS_OPT_PEND_BLOCKING,
0,
&os_err);
OSMutexPost(&AppTaskObjMutex,
OS_OPT_POST_NONE,
&os_err);
#endif
#if (OS_CFG_Q_EN > 0u)
OSQPend(&AppTaskObjQ,
0,
OS_OPT_PEND_BLOCKING,
&msg_size,
0,
&os_err);
#endif
#if (OS_CFG_FLAG_EN > 0u)
OSFlagPend(&AppTaskObjFlag,
DEF_BIT_00,
0,
OS_OPT_PEND_FLAG_SET_ALL + OS_OPT_PEND_FLAG_CONSUME + OS_OPT_PEND_BLOCKING,
0,
&os_err);
#endif
OSTimeDlyHMSM( 0u, 0u, 0u, 10u,
OS_OPT_TIME_HMSM_STRICT,
&os_err);
APP_TRACE_INFO(("Object test task 1 running ....\n"));
}
}
//onoff : 0 - turn off PDM clock, 1 - turn on PDM clock
//fast_switch : 0 - normal usage, 1 - fast onoff switch, not care pop sound
unsigned char FM36_PDMADC_CLK_OnOff( unsigned char onoff, unsigned char fast_switch )
{
unsigned char err ;
if( flag_state_pwd ) return 0 ;
APP_TRACE_INFO(("\r\nEnable/Disbale FM36 ADC PDM CLK: %d",onoff));
if( onoff ) { //PDMCLK_ON, for normal operation
err = DM_SingleWrite( FM36_I2C_ADDR, 0x3FCF, 0x0020 ) ; //turn on clk
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x3F90, 0x0000 ) ; //power up MIC0-5
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;
}
if( fast_switch == 0 ) {
OSTimeDly(5); //depop time
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x3F96, 0x003F ) ; //unmute MIC0-5
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;
}
} else { //PDMCLK_OFF
err = DM_SingleWrite( FM36_I2C_ADDR, 0x3F96, 0x3F3F ) ; //mute MIC0-5
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;
}
if( fast_switch == 0 ) {
OSTimeDly(10); //wait data 0 to cyclebuffer
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x3F90, 0x003F ) ; //power down MIC0-5
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;
}
if( fast_switch == 0 ) {
OSTimeDly(5);
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x3FCF, 0x0024 ) ; //turn off clk
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;
}
}
return err;
}
static void AppTaskObj0 (void *p_arg)
{
OS_ERR os_err;
(void)p_arg;
while (DEF_TRUE) {
#if (OS_CFG_SEM_EN > 0u)
OSSemPost(&AppTaskObjSem,
OS_OPT_POST_1,
&os_err);
#endif
#if (OS_CFG_MUTEX_EN > 0u)
OSMutexPend(&AppTaskObjMutex,
0,
OS_OPT_PEND_BLOCKING,
0,
&os_err);
OSTimeDlyHMSM( 0u, 0u, 0u, 100u,
OS_OPT_TIME_HMSM_STRICT,
&os_err);
OSMutexPost(&AppTaskObjMutex,
OS_OPT_POST_NONE,
&os_err);
#endif
#if (OS_CFG_Q_EN > 0u)
OSQPost( &AppTaskObjQ,
(void *) 1u,
1u,
OS_OPT_POST_FIFO,
&os_err);
#endif
#if (OS_CFG_FLAG_EN > 0u)
OSFlagPost(&AppTaskObjFlag,
DEF_BIT_00,
OS_OPT_POST_FLAG_SET,
&os_err);
#endif
OSTimeDlyHMSM( 0u, 0u, 0u, 10u,
OS_OPT_TIME_HMSM_STRICT,
&os_err);
APP_TRACE_INFO(("Object test task 0 running ....\n"));
}
}
static void App_TaskStart (void *p_arg)
{
OS_ERR os_err;
(void)p_arg; /* See Note #1. */
BSP_Init(); /* Start BSP and tick initialization. */
BSP_Tick_Init(); /* Start Tick Initialization. */
BSP_LCD_Init(); /* Initialize the seven-segment display panel. */
#if OS_CFG_STAT_TASK_EN > 0u
OSStatTaskCPUUsageInit(&os_err); /* Compute CPU capacity with no task running */
#endif
#ifdef CPU_CFG_INT_DIS_MEAS_EN
CPU_IntDisMeasMaxCurReset();
#endif
APP_TRACE_INFO(("Creating Application Events...\n\r"));
App_ObjCreate(); /* Create Applicaton kernel objects. */
APP_TRACE_INFO(("Creating Application Tasks...\n\r"));
App_TaskCreate(); /* Create Application tasks. */
while (DEF_TRUE) { /* Task body, always written as an infinite loop. */
BSP_LED_Toggle(BSP_LED_RED);
OSTimeDlyHMSM(0, 0, 0, 200,
OS_OPT_TIME_HMSM_STRICT, &os_err);
BSP_LED_Toggle(BSP_LED_GREEN);
OSTimeDlyHMSM(0, 0, 0, 200,
OS_OPT_TIME_HMSM_STRICT, &os_err);
}
}
static unsigned char Config_SPx_Format( unsigned char bit_length, unsigned char i2s_tdm_sel )
{
unsigned char err ;
unsigned short temp;
if( flag_state_pwd ) return 0 ;
APP_TRACE_INFO(("\r\nConf FM36 Bit length = %d, %d\r\n", bit_length, i2s_tdm_sel));
if( i2s_tdm_sel == 0 ) { //I2S
if( bit_length == 32 ) {
//temp = 0x78FF;//32bit I2S, 16bit data, MSB first,Left alignment
APP_TRACE_INFO(("\r\nConf FM36 I2S to 32bit, not support!\r\n"));
return FM36_WR_DM_ERR;
} else {//16
temp = 0x78D9;//16bit I2S,16bit data, MSB first,Left alignment
}
} else { //8slot-TDM
if( bit_length == 32 ) {
temp = 0x78FF;//32bit TDM, 16bit data, MSB first,Left alignment,8 slot
} else { //16
temp = 0x78DF;//16bit TDM,16bit data, MSB first,Left alignment,8 slot
}
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x2260, temp ) ; //SP0
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x2261, temp ) ; //SP1
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
return err;
}
static unsigned char Config_SR( unsigned short sr )
{
unsigned char err ;
unsigned short temp ;
if( flag_state_pwd ) return 0 ;
APP_TRACE_INFO(("\r\nConf FM36 SR = %dkHz\r\n", sr));
switch ( sr ) {
case 8000 :
temp = 0x1F40;
break;
case 16000 :
temp = 0x3E80;
break;
case 22050 :
temp = 0x5622;
break;
case 24000 :
temp = 0x5DC0;
break;
case 32000 :
temp = 0x7D00;
break;
case 44100 :
temp = 0xAC44;
break;
default: //48000 :
temp = 0xBB80;
break;
}
//select output data source slot
err = DM_SingleWrite( FM36_I2C_ADDR, 0x2268, temp ) ; //Output Clock for ADC DPLL, PDM input sampling rate.
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x2269, temp ) ;// reference Clock for DAC DPLL,PDM output sampling rate.
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
return err;
}
static unsigned char Config_SP0IN_to_SP1Out( void )
{
unsigned char err ;
unsigned int i ;
if( flag_state_pwd ) return 0 ;
APP_TRACE_INFO(("\r\nConf FM36 SP0 Rx to SP1 Tx\r\n"));
for(i = 0; i < sizeof(fm36_para_table_tdm_aec)/4; i++) {
err = DM_SingleWrite( FM36_I2C_ADDR, fm36_para_table_tdm_aec[i][0], fm36_para_table_tdm_aec[i][1] ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
}
return err;
}
unsigned char FM36_PWD_Bypass( void )
{
unsigned char err ;
if( flag_state_pwd ) return 0 ;
APP_TRACE_INFO(("\r\nPower down FM36 to bypass SP0<-->SP1\r\n"));
err = DM_SingleWrite( FM36_I2C_ADDR, 0x3FEF, 0x2000 ) ; //pwd
//err = DM_SingleWrite( FM36_I2C_ADDR, 0x22F9, 1 ) ; //pwd
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
flag_state_pwd = true ;
return err;
}
unsigned char Config_PDM_PA( void )
{
unsigned char err ;
unsigned int i ;
unsigned char buf[3] ;
APP_TRACE_INFO(("\r\nConf PDM PA\r\n"));
buf[0] = 0;
for(i = 0; i < sizeof(para_table_pdm_pa)/2; i++) {
buf[1] = para_table_pdm_pa[i][0];
buf[2] = para_table_pdm_pa[i][1];
err = TWID_Write( MAX98504>>1, 0, 0, buf, sizeof(buf), NULL);
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
}
return err;
}
void App_TaskUserIF (void *p_arg)
{
CPU_INT32U *msg;
CPU_INT08U err;
CPU_INT32U key_state;
CPU_INT08U ruler_id;
(void)p_arg;
OSTimeDly(500); //wait for other tasks be ready , and time for power stable for ruler
Head_Info(); //Send header
Ruler_Power_Switch(1);
Init_Global_Var();
AB_POST();
#ifndef BOARD_TYPE_AB01
APP_TRACE_INFO_T(("WARNING: NOT AB01, NO MCU CRT UART SWITCH\r\n"));
#endif
while ( DEF_TRUE ) { /* Task body, always written as an infinite loop. */
msg = (CPU_INT32U *)(OSMboxPend(App_UserIF_Mbox, 0, &err)); //pending, no timeout
if (msg != NULL) {
key_state = *msg ;
APP_TRACE_INFO(("\r\n"));
switch( key_state & MSG_TYPE_MASK ) {
case MSG_TYPE_RESET : //reset send msg
//PDM_Pattern_Gen(0); //gen cp2240 pattern
Head_Info();
break;
case MSG_TYPE_SWITCH ://Switch
APP_TRACE_INFO_T(("Switch status updated: SW[1..0] = [%d, %d]\r\n",\
(key_state>>0)&(0x01),(key_state>>1)&(0x01) ));
/**********************************************************************/
//To do something to do with Switch selection...
// Switch 'SW0' used to control DEBUG port:
// 0: ON : UART1 used as debug port
// 1: OFF: DBG UART used as debug port
if( (key_state>>(8 + 1)) & 0x01) { //check if SW0 switch status changed
OSTaskDel( APP_CFG_TASK_SHELL_PRIO );
OSSemSet (Bsp_Ser_Tx_Sem_lock, 1, &err) ;
OSSemSet (Bsp_Ser_Rx_Sem_lock, 1, &err) ;
Task_ReCreate_Shell();
if( ((key_state>>1)& 0x01 ) == 0 ) { //debug to UART1
Debug_COM_Sel = 1 ;
BSP_Ser_Init(115200);
} else { //debug to DBG_UART
Debug_COM_Sel = 0 ;
UART_Init(PC_UART, ISR_PC_UART, 115200 ); //To PC ? Sem recreat issue
}
}
// // Switch 'SW1' used to control Buzzer mute:
// // 0: ON : Buzzer muted
// // 1: OFF: Buzzer unmuted
// if( (key_state>>(8 + 0)) & 0x01) { //check if SW1 switch status changed
// if( ((key_state>>0)& 0x01 ) == 0 ) {
// BUZZER_MUTE = 1; //mute buzzer
// } else {
// BUZZER_MUTE = 0; //unmute buzzer
// }
// }
// Switch 'SW1' used to control CODEC LOUT PGA Gain:
// 0: ON : 24dB attenuated signal for Phone MIC input
// 1: OFF: Normal signal for ACQUA
if( (key_state>>(8 + 0)) & 0x01) { //check if SW1 switch status changed
if( ((key_state>>0)& 0x01 ) == 0 ) {
err = CODEC_LOUT_Small_Gain_En( true ) ; //enable 24dB attenuated signal for Phone Mic
} else {
err = CODEC_LOUT_Small_Gain_En( false ) ; //normal signal, no attenuation
}
if( OS_ERR_NONE != err ) {
APP_TRACE_INFO_T(("ERR: Set CODEC_LOUT_Small_Gain_En err! [%d]\r\n",err));
}
}
break;
case MSG_TYPE_PORT_DET :
if( port_enable == false ) {
//APP_TRACE_INFO(("Ruler port disabled !\r\n"));
break;
}
APP_TRACE_INFO_T(("Ruler port status changed: Port[3..0] = [%1d%1d%1d%1d] ",\
(key_state>>0)&(0x01),(key_state>>1)&(0x01),(key_state>>2)&(0x01),(key_state>>3)&(0x01) ));
for( ruler_id = 0 ; ruler_id < 4 ; ruler_id++ ) {
if( (key_state>>( 8 + 3 - ruler_id)) & 0x01) { //check if Ruler Port[0] switch status changed
if( ( (key_state>>(3 - ruler_id)) & 0x01 ) == 0 ) { // ruler attached, setup ruler
//LED_Set( LED_P0 + ruler_id );
APP_TRACE_INFO_T(("Ruler[%d] Attached.\r\n", ruler_id ));
Global_Ruler_State[ruler_id] = RULER_STATE_ATTACHED;
err = Init_Ruler( ruler_id );
if( OS_ERR_NONE != err ) {
//LED_Clear( LED_P0 + ruler_id );
continue;
}
err = Setup_Ruler( ruler_id );
if( OS_ERR_NONE != err ) {
//LED_Clear( LED_P0 + ruler_id );
continue;
}
//// err = Ruler_Setup_Sync( ruler_id );
//// if( OS_ERR_NONE != err ) {
//// //LED_Clear( LED_P0 + ruler_id );
//// continue;
//// }
err = Get_Ruler_Type( ruler_id );
if( OS_ERR_NONE != err ) {
//LED_Clear( LED_P0 + ruler_id );
continue;
}
err = Get_Ruler_Version( ruler_id );
if( OS_ERR_NONE != err ) {
//LED_Clear( LED_P0 + ruler_id );
continue;
}
err = Ruler_POST( ruler_id );
if( OS_ERR_NONE != err ) {
//LED_Clear( LED_P0 + ruler_id );
continue;
}
Global_Ruler_State[ruler_id] = RULER_STATE_CONFIGURED ;
// mic_mask = Global_Mic_Mask[ruler_id];
// err = Update_Mic_Mask( ruler_id, mic_mask );
// if( OS_ERR_NONE != err ) {
// continue;
// }
// if( mic_mask ) {
// Global_Ruler_State[ruler_id]= RULER_STATE_SELECTED;
// }
//OSTimeDly(500);
//simple_test_use();//test for Dr.Yang and use USBApp0815.exe
} else { // ruler detached
//LED_Clear( LED_P0 + ruler_id );
APP_TRACE_INFO_T(("Ruler[%d] Detached.\r\n", ruler_id ));
Global_Ruler_State[ruler_id] = RULER_STATE_DETACHED ;
Global_Ruler_Type[ruler_id] = 0 ;
Global_Mic_Mask[ruler_id] = 0 ;
}
}
}
/*
*********************************************************************************************************
* App_TaskUART_Tx()
*
* Description : Process UART Transmit related process between Audio Bridge and PC.
* Wait for data message from other task that want to send to PC.
*
* Argument(s) : p_arg Argument passed to 'App_TaskUART_Tx()' by 'OSTaskCreate()'.
*
* Return(s) : none.
*
* Note(s) : (1) The first line of code is used to prevent a compiler warning because 'p_arg' is not
* used. The compiler should not generate any code for this statement.
*********************************************************************************************************
*/
void App_TaskUART_Tx( void *p_arg )
{
(void)p_arg;
CPU_INT08U errCode ;
CPU_INT08U *pTaskMsgIN ;
pNEW_CMD pPcCmd ;
CPU_INT32U counter ;
CPU_INT32U size ;
CPU_INT32U times ;
CPU_INT08U *pChar ;
pTaskMsgIN = NULL;
pPcCmd = NULL;
errCode = UNKOW_ERR_RPT ;
// unsigned char tt[512];
// for (unsigned int i = 0; i<512; i++) {
// tt[i] = '0'+i;
// }
//// while(1){
//
//// kfifo_put(pUART_Send_kfifo[PC_UART], (unsigned char *)&tt , 512) ;
//// UART_WriteStart( PC_UART );
//// OSTimeDly(1);
////
//// }
//
// while (DEF_TRUE) {
//
// // Noah to Uart transmit
// pTaskMsgIN = (INT8U *)OSQPend( EVENT_MsgQ_Noah2PCUART, 0, &errCode );
//
// if( pTaskMsgIN != NULL && OS_ERR_NONE == errCode ) {
// kfifo_put(pUART_Send_kfifo[PC_UART], (unsigned char *)&tt , 512) ;
// UART_WriteStart( PC_UART );
// }
// }
//////////////////////////////////////////////////////////////////////////////
//pcSendDateToBuf( EVENT_MsgQ_Noah2PCUART, SET_FRAME_HEAD(PcCmdTxID,FRAM_TYPE_EST), NULL, 0, 0, NULL, 0 ) ; // send a EST package on startup
while (DEF_TRUE) {
// Noah to Uart transmit
pTaskMsgIN = (INT8U *)OSQPend( EVENT_MsgQ_Noah2PCUART, 0, &errCode );
if( pTaskMsgIN != NULL && OS_ERR_NONE == errCode ) {
// Time_Stamp();
// APP_TRACE_INFO(("\r\n:App_TaskUART_Tx : [%d] start ",pPcCmd->DataLen + 5));
pPcCmd = (pNEW_CMD)pTaskMsgIN ;
pChar = (unsigned char *)pTaskMsgIN ;
counter = (pPcCmd->data_len[0]<<16) + (pPcCmd->data_len[1]<<8) + pPcCmd->data_len[2];
counter += 8;
#if( false )
APP_TRACE_INFO(("\r\n############DATA==counter: %d ####################\r\n",counter));
for(unsigned int i = 0; i< counter; i++ ){
APP_TRACE_INFO(("%0X ", *(pChar+i) ));
if(i%32 == 31) {
APP_TRACE_INFO(("\r\n"));
}
}
APP_TRACE_INFO(("\r\n##########################################\r\n"));
#endif
times = counter / UART1_SEND_QUEUE_LENGTH ;
counter = counter % UART1_SEND_QUEUE_LENGTH ;
if( times ) {
for(unsigned int i = 0; i<times; i++ ) {
while(1) {
size = kfifo_get_free_space( pUART_Send_kfifo[PC_UART] );
if( size >= UART1_SEND_QUEUE_LENGTH ) {
kfifo_put(pUART_Send_kfifo[PC_UART], pChar, UART1_SEND_QUEUE_LENGTH) ;
pChar += UART1_SEND_QUEUE_LENGTH;
break;
}
//OSTimeDly(1);
}
UART_WriteStart( PC_UART ); //send data
}
}
if( counter ) {
while(1) {
size = kfifo_get_free_space( pUART_Send_kfifo[PC_UART] );
if( size >= counter ) {
kfifo_put(pUART_Send_kfifo[PC_UART], pChar, counter) ;
break;
}
//OSTimeDly(1);
}
UART_WriteStart( PC_UART ); //send data
}
OSMemPut( pMEM_Part_MsgUART, pTaskMsgIN );
}
////OSTimeDly(5);
}
}
void AppTaskEq1Fp (void *p_arg)
{
CPU_FP32 a;
CPU_FP32 b;
CPU_FP32 c;
CPU_FP32 eps;
CPU_FP32 f_a;
CPU_FP32 f_c;
CPU_FP32 delta;
CPU_INT08U iteration;
RAND_NBR wait_cycles;
while (DEF_TRUE) {
eps = 0.00001;
a = 1.0;
b = 4.0;
delta = a - b;
iteration = 0u;
if (delta < 0) {
delta = delta * -1.0;
}
while ((2.00 * eps) < delta) {
c = (a + b) / 2.0;
f_a = a * a - 3.0;
f_c = c * c - 3.0;
if (((f_a > 0.0) && (f_c < 0.0)) ||
((f_a < 0.0) && (f_c > 0.0))) {
b = c;
} else if (((f_a > 0.0) && (f_c > 0.0)) ||
((f_a < 0.0) && (f_c < 0.0))) {
a = c;
} else {
break;
}
delta = a - b;
if (delta < 0) {
delta = delta * -1.0;
}
iteration++;
wait_cycles = Math_Rand();
wait_cycles = wait_cycles % 1000;
while (wait_cycles > 0u) {
wait_cycles--;
}
if (iteration > APP_TASK_EQ_1_ITERATION_NBR) {
APP_TRACE_INFO(("AppTaskEq1Fp() max # iteration reached\n"));
break;
}
}
APP_TRACE_INFO(("Eq1 Task Running ....\n"));
if (iteration == APP_TASK_EQ_1_ITERATION_NBR) {
#if 0 /* See Note 1. */
APP_TRACE_INFO(("Root = %f; f(c) = %f; #iterations : %d\n", c, f_c, iteration));
#else
APP_TRACE_INFO(("Eq1 task; #iterations : %d\n", iteration));
#endif
}
}
}
static void AppTaskStart (void *p_arg)
{
OS_ERR err;
CPU_INT32U r0;
CPU_INT32U r1;
CPU_INT32U r2;
CPU_INT32U r3;
CPU_INT32U r4;
CPU_INT32U r5;
CPU_INT32U r6;
CPU_INT32U r7;
CPU_INT32U r8;
CPU_INT32U r9;
CPU_INT32U r10;
CPU_INT32U r11;
CPU_INT32U r12;
(void)p_arg;
r0 = 0u; /* Initialize local variables. */
r1 = 1u;
r2 = 2u;
r3 = 3u;
r4 = 4u;
r5 = 5u;
r6 = 6u;
r7 = 7u;
r8 = 8u;
r9 = 9u;
r10 = 10u;
r11 = 11u;
r12 = 12u;
BSP_Init(); /* Initialize BSP functions */
CPU_Init(); /* Initialize the uC/CPU services */
#if OS_CFG_STAT_TASK_EN > 0u
OSStatTaskCPUUsageInit(&err); /* Compute CPU capacity with no task running */
#endif
#ifdef CPU_CFG_INT_DIS_MEAS_EN
CPU_IntDisMeasMaxCurReset();
#endif
#if (APP_CFG_SERIAL_EN == DEF_ENABLED)
App_SerialInit(); /* Initialize Serial Communication for Application ... */
#endif
APP_TRACE_DBG(("Creating Application kernel objects\n\r"));
AppObjCreate(); /* Create Applicaiton kernel objects */
APP_TRACE_DBG(("Creating Application Tasks\n\r"));
AppTaskCreate(); /* Create Application tasks */
BSP_LED_Off(0u);
while (DEF_TRUE) { /* Task body, always written as an infinite loop. */
BSP_LED_Toggle(0u);
OSTimeDlyHMSM(0u, 0u, 0u, 100u,
OS_OPT_TIME_HMSM_STRICT,
&err);
if ((r0 != 0u) || /* Check task context. */
(r1 != 1u) ||
(r2 != 2u) ||
(r3 != 3u) ||
(r4 != 4u) ||
(r5 != 5u) ||
(r6 != 6u) ||
(r7 != 7u) ||
(r8 != 8u) ||
(r9 != 9u) ||
(r10 != 10u) ||
(r11 != 11u) ||
(r12 != 12u)) {
APP_TRACE_INFO(("Context Error\n"));
}
}
}
unsigned char FM36_PDM_CLK_Set( unsigned char pdm_dac_clk, unsigned char pdm_adc_clk, unsigned char type )
{
unsigned char err ;
unsigned short data1,data2,data3 ;
if( flag_state_pwd ) return 0 ;
APP_TRACE_INFO(("\r\nConf FM36 PDMADC Clock = %dMHz\r\n", pdm_adc_clk));
switch ( pdm_adc_clk ) {
case 4 : //4.096
data3 = 0x0F;
data1 = 0xFA00;
break;
case 3 : //3.072
data3 = 0x13;
data1 = 0xBB80;
break;
case 2 : //2.048
data3 = 0x1B;
data1 = 0x7D00;
break;
case 1 : //1.024
data3 = 0x33;
data1 = 0x3E80;
break;
default ://2.048
APP_TRACE_INFO(("Not supported PDM ADC CLK, reset to default 2.048MHz\r\n"));
data3 = 0x1B;
data1 = 0x7D00;
break;
}
APP_TRACE_INFO(("\r\nConf FM36 PDMDAC Clock = %dMHz\r\n", pdm_dac_clk));
switch ( pdm_dac_clk ) {
case 4 : //4.096
data2 = 0xFA00;
break;
case 3 : //3.072
data2 = 0xBB80;
break;
case 2 : //2.048
data2 = 0x7D00;
break;
case 1 : //1.024
data2 = 0x3E80;
break;
default ://1.024
APP_TRACE_INFO(("Not supported PDM ADC CLK, reset to default 1.024MHz\r\n"));
data2 = 0x3E80;
break;
}
if( type == 0 ) { //para set before run
err = DM_SingleWrite( FM36_I2C_ADDR, 0x2267, data1 ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x226A, data2 ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x2266, data3 ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
} else { //on the fly check
err = DM_SingleWrite( FM36_I2C_ADDR, 0x3FD5, data1 ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x3FCD, data2 ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x3FED, data3 ) ;
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
err = DM_LegacyRead( FM36_I2C_ADDR, 0x3FE4,(unsigned char *)&data1 ) ;
if( OS_ERR_NONE != err ) {
err = FM36_RD_DM_ERR;
return err ;
}
err = DM_SingleWrite( FM36_I2C_ADDR, 0x3FE4, data1) ;// must rewrite 3fe4 to setting PLL.
if( OS_ERR_NONE != err ) {
return FM36_WR_DM_ERR;;
}
}
return err;
}
/*
*********************************************************************************************************
* Init_FM36_AB03()
*
* Description : Initialize FM36 DSP on AB03 board.
* Argument(s) : sr : sample rate : 8000 ~ 48000
* mic_num : 0~6
* lin_sp_index : line in data source: 0 ~ 1
* start_slot_index: line in data slot: 0 ~ 7
* bit_length: 16bit/32bit mode
* i2s_tdm_sel: 0 - I2S, 1 - TDM-I2S
* force_reset: 1 - force reset FM36
* Return(s) : NO_ERR : execute successfully
* others : =error code .
*
* Note(s) : None.
*********************************************************************************************************
*/
unsigned char Init_FM36_AB03( unsigned short sr,
unsigned char mic_num,
unsigned char lin_sp_index,
unsigned char start_slot_index,
unsigned char bit_length,
unsigned char i2s_tdm_sel,
unsigned char force_reset)
{
unsigned int i;
unsigned short temp, temp2 ;
unsigned short addr, val;
unsigned char err ;
//added for iM501 PCM clock pause issue
APP_TRACE_INFO(("\r\nInit_FM36_AB03:\r\n"));
if( Global_UIF_Setting[ UIF_TYPE_DUT_ID - 1 ].attribute == ATTRI_DUT_ID_IM501 ) { //make sure no unwanted FM36 reset whihc will casued iM501 PDMCLKI on/off
mic_num = 4 ;
}
APP_TRACE_INFO(("UIF_TYPE_DUT_ID = %d\r\n", Global_UIF_Setting[ UIF_TYPE_DUT_ID - 1 ].attribute));
if( sr == sr_saved && \
mic_num == mic_num_saved && \
lin_sp_index == lin_sp_index_saved && \
start_slot_index == start_slot_index_saved && \
bit_length == bit_length_saved && \
i2s_tdm_sel == i2s_tdm_sel_saved && \
force_reset == 0 )
{
APP_TRACE_INFO(("No need Re-Init FM36\r\n"));
return NO_ERR;
} else {
sr_saved = sr ;
mic_num_saved = mic_num ;
lin_sp_index_saved = lin_sp_index;
start_slot_index_saved = start_slot_index ;
bit_length_saved = bit_length;
i2s_tdm_sel_saved = i2s_tdm_sel;
}
Pin_Reset_FM36();
flag_state_pwd = false ;
// err = HOST_SingleWrite_2(FM36_I2C_ADDR, 0x0C, 2); //reset
// if( OS_ERR_NONE != err ) {
// return FM36_WR_HOST_ERR;
// }
// err = DM_LegacyRead( FM36_I2C_ADDR, 0x22FB,(unsigned char *)&temp ) ;
// if( OS_ERR_NONE != err ) {
// err = FM36_RD_DM_ERR;
// return err ;
// }
// APP_TRACE_INFO(("0x22FB = 0x%X\r\n", temp));
// err = DM_LegacyRead( FM36_I2C_ADDR, 0x2306,(unsigned char *)&temp ) ;
// if( OS_ERR_NONE != err ) {
// err = FM36_RD_DM_ERR;
// return err ;
// }
// APP_TRACE_INFO(("0x2306 = 0x%X\r\n", temp));
//
// err = HOST_SingleWrite_2(FM36_I2C_ADDR, 0x10, 0); //select FM36 DSP Core 0
// if( OS_ERR_NONE != err ) {
// return FM36_WR_HOST_ERR;
// }
//check chip type by rom id
err = CM_LegacyRead( FM36_I2C_ADDR, 0x2FFF,(unsigned char *)&temp ) ;
if( OS_ERR_NONE != err ) {
err = FM36_RD_CM_ERR;
return FM36_RD_CM_ERR ;
}
APP_TRACE_INFO(("ROM ID = 0x%X\r\n", temp));
if( temp != FM36_ROM_ID_2 ) {
return FM36_CHECK_ROMID_ERR; //dsp type error
}
//load FM36-600C patch code
if( flag_power_lose ) { //only need download patch once after one power cycle
flag_power_lose = false;
addr = (unsigned short)fm36_patch_code_3[0];
for( i = 1; i < sizeof(fm36_patch_code_3)/4; i++) {
Revert_patch_Endien(&fm36_patch_code_3[i]);
err = PM_SingleWrite( FM36_I2C_ADDR, addr++, (unsigned char*)&fm36_patch_code_3[i],0 ) ;
if( OS_ERR_NONE != err ) {
err = FM36_WR_PM_ERR;
return err ;
}
}
}
//load parameters
for( i = 0; i < sizeof(fm36_para_table_3)/4; i++) {
addr = fm36_para_table_3[i][0];
val = fm36_para_table_3[i][1];
if( addr == 0x22FB ) { //hit run flag para, do other inits before write it
err = Config_SP0_Out( mic_num );
if( OS_ERR_NONE != err ) {
return err ;
}
err = Config_Lin( lin_sp_index, start_slot_index );
if( OS_ERR_NONE != err ) {
return err ;
}
err = Config_SPx_Format( bit_length, i2s_tdm_sel );
if( OS_ERR_NONE != err ) {
return err ;
}
err = Config_SR( sr );
if( OS_ERR_NONE != err ) {
return err ;
}
err = FM36_PDM_CLK_Set( GET_BYTE_HIGH_4BIT(Global_UIF_Setting[ UIF_TYPE_FM36_PDMCLK - 1 ].attribute), GET_BYTE_LOW_4BIT(Global_UIF_Setting[ UIF_TYPE_FM36_PDMCLK - 1 ].attribute), 0 );
if( OS_ERR_NONE != err ) {
return err ;
}
err = Config_SP0IN_to_SP1Out();
if( OS_ERR_NONE != err ) {
return err ;
}
}
err = DM_SingleWrite( FM36_I2C_ADDR, addr, val ) ;
if( OS_ERR_NONE != err ) {
err = FM36_WR_DM_ERR;
return err ;
}
if( addr == 0x22FB ) { //if run chip, delay
OSTimeDly(100);
}
}
//check running status
err = DM_LegacyRead( FM36_I2C_ADDR, 0x2306,(unsigned char *)&temp2 ) ;
if( OS_ERR_NONE != err ) {
err = FM36_RD_DM_ERR;
return err ;
}
APP_TRACE_INFO(("0x2306 = 0x%X\r\n", temp2));
OSTimeDly(100);
err = DM_LegacyRead( FM36_I2C_ADDR, 0x22FB,(unsigned char *)&temp ) ;
if( OS_ERR_NONE != err ) {
err = FM36_RD_DM_ERR;
return err ;
}
APP_TRACE_INFO(("0x22FB = 0x%X\r\n", temp));
if( temp != 0x5A5A ) {
return FM36_CHECK_FLAG_ERR;
}
err = DM_LegacyRead( FM36_I2C_ADDR, 0x2306,(unsigned char *)&temp ) ;
if( OS_ERR_NONE != err ) {
err = FM36_RD_DM_ERR;
return err ;
}
APP_TRACE_INFO(("0x2306 = 0x%X\r\n", temp));
if( temp == temp2 ) {
APP_TRACE_INFO(("FM36 frame counter stopped !"));
return FM36_CHECK_COUNTER_ERR;
}
// if( Global_UIF_Setting[ UIF_TYPE_FM36_PATH - 1 ].attribute == ATTRI_FM36_PATH_PWD_BP ) {
// FM36_PWD_Bypass();
//
// }
return err;
}
