/*-------------------------------------------------------------------*/
void ARCH_DEP(perform_external_interrupt) (REGS *regs)
{
PSA *psa; /* -> Prefixed storage area */
U16 cpuad; /* Originating CPU address */
#if defined(FEATURE_VM_BLOCKIO)
#if defined(FEATURE_ESAME)
RADR servpadr; /* Address of 64-bit block I/O interrupt */
#endif
U16 servcode; /* Service Signal or Block I/O Interrupt code */
#endif /* defined(FEATURE_VM_BLOCKIO) */
/* External interrupt if console interrupt key was depressed */
if ( OPEN_IC_INTKEY(regs) && !SIE_MODE(regs) )
{
WRMSG (HHC00840, "I");
/* Reset interrupt key pending */
OFF_IC_INTKEY;
/* Generate interrupt key interrupt */
ARCH_DEP(external_interrupt) (EXT_INTERRUPT_KEY_INTERRUPT, regs);
}
/* External interrupt if malfunction alert is pending */
if (OPEN_IC_MALFALT(regs))
{
/* Find first CPU which generated a malfunction alert */
for (cpuad = 0; regs->malfcpu[cpuad] == 0; cpuad++)
{
if (cpuad >= sysblk.maxcpu)
{
OFF_IC_MALFALT(regs);
return;
}
} /* end for(cpuad) */
// /*debug*/ logmsg (_("External interrupt: Malfuction Alert from CPU %d\n"),
// /*debug*/ cpuad);
/* Reset the indicator for the CPU which was found */
regs->malfcpu[cpuad] = 0;
/* Store originating CPU address at PSA+X'84' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_HW(psa->extcpad,cpuad);
/* Reset emergency signal pending flag if there are
no other CPUs which generated emergency signal */
OFF_IC_MALFALT(regs);
while (++cpuad < sysblk.maxcpu)
{
if (regs->malfcpu[cpuad])
{
ON_IC_MALFALT(regs);
break;
}
} /* end while */
/* Generate emergency signal interrupt */
ARCH_DEP(external_interrupt) (EXT_MALFUNCTION_ALERT_INTERRUPT, regs);
}
/* External interrupt if emergency signal is pending */
if (OPEN_IC_EMERSIG(regs))
{
/* Find first CPU which generated an emergency signal */
for (cpuad = 0; regs->emercpu[cpuad] == 0; cpuad++)
{
if (cpuad >= sysblk.maxcpu)
{
OFF_IC_EMERSIG(regs);
return;
}
} /* end for(cpuad) */
// /*debug*/ logmsg (_("External interrupt: Emergency Signal from CPU %d\n"),
// /*debug*/ cpuad);
/* Reset the indicator for the CPU which was found */
regs->emercpu[cpuad] = 0;
/* Store originating CPU address at PSA+X'84' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_HW(psa->extcpad,cpuad);
/* Reset emergency signal pending flag if there are
no other CPUs which generated emergency signal */
OFF_IC_EMERSIG(regs);
while (++cpuad < sysblk.maxcpu)
{
if (regs->emercpu[cpuad])
{
ON_IC_EMERSIG(regs);
break;
}
} /* end while */
/* Generate emergency signal interrupt */
ARCH_DEP(external_interrupt) (EXT_EMERGENCY_SIGNAL_INTERRUPT, regs);
}
/* External interrupt if external call is pending */
if (OPEN_IC_EXTCALL(regs))
{
// /*debug*/logmsg (_("External interrupt: External Call from CPU %d\n"),
// /*debug*/ regs->extccpu);
/* Reset external call pending */
OFF_IC_EXTCALL(regs);
/* Store originating CPU address at PSA+X'84' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_HW(psa->extcpad,regs->extccpu);
/* Generate external call interrupt */
ARCH_DEP(external_interrupt) (EXT_EXTERNAL_CALL_INTERRUPT, regs);
}
/* External interrupt if TOD clock exceeds clock comparator */
if ( tod_clock(regs) > regs->clkc
&& OPEN_IC_CLKC(regs) )
{
if (CPU_STEPPING_OR_TRACING_ALL)
{
WRMSG (HHC00841, "I");
}
ARCH_DEP(external_interrupt) (EXT_CLOCK_COMPARATOR_INTERRUPT, regs);
}
/* External interrupt if CPU timer is negative */
if ( CPU_TIMER(regs) < 0
&& OPEN_IC_PTIMER(regs) )
{
if (CPU_STEPPING_OR_TRACING_ALL)
{
WRMSG (HHC00842, "I", CPU_TIMER(regs) << 8);
}
ARCH_DEP(external_interrupt) (EXT_CPU_TIMER_INTERRUPT, regs);
}
/* External interrupt if interval timer interrupt is pending */
#if defined(FEATURE_INTERVAL_TIMER)
if (OPEN_IC_ITIMER(regs)
#if defined(_FEATURE_SIE)
&& !(SIE_STATB(regs, M, ITMOF))
#endif /*defined(_FEATURE_SIE)*/
)
{
if (CPU_STEPPING_OR_TRACING_ALL)
{
WRMSG (HHC00843, "I");
}
OFF_IC_ITIMER(regs);
ARCH_DEP(external_interrupt) (EXT_INTERVAL_TIMER_INTERRUPT, regs);
}
#if defined(FEATURE_ECPSVM)
if ( OPEN_IC_ECPSVTIMER(regs) )
{
OFF_IC_ECPSVTIMER(regs);
ARCH_DEP(external_interrupt) (EXT_VINTERVAL_TIMER_INTERRUPT,regs);
}
#endif /*FEATURE_ECPSVM*/
#endif /*FEATURE_INTERVAL_TIMER*/
/* External interrupt if service signal is pending */
if ( OPEN_IC_SERVSIG(regs) && !SIE_MODE(regs) )
{
#if defined(FEATURE_VM_BLOCKIO)
/* Note: Both Block I/O and Service Signal are enabled by the */
/* the same CR0 bit. Hence they are handled in the same code */
switch(sysblk.servcode)
{
case EXT_BLOCKIO_INTERRUPT: /* VM Block I/O Interrupt */
if (sysblk.biodev->ccwtrace)
{
WRMSG (HHC00844, "I",
SSID_TO_LCSS(sysblk.biodev->ssid),
sysblk.biodev->devnum,
sysblk.servcode,
sysblk.bioparm,
sysblk.biostat,
sysblk.biosubcd
);
}
servcode = EXT_BLOCKIO_INTERRUPT;
#if defined(FEATURE_ESAME)
/* Real address used to store the 64-bit interrupt parameter */
#define VM_BLOCKIO_INT_PARM 0x11B8
if (sysblk.biosubcd == 0x07)
{
/* 8-byte interrupt parm */
if (CPU_STEPPING_OR_TRACING_ALL)
{
char buf[40];
MSGBUF(buf, "%16.16X", (unsigned) sysblk.bioparm);
WRMSG (HHC00845,"I", buf);
}
/* Set the main storage reference and change bits */
/* for 64-bit interruption parameter. */
/* Note: This is handled for the first 4K page in */
/* ARCH_DEP(external_interrupt), but not for the */
/* the second 4K page used for the 64-bit interrupt */
/* parameter. */
/* Point to 2nd page of PSA in main storage */
servpadr=APPLY_PREFIXING(VM_BLOCKIO_INT_PARM,regs->PX);
STORAGE_KEY(servpadr, regs)
|= (STORKEY_REF | STORKEY_CHANGE);
#if 0
/* Store the 64-bit interrupt parameter */
logmsg (_("Saving 64-bit Block I/O interrupt parm at "
"%16.16X: %16.16X\n"),
servpadr,
sysblk.bioparm
);
#endif
STORE_DW(regs->mainstor + servpadr,sysblk.bioparm);
psa = (void*)(regs->mainstor + regs->PX);
}
else
{
#endif /* defined(FEATURE_ESAME) */
/* 4-byte interrupt parm */
if (CPU_STEPPING_OR_TRACING_ALL)
{
char buf[40];
MSGBUF(buf, "%8.8X", (U32) sysblk.bioparm);
WRMSG (HHC00845,"I", buf);
}
/* Store Block I/O parameter at PSA+X'80' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_FW(psa->extparm,(U32)sysblk.bioparm);
#if defined(FEATURE_ESAME)
}
#endif
/* Store sub-interruption code and status at PSA+X'84' */
STORE_HW(psa->extcpad,(sysblk.biosubcd<<8)|sysblk.biostat);
/* Reset interruption data */
sysblk.bioparm = 0;
sysblk.biosubcd = 0;
sysblk.biostat = 0;
break;
case EXT_SERVICE_SIGNAL_INTERRUPT: /* Service Signal */
default:
servcode = EXT_SERVICE_SIGNAL_INTERRUPT;
/* Apply prefixing if the parameter is a storage address */
if ( (sysblk.servparm & SERVSIG_ADDR) )
sysblk.servparm =
APPLY_PREFIXING (sysblk.servparm, regs->PX);
if (CPU_STEPPING_OR_TRACING_ALL)
{
WRMSG (HHC00846,"I", sysblk.servparm);
}
/* Store service signal parameter at PSA+X'80' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_FW(psa->extparm,sysblk.servparm);
} /* end switch(sysblk.servcode) */
/* Reset service parameter */
sysblk.servparm = 0;
/* Reset service code */
sysblk.servcode = 0;
/* Reset service signal pending */
OFF_IC_SERVSIG;
/* Generate service signal interrupt */
ARCH_DEP(external_interrupt) (servcode, regs);
#else /* defined(FEATURE_VM_BLOCKIO) */
/* Apply prefixing if the parameter is a storage address */
if ( (sysblk.servparm & SERVSIG_ADDR) )
sysblk.servparm =
APPLY_PREFIXING (sysblk.servparm, regs->PX);
if (CPU_STEPPING_OR_TRACING_ALL)
{
WRMSG (HHC00846,"I", sysblk.servparm);
}
/* Store service signal parameter at PSA+X'80' */
psa = (void*)(regs->mainstor + regs->PX);
STORE_FW(psa->extparm,sysblk.servparm);
/* Reset service parameter */
sysblk.servparm = 0;
/* Reset service signal pending */
OFF_IC_SERVSIG;
/* Generate service signal interrupt */
ARCH_DEP(external_interrupt) (EXT_SERVICE_SIGNAL_INTERRUPT, regs);
#endif /* defined(FEATURE_VM_BLOCKIO) */
} /* end OPEN_IC_SERVSIG(regs) */
} /* end function perform_external_interrupt */
/*-------------------------------------------------------------------*/
int ARCH_DEP(system_reset) (int cpu, int clear)
{
int rc = 0;
REGS *regs;
/* Configure the cpu if it is not online */
if (!IS_CPU_ONLINE(cpu))
{
if (configure_cpu(cpu) != 0)
{
/* ZZ FIXME: we should probably present a machine-check
if we encounter any errors during the reset (rc != 0) */
return -1;
}
ASSERT(IS_CPU_ONLINE(cpu));
}
regs = sysblk.regs[cpu];
HDC1(debug_cpu_state, regs);
/* Perform system-reset-normal or system-reset-clear function */
if (!clear)
{
/* Reset external interrupts */
OFF_IC_SERVSIG;
OFF_IC_INTKEY;
/* Reset all CPUs in the configuration */
for (cpu = 0; cpu < MAX_CPU; cpu++)
if (IS_CPU_ONLINE(cpu))
if (ARCH_DEP(cpu_reset) (sysblk.regs[cpu]))
rc = -1;
/* Perform I/O subsystem reset */
io_reset ();
}
else
{
/* Reset external interrupts */
OFF_IC_SERVSIG;
OFF_IC_INTKEY;
/* Reset all CPUs in the configuration */
for (cpu = 0; cpu < MAX_CPU; cpu++)
{
if (IS_CPU_ONLINE(cpu))
{
regs=sysblk.regs[cpu];
if (ARCH_DEP(initial_cpu_reset) (regs))
{
rc = -1;
}
/* Clear all the registers (AR, GPR, FPR, VR)
as part of the CPU CLEAR RESET operation */
memset (regs->ar,0,sizeof(regs->ar));
memset (regs->gr,0,sizeof(regs->gr));
memset (regs->fpr,0,sizeof(regs->fpr));
#if defined(_FEATURE_VECTOR_FACILITY)
memset (regs->vf->vr,0,sizeof(regs->vf->vr));
#endif /*defined(_FEATURE_VECTOR_FACILITY)*/
}
}
/* Perform I/O subsystem reset */
io_reset ();
#if defined(FEATURE_LOAD_PROGRAM_PARAMETER_FACILITY)
/* Clear the program-parameter register */
sysblk.program_parameter = 0;
#endif /*defined(FEATURE_LOAD_PROGRAM_PARAMETER_FACILITY)*/
/* Clear storage */
sysblk.main_clear = sysblk.xpnd_clear = 0;
storage_clear();
xstorage_clear();
}
#if defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)
/* Set horizontal polarization */
sysblk.topology = TOPOLOGY_HORIZ;
/* Clear topology-change-report-pending condition */
sysblk.topchnge = 0;
#endif /*defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)*/
/* ZZ FIXME: we should probably present a machine-check
if we encounter any errors during the reset (rc != 0) */
return rc;
} /* end function system_reset */
/*-------------------------------------------------------------------*/
int ARCH_DEP(initial_cpu_reset) (REGS *regs)
{
/* Clear reset pending indicators */
regs->sigpireset = regs->sigpreset = 0;
/* Clear the registers */
memset ( ®s->psw, 0, sizeof(regs->psw) );
memset ( ®s->captured_zpsw, 0, sizeof(regs->captured_zpsw) );
memset ( regs->cr, 0, sizeof(regs->cr) );
regs->fpc = 0;
regs->PX = 0;
regs->psw.AMASK_G = AMASK24;
/*
* ISW20060125 : Since we reset the prefix, we must also adjust
* the PSA ptr
*/
regs->psa = (PSA_3XX *)regs->mainstor;
/* Perform a CPU reset (after setting PSA) */
ARCH_DEP(cpu_reset) (regs);
regs->todpr = 0;
regs->clkc = 0;
set_cpu_timer(regs, 0);
#ifdef _FEATURE_INTERVAL_TIMER
set_int_timer(regs, 0);
#endif
/* The breaking event address register is initialised to 1 */
regs->bear = 1;
/* Initialize external interrupt masks in control register 0 */
regs->CR(0) = CR0_XM_ITIMER | CR0_XM_INTKEY | CR0_XM_EXTSIG;
#ifdef FEATURE_S370_CHANNEL
/* For S/370 initialize the channel masks in CR2 */
regs->CR(2) = 0xFFFFFFFF;
#endif /*FEATURE_S370_CHANNEL*/
regs->chanset =
#if defined(FEATURE_CHANNEL_SWITCHING)
regs->cpuad < FEATURE_LCSS_MAX ? regs->cpuad :
#endif /*defined(FEATURE_CHANNEL_SWITCHING)*/
0xFFFF;
/* Initialize the machine check masks in control register 14 */
regs->CR(14) = CR14_CHKSTOP | CR14_SYNCMCEL | CR14_XDMGRPT;
#ifndef FEATURE_LINKAGE_STACK
/* For S/370 initialize the MCEL address in CR15 */
regs->CR(15) = 512;
#endif /*!FEATURE_LINKAGE_STACK*/
if(regs->host && regs->guestregs)
ARCH_DEP(initial_cpu_reset)(regs->guestregs);
#if defined(_FEATURE_MESSAGE_SECURITY_ASSIST)
renew_wrapping_keys();
#endif /*defined(_FEATURE_MESSAGE_SECURITY_ASSIST)*/
return 0;
} /* end function initial_cpu_reset */
/*-------------------------------------------------------------------*/
int ARCH_DEP(load_ipl) (U16 lcss, U16 devnum, int cpu, int clear)
{
REGS *regs; /* -> Regs */
DEVBLK *dev; /* -> Device control block */
int i; /* Array subscript */
BYTE unitstat; /* IPL device unit status */
BYTE chanstat; /* IPL device channel status */
/* Get started */
if (ARCH_DEP(common_load_begin) (cpu, clear) != 0)
return -1;
/* The actual IPL proper starts here... */
regs = sysblk.regs[cpu]; /* Point to IPL CPU's registers */
/* Point to the device block for the IPL device */
dev = find_device_by_devnum (lcss,devnum);
if (dev == NULL)
{
logmsg (_("HHCCP027E Device %4.4X not in configuration%s\n"),
devnum,
(sysblk.arch_mode == ARCH_370 ?
" or not connected to channelset" : ""));
HDC1(debug_cpu_state, regs);
return -1;
}
#if defined(OPTION_IPLPARM)
if(sysblk.haveiplparm)
{
for(i=0;i<16;i++)
{
regs->GR_L(i)=fetch_fw(&sysblk.iplparmstring[i*4]);
}
sysblk.haveiplparm=0;
}
#endif
/* Set Main Storage Reference and Update bits */
STORAGE_KEY(regs->PX, regs) |= (STORKEY_REF | STORKEY_CHANGE);
sysblk.main_clear = sysblk.xpnd_clear = 0;
/* Build the IPL CCW at location 0 */
regs->psa->iplpsw[0] = 0x02; /* CCW command = Read */
regs->psa->iplpsw[1] = 0; /* Data address = zero */
regs->psa->iplpsw[2] = 0;
regs->psa->iplpsw[3] = 0;
regs->psa->iplpsw[4] = CCW_FLAGS_CC | CCW_FLAGS_SLI;
/* CCW flags */
regs->psa->iplpsw[5] = 0; /* Reserved byte */
regs->psa->iplpsw[6] = 0; /* Byte count = 24 */
regs->psa->iplpsw[7] = 24;
/* Enable the subchannel for the IPL device */
dev->pmcw.flag5 |= PMCW5_E;
/* Build the operation request block */ /*@IWZ*/
memset (&dev->orb, 0, sizeof(ORB)); /*@IWZ*/
dev->busy = 1;
RELEASE_INTLOCK(NULL);
/* Execute the IPL channel program */
ARCH_DEP(execute_ccw_chain) (dev);
OBTAIN_INTLOCK(NULL);
/* Clear the interrupt pending and device busy conditions */
obtain_lock (&sysblk.iointqlk);
DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->ioint);
DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->pciioint);
DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->attnioint);
release_lock(&sysblk.iointqlk);
dev->busy = 0;
dev->scsw.flag2 = 0;
dev->scsw.flag3 = 0;
/* Check that load completed normally */
#ifdef FEATURE_S370_CHANNEL
unitstat = dev->csw[4];
chanstat = dev->csw[5];
#endif /*FEATURE_S370_CHANNEL*/
#ifdef FEATURE_CHANNEL_SUBSYSTEM
unitstat = dev->scsw.unitstat;
chanstat = dev->scsw.chanstat;
#endif /*FEATURE_CHANNEL_SUBSYSTEM*/
if (unitstat != (CSW_CE | CSW_DE) || chanstat != 0) {
logmsg (_("HHCCP029E %s mode IPL failed: CSW status=%2.2X%2.2X\n"
" Sense="),
get_arch_mode_string(regs), unitstat, chanstat);
for (i=0; i < (int)dev->numsense; i++)
{
logmsg ("%2.2X", dev->sense[i]);
if ((i & 3) == 3) logmsg(" ");
}
logmsg ("\n");
HDC1(debug_cpu_state, regs);
return -1;
}
#ifdef FEATURE_S370_CHANNEL
/* Test the EC mode bit in the IPL PSW */
if (regs->psa->iplpsw[1] & 0x08) {
/* In EC mode, store device address at locations 184-187 */
STORE_FW(regs->psa->ioid, dev->devnum);
} else {
/* In BC mode, store device address at locations 2-3 */
STORE_HW(regs->psa->iplpsw + 2, dev->devnum);
}
#endif /*FEATURE_S370_CHANNEL*/
#ifdef FEATURE_CHANNEL_SUBSYSTEM
/* Set LPUM */
dev->pmcw.lpum = 0x80;
STORE_FW(regs->psa->ioid, (dev->ssid<<16)|dev->subchan);
/* Store zeroes at locations 188-191 */
memset (regs->psa->ioparm, 0, 4);
#endif /*FEATURE_CHANNEL_SUBSYSTEM*/
/* Save IPL device number, cpu number and lcss */
sysblk.ipldev = devnum;
sysblk.iplcpu = regs->cpuad;
sysblk.ipllcss = lcss;
/* Finish up... */
return ARCH_DEP(common_load_finish) (regs);
} /* end function load_ipl */
