/*
function to adjust PRSSI value for CAC problem
*/
void
ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start)
{
u_int32_t val;
struct ath_hal_9300 *ahp = AH9300(ah);
bool asleep = ahp->ah_chip_full_sleep;
if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
ar9300_set_power_mode(ah, HAL_PM_AWAKE, true);
}
if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah) || AR_SREV_OSPREY(ah)) {
val = OS_REG_READ(ah, AR_PHY_RADAR_0);
if (start) {
val &= ~AR_PHY_RADAR_0_PRSSI;
val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI);
} else {
val &= ~AR_PHY_RADAR_0_PRSSI;
val |= SM(AR9300_DFS_PRSSI, AR_PHY_RADAR_0_PRSSI);
}
OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA);
ah->ah_use_cac_prssi = start;
}
if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, true);
}
}
void
ar9300_tx99_tgt_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype)
{
OS_REG_WRITE(ah, AR_PHY_TST_DAC_CONST, OS_REG_READ(ah, AR_PHY_TST_DAC_CONST) | (0x7ff<<11) | 0x7ff);
OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, OS_REG_READ(ah, AR_PHY_TEST_CTL_STATUS) | (1<<7) | (1<<1));
OS_REG_WRITE(ah, AR_PHY_ADDAC_PARA_CTL, (OS_REG_READ(ah, AR_PHY_ADDAC_PARA_CTL) | (1<<31) | (1<<15)) & ~(1<<13));
/* 11G mode */
if (!chtype)
{
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
| (0x1 << 3) | (0x1 << 2));
if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
& ~(0x1 << 4));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
| (0x1 << 26) | (0x7 << 24))
& ~(0x1 << 22));
} else {
OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
& ~(0x1 << 4));
OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, (OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
| (0x1 << 26) | (0x7 << 24))
& ~(0x1 << 22));
}
/* chain zero */
if((tx_chain_mask & 0x01) == 0x01) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
| (0x1 << 31) | (0x5 << 15)
| (0x3 << 9)) & ~(0x1 << 27)
& ~(0x1 << 12));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 7)) & ~(0x1 << 11));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
| (0x1 << 29) | (0x1 << 25)
| (0x1 << 23) | (0x1 << 19)
| (0x1 << 10) | (0x1 << 9)
| (0x1 << 8) | (0x1 << 3))
& ~(0x1 << 28)& ~(0x1 << 24)
& ~(0x1 << 22)& ~(0x1 << 7));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
| (0x1 << 23))& ~(0x1 << 21));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 6) | (0x1 << 5)
| (0x1 << 4) | (0x1 << 3)
| (0x1 << 2));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2)
| (0x1 << 31));
}
if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
/* chain one */
if ((tx_chain_mask & 0x02) == 0x02 ) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
| (0x1 << 31) | (0x5 << 15)
| (0x3 << 9)) & ~(0x1 << 27)
& ~(0x1 << 12));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 7)) & ~(0x1 << 11));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
| (0x1 << 29) | (0x1 << 25)
| (0x1 << 23) | (0x1 << 19)
| (0x1 << 10) | (0x1 << 9)
| (0x1 << 8) | (0x1 << 3))
& ~(0x1 << 28)& ~(0x1 << 24)
& ~(0x1 << 22)& ~(0x1 << 7));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
| (0x1 << 23))& ~(0x1 << 21));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 6) | (0x1 << 5)
| (0x1 << 4) | (0x1 << 3)
| (0x1 << 2));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2)
| (0x1 << 31));
}
}
if (AR_SREV_OSPREY(ah)) {
/* chain two */
if ((tx_chain_mask & 0x04) == 0x04 ) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
| (0x1 << 31) | (0x5 << 15)
| (0x3 << 9)) & ~(0x1 << 27)
& ~(0x1 << 12));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 7)) & ~(0x1 << 11));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
| (0x1 << 29) | (0x1 << 25)
| (0x1 << 23) | (0x1 << 19)
| (0x1 << 10) | (0x1 << 9)
| (0x1 << 8) | (0x1 << 3))
& ~(0x1 << 28)& ~(0x1 << 24)
& ~(0x1 << 22)& ~(0x1 << 7));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
| (0x1 << 23))& ~(0x1 << 21));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 6) | (0x1 << 5)
| (0x1 << 4) | (0x1 << 3)
| (0x1 << 2));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2)
| (0x1 << 31));
}
}
OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0x11111);
OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x111);
}
else
{
/* chain zero */
if((tx_chain_mask & 0x01) == 0x01) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
| (0x1 << 31) | (0x1 << 27)
| (0x3 << 23) | (0x1 << 19)
| (0x1 << 15) | (0x3 << 9))
& ~(0x1 << 12));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 7) | (0x1 << 3)
| (0x1 << 2) | (0x1 << 1))
& ~(0x1 << 11)& ~(0x1 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
| (0x1 << 29) | (0x1 << 25)
| (0x1 << 23) | (0x1 << 19)
| (0x1 << 10) | (0x1 << 9)
| (0x1 << 8) | (0x1 << 3))
& ~(0x1 << 28)& ~(0x1 << 24)
& ~(0x1 << 22)& ~(0x1 << 7));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
| (0x1 << 23))& ~(0x1 << 21));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2)
| (0x3 << 3) | (0x3 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3)
| (0x3 << 29) | (0x3 << 26)
| (0x2 << 23) | (0x2 << 20)
| (0x2 << 17))& ~(0x1 << 14));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 6) | (0x1 << 5)
| (0x1 << 4) | (0x1 << 3)
| (0x1 << 2));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2)
| (0x1 << 31));
if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
& ~(0x1 << 4));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
| (0x1 << 26) | (0x7 << 24)
| (0x3 << 22));
} else {
OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
& ~(0x1 << 4));
OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
| (0x1 << 26) | (0x7 << 24)
| (0x3 << 22));
}
if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
| (0x1 << 3) | (0x1 << 2)
| (0x1 << 1)) & ~(0x1 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
| (0x1 << 19) | (0x1 << 3));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
| (0x1 << 23));
}
if (AR_SREV_OSPREY(ah)) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
| (0x1 << 3) | (0x1 << 2)
| (0x1 << 1)) & ~(0x1 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
| (0x1 << 19) | (0x1 << 3));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
| (0x1 << 23));
}
}
if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
/* chain one */
if ((tx_chain_mask & 0x02) == 0x02 ) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
| (0x1 << 3) | (0x1 << 2)
| (0x1 << 1)) & ~(0x1 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
| (0x1 << 19) | (0x1 << 3));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
| (0x1 << 23));
if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
& ~(0x1 << 4));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
| (0x1 << 26) | (0x7 << 24)
| (0x3 << 22));
} else {
OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
& ~(0x1 << 4));
OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
| (0x1 << 26) | (0x7 << 24)
| (0x3 << 22));
}
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
| (0x1 << 31) | (0x1 << 27)
| (0x3 << 23) | (0x1 << 19)
| (0x1 << 15) | (0x3 << 9))
& ~(0x1 << 12));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 7) | (0x1 << 3)
| (0x1 << 2) | (0x1 << 1))
& ~(0x1 << 11)& ~(0x1 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
| (0x1 << 29) | (0x1 << 25)
| (0x1 << 23) | (0x1 << 19)
| (0x1 << 10) | (0x1 << 9)
| (0x1 << 8) | (0x1 << 3))
& ~(0x1 << 28)& ~(0x1 << 24)
& ~(0x1 << 22)& ~(0x1 << 7));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
| (0x1 << 23))& ~(0x1 << 21));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2)
| (0x3 << 3) | (0x3 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3)
| (0x3 << 29) | (0x3 << 26)
| (0x2 << 23) | (0x2 << 20)
| (0x2 << 17))& ~(0x1 << 14));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 6) | (0x1 << 5)
| (0x1 << 4) | (0x1 << 3)
| (0x1 << 2));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2)
| (0x1 << 31));
if (AR_SREV_OSPREY(ah)) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
| (0x1 << 3) | (0x1 << 2)
| (0x1 << 1)) & ~(0x1 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
| (0x1 << 19) | (0x1 << 3));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
| (0x1 << 23));
}
}
}
if (AR_SREV_OSPREY(ah)) {
/* chain two */
if ((tx_chain_mask & 0x04) == 0x04 ) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
| (0x1 << 3) | (0x1 << 2)
| (0x1 << 1)) & ~(0x1 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
| (0x1 << 19) | (0x1 << 3));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
| (0x1 << 23));
if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
& ~(0x1 << 4));
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
| (0x1 << 26) | (0x7 << 24)
| (0x3 << 22));
} else {
OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
& ~(0x1 << 4));
OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
| (0x1 << 26) | (0x7 << 24)
| (0x3 << 22));
}
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
| (0x1 << 3) | (0x1 << 2)
| (0x1 << 1)) & ~(0x1 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
| (0x1 << 19) | (0x1 << 3));
OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
| (0x1 << 23));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
| (0x1 << 31) | (0x1 << 27)
| (0x3 << 23) | (0x1 << 19)
| (0x1 << 15) | (0x3 << 9))
& ~(0x1 << 12));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 7) | (0x1 << 3)
| (0x1 << 2) | (0x1 << 1))
& ~(0x1 << 11)& ~(0x1 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
| (0x1 << 29) | (0x1 << 25)
| (0x1 << 23) | (0x1 << 19)
| (0x1 << 10) | (0x1 << 9)
| (0x1 << 8) | (0x1 << 3))
& ~(0x1 << 28)& ~(0x1 << 24)
& ~(0x1 << 22)& ~(0x1 << 7));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
| (0x1 << 23))& ~(0x1 << 21));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2)
| (0x3 << 3) | (0x3 << 0));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3)
| (0x3 << 29) | (0x3 << 26)
| (0x2 << 23) | (0x2 << 20)
| (0x2 << 17))& ~(0x1 << 14));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
| (0x1 << 12) | (0x1 << 10)
| (0x1 << 9) | (0x1 << 8)
| (0x1 << 6) | (0x1 << 5)
| (0x1 << 4) | (0x1 << 3)
| (0x1 << 2));
OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2)
| (0x1 << 31));
}
}
OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0x22222);
OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x222);
}
}
/*
* Enable radar detection and set the radar parameters per the
* values in pe
*/
void
ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{
u_int32_t val;
struct ath_hal_private *ahp = AH_PRIVATE(ah);
HAL_CHANNEL_INTERNAL *ichan = ahp->ah_curchan;
struct ath_hal_9300 *ah9300 = AH9300(ah);
bool asleep = ah9300->ah_chip_full_sleep;
int reg_writes = 0;
if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
ar9300_set_power_mode(ah, HAL_PM_AWAKE, true);
}
val = OS_REG_READ(ah, AR_PHY_RADAR_0);
val |= AR_PHY_RADAR_0_FFT_ENA | AR_PHY_RADAR_0_ENA;
if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_FIRPWR;
val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR);
}
if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_RRSSI;
val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI);
}
if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_HEIGHT;
val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT);
}
if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_PRSSI;
if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah) || AR_SREV_OSPREY(ah)) {
if (ah->ah_use_cac_prssi) {
val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI);
} else {
val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
}
} else {
val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
}
}
if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_INBAND;
val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND);
}
OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
val = OS_REG_READ(ah, AR_PHY_RADAR_1);
val |= AR_PHY_RADAR_1_MAX_RRSSI | AR_PHY_RADAR_1_BLOCK_CHECK;
if (pe->pe_maxlen != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_1_MAXLEN;
val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN);
}
if (pe->pe_relstep != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_1_RELSTEP_THRESH;
val |= SM(pe->pe_relstep, AR_PHY_RADAR_1_RELSTEP_THRESH);
}
if (pe->pe_relpwr != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_1_RELPWR_THRESH;
val |= SM(pe->pe_relpwr, AR_PHY_RADAR_1_RELPWR_THRESH);
}
OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);
if (ath_hal_getcapability(ah, HAL_CAP_EXT_CHAN_DFS, 0, 0) == HAL_OK) {
val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
if (IS_CHAN_HT40(ichan)) {
/* Enable extension channel radar detection */
OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val | AR_PHY_RADAR_EXT_ENA);
} else {
/* HT20 mode, disable extension channel radar detect */
OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val & ~AR_PHY_RADAR_EXT_ENA);
}
}
/*
apply DFS postamble array from INI
column 0 is register ID, column 1 is HT20 value, colum2 is HT40 value
*/
if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_OSPREY_22(ah) || AR_SREV_SCORPION(ah)) {
REG_WRITE_ARRAY(&ah9300->ah_ini_dfs,IS_CHAN_HT40(ichan)? 2:1, reg_writes);
}
#ifdef ATH_HAL_DFS_CHIRPING_FIX_APH128
HDPRINTF(ah, HAL_DBG_DFS,"DFS change the timing value\n");
if (AR_SREV_AR9580(ah) && IS_CHAN_HT40(ichan)) {
OS_REG_WRITE(ah, AR_PHY_TIMING6, 0x3140c00a);
}
#endif
if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, true);
}
}
