void spi_low_mst_init(void)
{
// Enable SPI clock
AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1 << AT91C_ID_SPI ) ;
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
//((unsigned int) AT91C_PA11_NPCS0) |
((unsigned int) AT91C_PA12_MISO ) |
((unsigned int) AT91C_PA13_MOSI ) |
((unsigned int) AT91C_PA14_SPCK ), // Periph A
0); // Periph B
AT91PS_SPI spi = AT91C_BASE_SPI;
// reset SPI and enable it
spi->SPI_CR = AT91C_SPI_SWRST;
spi->SPI_CR = AT91C_SPI_SWRST;
spi->SPI_CR = AT91C_SPI_SPIEN;
// SPI mode: master mode
// MODFDIS is required to allow manual CSx control
spi->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_PS_FIXED | AT91C_SPI_MODFDIS;
}
//*--------------------------------------------------------------------------------------
//* Function Name : AT91F_InitSdram
//* Object : Initialize the SDRAM
//* Input Parameters :
//* Output Parameters :
//*--------------------------------------------------------------------------------------
void AT91F_InitSdram()
{
int *pRegister;
AT91PS_SDRC pSdrc = AT91C_BASE_SDRC;
int i;
// Configure PIOC as peripheral (D16/D31)
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOC, // PIO controller base address
0xFFFF0000,
0
);
// Init SDRAM
// based on AT91Bootstrap for AT91SAM9260
/* 9 columns, 13 rows, 2 CAS, 4 banks, 32 bits,
* 2 TWR, 7 TRC, 2 TRP, 2 TRCD, 5 TRAS, 8 TXSR
*/
//pSdrc->SDRC_CR = 0x42913959;
/* default values
* 9 columns, 13 rows, 2 CAS, 4 banks, 32 bits,
* 2 TWR, 8 TRC, 3 TRP, 3 TRCD, 5 TRAS, 5 TXSR
*/
pSdrc->SDRC_CR = 0x2A99C159;
// sleep for a while
for (i =0; i< 1000;i++);
// precharge all
pSdrc->SDRC_MR = AT91C_SDRC_MODE_PRCGALL_CMD;
pRegister = (int *)(AT91C_SDRAM_BASE_ADDRESS);
*pRegister = 0;
// sleep for a while
for (i =0; i< 1000;i++);
// 8 auto refresh cycles
pSdrc->SDRC_MR = AT91C_SDRC_MODE_RFSH_CMD;
pRegister = (int *)(AT91C_SDRAM_BASE_ADDRESS);
for (i = 0; i < 8; i++)
*pRegister = 0;
// load mode register
pSdrc->SDRC_MR = AT91C_SDRC_MODE_LMR_CMD;
// mode is 0x20, but has to be shifted 2 bits left for 32-bit data bus width
// CAS latency = 2, (mode register bits 6:4)
pRegister = (int *)(AT91C_SDRAM_BASE_ADDRESS + 0x80);
*pRegister = 0;
// normal mode
pSdrc->SDRC_MR = AT91C_SDRC_MODE_NORMAL_CMD;
pRegister = (int *)(AT91C_SDRAM_BASE_ADDRESS);
*pRegister = 0;
// program refresh rate
// 8192 rows have to be refreshed each 64ms which gives refresh cycle every 7.8 microseconds
// 468 = 7.8us * MASTER_CLOCK / 1000000
pSdrc->SDRC_TR = 0x1D4;
}
void poti_init(void)
{
AT91F_SPI_CfgPMC();
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA,
AT91C_PA13_MOSI | AT91C_PA14_SPCK, 0);
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPICC_PIO_SS2_DT_THRESH);
AT91F_PIO_SetOutput(AT91C_BASE_PIOA, OPENPICC_PIO_SS2_DT_THRESH);
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPICC_PIO_nSLAVE_RESET);
poti_reset();
#if 0
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SPI,
OPENPCD_IRQ_PRIO_SPI,
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &spi_irq);
AT91G_AIC_EnableIt(AT9C_BASE_AIC, AT91C_ID_SPI);
#endif
AT91F_SPI_CfgMode(spi, AT91C_SPI_MSTR |
AT91C_SPI_PS_FIXED | AT91C_SPI_MODFDIS);
/* CPOL = 0, NCPHA = 1, CSAAT = 0, BITS = 0000, SCBR = 13 (3.69MHz),
* DLYBS = 6 (125nS), DLYBCT = 0 */
AT91F_SPI_CfgCs(spi, 0, AT91C_SPI_BITS_8 | AT91C_SPI_NCPHA |
(13 << 8) | (6 << 16));
AT91F_SPI_Enable(spi);
}
void soundInit( void ) {
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, SPI_PERIPH, 0x0); //Sets the output lines required for the SPI.
AT91F_SPI_CfgPMC(); // Enables the SPI periphial clock.
AT91F_SPI_CfgMode (AT91C_BASE_SPI, SPI_MODE); //Sets the SPI's mode.
AT91F_SPI_CfgCs(AT91C_BASE_SPI, 0, CS_REG); // Sets the clients settings.
AT91F_SPI_Enable(AT91C_BASE_SPI); // Enables the SPI.
}
void tc_fdt_init(void)
{
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, AT91C_PA15_TF,
AT91C_PA26_TIOA2 | AT91C_PA27_TIOB2);
AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
((unsigned int) 1 << AT91C_ID_TC2));
/* Enable Clock for TC2 */
tcfdt->TC_CCR = AT91C_TC_CLKEN;
/* Clock XC1, Wave Mode, No automatic reset on RC comp
* TIOA2 in RA comp = set, TIOA2 on RC comp = clear,
* TIOA2 on EEVT = clear, TIOA2 on SWTRG = clear,
* TIOB2 as input, EEVT = TIOB2, Reset/Trigger on EEVT */
tcfdt->TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE |
AT91C_TC_WAVESEL_UP |
AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR |
AT91C_TC_AEEVT_CLEAR | AT91C_TC_ASWTRG_CLEAR |
AT91C_TC_BEEVT_NONE | AT91C_TC_BCPB_NONE |
AT91C_TC_EEVT_TIOB | AT91C_TC_ETRGEDG_FALLING |
AT91C_TC_ENETRG | AT91C_TC_CPCSTOP ;
tcfdt->TC_RC = 0xffff;
/* Reset to start timers */
tcb->TCB_BCR = 1;
AT91F_AIC_ConfigureIt(AT91C_ID_TC2,
OPENPCD_IRQ_PRIO_TC_FDT,
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, (THandler)&tc_fdt_irq);
tcfdt->TC_IER = AT91C_TC_CPCS | AT91C_TC_ETRGS;
AT91F_AIC_ClearIt(AT91C_ID_TC2);
AT91F_AIC_EnableIt(AT91C_ID_TC2);
}
void tc0_tc1_interval_init(void)
{
/* Cfg PA28(TCLK1), and PA0 (TIOA0) as peripheral B */
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0,
AT91C_PA28_TCLK1|AT91C_PA0_TIOA0 );
/* Enable peripheral Clock for TC0 and TC1 */
AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
((unsigned int) 1 << AT91C_ID_TC0));
AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
((unsigned int) 1 << AT91C_ID_TC1));
/* Enable Clock for TC0 and TC1 */
tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKEN;
tcb->TCB_TC1.TC_CCR = AT91C_TC_CLKEN;
/* Connect TCLK1 to XC1, TIOA1 to XC0, so TC0 and 1 are chained */
tcb->TCB_BMR &= ~(AT91C_TCB_TC1XC1S | AT91C_TCB_TC0XC0S);
tcb->TCB_BMR |= (AT91C_TCB_TC1XC1S_TCLK1 | AT91C_TCB_TC0XC0S_TIOA1);
/*TC1 is set to waveform mode, 128 divider, 50% dutycycle waveform*/
//WAVSEL=10, RC=128,
tcb->TCB_TC1.TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE | //runs from XC1, waveform mode
AT91C_TC_WAVESEL_UP_AUTO | //up counting and auto reset on RC compare
AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR | //RA compare sets TIOA1, RC compare clears TIOA
AT91C_TC_BEEVT_NONE | AT91C_TC_BCPB_NONE | //TIOB1 external event not used, RB compare not rounted out
AT91C_TC_EEVT_TIOB | AT91C_TC_ETRGEDG_NONE | //External event set to TIOB1, but not used (None edge)
AT91C_TC_BSWTRG_CLEAR | AT91C_TC_ASWTRG_CLEAR; //SW trigger resets TIOA, TIOB
tcb->TCB_TC1.TC_RC = 31;//128 divider,
tcb->TCB_TC1.TC_RA = 16;//50 duty cycle
tcb->TCB_TC1.TC_RB = 0xFFFF;//RB setting is useless since RB not used at all
/*TC0 is set to waveform mode, 65536 divider, 50% dutycycle waveform*/
tcb->TCB_TC0.TC_CMR = AT91C_TC_CLKS_XC0 | AT91C_TC_WAVE | //runs from XC0, waveform mode
AT91C_TC_WAVESEL_UP | //up counting and auto reset on 0xFFFF compare
AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR | //RA compare sets TIOA0, RC compare clears TIOA0
AT91C_TC_BEEVT_NONE | AT91C_TC_BCPB_NONE | //TIOB1 external event not used, RB compare not rounted out
AT91C_TC_EEVT_TIOB | AT91C_TC_ETRGEDG_NONE | //External event set to TIOB1, but not used (None edge)
AT91C_TC_BSWTRG_CLEAR | AT91C_TC_ASWTRG_CLEAR; //SW trigger resets TIOA, TIOB
tcb->TCB_TC0.TC_RC = 0xFFFE;//no use at all
tcb->TCB_TC0.TC_RA = 32769;//50 duty cycle for RA compare
tcb->TCB_TC0.TC_RB = 0xFFFF;//RB setting is useless since RB not used at all
tcb->TCB_TC0.TC_IDR = 0xFF; //first disable all TC0 interrupts
tcb->TCB_TC0.TC_IER = AT91C_TC_COVFS;//Enable the counter overflow interrupt
tcb->TCB_BCR = 1;/* Reset to start timers */
/*register the interrupt handler*/
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_TC0,
OPENPCD_IRQ_PRIO_TC0,
AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE, &tc0_irq);
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_TC0);
proc_status = IDLE;
params_to_proc = NULL;
}
void Init_PWM(void)
{
AT91F_PWMC_InterruptDisable(AT91C_BASE_PWMC, AT91C_PWMC_CHID0);
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA );
AT91F_PWMC_CH0_CfgPIO();
AT91F_PWMC_CfgPMC();
AT91F_PWMC_StopChannel(AT91C_BASE_PWMC, AT91C_PWMC_CHID0);
AT91F_PWMC_CfgChannel(AT91C_BASE_PWMC, 0, 1 | AT91C_PWMC_CPOL, 100000, 66000);
AT91F_PWMC_UpdateChannel(AT91C_BASE_PWMC, AT91C_PWMC_CHID0, 0);
AT91F_PWMC_StopChannel(AT91C_BASE_PWMC, AT91C_PWMC_CHID0);
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0, AT91C_PA23_PWM0);
AT91F_PWMC_StartChannel(AT91C_BASE_PWMC, AT91C_PWMC_CHID0);
}
//----------------------------------------------------------------------------
// Функция инициализации PWM
//----------------------------------------------------------------------------
void AT91F_PWM_Open(U8 SIGN_SINHR, U8 DIVIDER)
{
//Разрешение выхода PWM в контроллере PIO (PA11, канал 0 PWM)
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0, AT91C_PA11_PWM0);
//Разрешение синхронизации PWM
AT91F_PWMC_CfgPMC ();
//Остановка канала 0 PWM
AT91F_PWMC_StopChannel(AT91C_BASE_PWMC,AT91C_PWMC_CHID0);
//Установки делителя A (выбор источника синхрочастоты и задание коэфф деления делителя)
AT91C_BASE_PWMC->PWMC_MR = (( SIGN_SINHR << 8 ) | DIVIDER);
}
int main(void)
{
/* initialize LED and debug unit */
led_init();
sysirq_init();
AT91F_DBGU_Init();
AT91F_PIOA_CfgPMC();
wdt_init();
pit_init();
blinkcode_init();
/* initialize USB */
req_ctx_init();
usbcmd_gen_init();
udp_open();
/* call application specific init function */
_init_func();
// Enable User Reset and set its minimal assertion to 960 us
AT91C_BASE_RSTC->RSTC_RMR =
AT91C_RSTC_URSTEN | (0x4 << 8) | (unsigned int)(0xA5 << 24);
#ifdef DEBUG_CLOCK_PA6
AT91F_PMC_EnablePCK(AT91C_BASE_PMC, 0, AT91C_PMC_CSS_PLL_CLK);
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0, AT91C_PA6_PCK0);
#endif
/* switch on first led */
led_switch(2, 1);
DEBUGPCRF("entering main (idle) loop");
while (1) {
/* Call application specific main idle function */
_main_func();
dbgu_rb_flush();
/* restart watchdog timer */
wdt_restart();
#ifdef CONFIG_IDLE
//cpu_idle();
#endif
}
}
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
xComPortHandle xReturn = serHANDLE;
extern void ( vUART_ISR )( void );
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* If the queues were created correctly then setup the serial port
hardware. */
if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
{
portENTER_CRITICAL();
{
/* Enable the USART clock. */
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_US0 );
AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, ( ( unsigned long ) AT91C_PA5_RXD0 ) | ( ( unsigned long ) AT91C_PA6_TXD0 ), serNO_PERIPHERAL_B_SETUP );
/* Set the required protocol. */
AT91F_US_Configure( serCOM0, configCPU_CLOCK_HZ, AT91C_US_ASYNC_MODE, ulWantedBaud, serNO_TIMEGUARD );
/* Enable Rx and Tx. */
serCOM0->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
/* Enable the Rx interrupts. The Tx interrupts are not enabled
until there are characters to be transmitted. */
AT91F_US_EnableIt( serCOM0, AT91C_US_RXRDY );
/* Enable the interrupts in the AIC. */
AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_US0, serINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vSerialISREntry );
AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_US0 );
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
/* This demo file only supports a single port but we have to return
something to comply with the standard demo header file. */
return xReturn;
}
unsigned char nRFCMD_Init(void)
{
volatile int dummy;
const int SCBR = ((int)(MCK / 8e6) + 1)&0xFF;
nRFCMD_Macro=nRFCMD_MacroResult=NULL;
vSemaphoreCreateBinary(xnRF_SemaphoreDMA);
vSemaphoreCreateBinary(xnRF_SemaphoreACK);
if(!(xnRF_SemaphoreDMA && xnRF_SemaphoreACK))
return 1;
xSemaphoreTake(xnRF_SemaphoreDMA,0);
xSemaphoreTake(xnRF_SemaphoreACK,0);
AT91F_SPI_CfgPMC();
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, NRF_SPI_PINS_PERIPHERAL_A, NRF_SPI_PINS_PERIPHERAL_B);
AT91F_PIO_CfgInput(AT91C_BASE_PIOA, IRQ_PIN);
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, CE_PIN);
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, CE_PIN);
portENTER_CRITICAL();
/* CPOL = 0, NCPHA = 1, CSAAT = 0, BITS = 0000, SCBR = <8MHz,
* DLYBS = 0, DLYBCT = 0 */
AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_PS_FIXED;
AT91F_SPI_CfgCs(AT91C_BASE_SPI, 0, AT91C_SPI_BITS_8|AT91C_SPI_NCPHA|(SCBR<<8));
AT91F_SPI_Enable(AT91C_BASE_SPI);
AT91F_AIC_ConfigureIt(AT91C_ID_SPI, 4, AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE, nRFCMD_ISR_DMA );
AT91C_BASE_SPI->SPI_IER = AT91C_SPI_ENDTX;
/* Enable PIO interrupt for IRQ pin */
AT91F_AIC_ConfigureIt(AT91C_ID_PIOA, 3, AT91C_AIC_SRCTYPE_HIGH_LEVEL, nRFCMD_ISR_ACK );
/* reset IRQ status */
dummy = AT91C_BASE_PIOA->PIO_ISR;
AT91C_BASE_PIOA->PIO_IER = IRQ_PIN;
AT91C_BASE_AIC->AIC_IECR = (0x1 << AT91C_ID_SPI) | (0x1 << AT91C_ID_PIOA) ;
portEXIT_CRITICAL();
return 0;
}
void spi_low_slv_init(void)
{
// Enable SPI clock
AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1 << AT91C_ID_SPI ) ;
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
//((unsigned int) AT91C_PA11_NPCS0) |
((unsigned int) AT91C_PA12_MISO ) |
((unsigned int) AT91C_PA13_MOSI ) |
((unsigned int) AT91C_PA14_SPCK ), // Periph A
0); // Periph B
AT91PS_SPI spi = AT91C_BASE_SPI;
// SPI mode: slave mode
spi->SPI_MR = 0;
// CS0: 8 bits
spi->SPI_CSR[0] = AT91C_SPI_BITS_8;
}
void tc_cdiv_init(void)
{
/* Cfg PA28(TCLK1), PA0(TIOA0), PA1(TIOB0), PA20(TCLK2) as Periph B */
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0,
OPENPCD_PIO_CARRIER_IN |
OPENPCD_PIO_CARRIER_DIV_OUT |
OPENPCD_PIO_CDIV_HELP_OUT |
OPENPCD_PIO_CDIV_HELP_IN);
AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
((unsigned int) 1 << AT91C_ID_TC0));
/* Enable Clock for TC0 and TC1 */
tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKEN;
tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKEN;
/* Connect TCLK1 to XC1, TCLK2 to XC2 */
tcb->TCB_BMR &= ~(AT91C_TCB_TC1XC1S | AT91C_TCB_TC2XC2S);
tcb->TCB_BMR |= (AT91C_TCB_TC1XC1S_TCLK1 | AT91C_TCB_TC2XC2S_TCLK2);
/* Clock XC1, Wave mode, Reset on RC comp
* TIOA0 on RA comp = set, * TIOA0 on RC comp = clear,
* TIOB0 on EEVT = set, TIOB0 on RB comp = clear,
* EEVT = XC2 (TIOA0) */
tcb->TCB_TC0.TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE |
AT91C_TC_WAVESEL_UP_AUTO |
AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR |
AT91C_TC_BEEVT_SET | AT91C_TC_BCPB_CLEAR |
AT91C_TC_EEVT_XC2 | AT91C_TC_ETRGEDG_RISING |
AT91C_TC_BSWTRG_CLEAR | AT91C_TC_ASWTRG_CLEAR;
tc_cdiv_set_divider(128);
/* Reset to start timers */
tcb->TCB_BCR = 1;
}
int _main_dbgu(char key)
{
switch (key) {
case 'o':
if (duty_percent >= 1)
duty_percent--;
pwm_duty_set_percent(0, duty_percent);
break;
case 'p':
if (duty_percent <= 99)
duty_percent++;
pwm_duty_set_percent(0, duty_percent);
break;
case 'k':
pwm_stop(0);
break;
case 'l':
pwm_start(0);
break;
case 'n':
if (pwm_freq_idx > 0) {
pwm_freq_idx--;
pwm_stop(0);
pwm_freq_set(0, pwm_freq[pwm_freq_idx]);
pwm_start(0);
pwm_duty_set_percent(0, 22); /* 22% of 9.43uS = 2.07uS */
}
break;
case 'm':
if (pwm_freq_idx < ARRAY_SIZE(pwm_freq)-1) {
pwm_freq_idx++;
pwm_stop(0);
pwm_freq_set(0, pwm_freq[pwm_freq_idx]);
pwm_start(0);
pwm_duty_set_percent(0, 22); /* 22% of 9.43uS = 2.07uS */
}
break;
case 'u':
DEBUGPCRF("PA23 output high");
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, AT91C_PIO_PA23);
AT91F_PIO_SetOutput(AT91C_BASE_PIOA, AT91C_PIO_PA23);
break;
case 'y':
DEBUGPCRF("PA23 output low");
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, AT91C_PIO_PA23);
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, AT91C_PIO_PA23);
return 0;
break;
case 't':
DEBUGPCRF("PA23 PeriphA (PWM)");
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0, AT91C_PA23_PWM0);
return 0;
break;
case 'f':
DEBUGPCRF("%sabling Force100ASK", force_100ask ? "Dis":"En");
if (force_100ask) {
force_100ask = 0;
opcd_rc632_clear_bits(RAH, RC632_REG_TX_CONTROL,
RC632_TXCTRL_FORCE_100_ASK);
} else {
force_100ask = 1;
opcd_rc632_set_bits(RAH, RC632_REG_TX_CONTROL,
RC632_TXCTRL_FORCE_100_ASK);
}
return 0;
break;
case 'v':
if (mod_conductance > 0) {
mod_conductance--;
opcd_rc632_reg_write(RAH, RC632_REG_MOD_CONDUCTANCE,
rsrel_table[mod_conductance]);
}
break;
case 'b':
if (mod_conductance < 0x3f) {
mod_conductance++;
opcd_rc632_reg_write(RAH, RC632_REG_MOD_CONDUCTANCE,
rsrel_table[mod_conductance]);
}
break;
case 'g':
if (cw_conductance > 0) {
cw_conductance--;
opcd_rc632_reg_write(RAH, RC632_REG_CW_CONDUCTANCE,
rsrel_table[cw_conductance]);
}
break;
case 'h':
if (cw_conductance < 0x3f) {
cw_conductance++;
opcd_rc632_reg_write(RAH, RC632_REG_CW_CONDUCTANCE,
rsrel_table[cw_conductance]);
}
break;
case '?':
help();
return 0;
break;
case '<':
tc_cdiv_phase_inc();
break;
case '>':
tc_cdiv_phase_dec();
break;
case '{':
if (cdiv_idx > 0)
cdiv_idx--;
tc_cdiv_set_divider(cdivs[cdiv_idx]);
break;
case '}':
if (cdiv_idx < ARRAY_SIZE(cdivs)-1)
cdiv_idx++;
tc_cdiv_set_divider(cdivs[cdiv_idx]);
break;
#ifdef SSC
case 's':
ssc_rx_start();
break;
case 'S':
ssc_rx_stop();
break;
#endif
default:
return -EINVAL;
}
DEBUGPCR("pwm_freq=%u, duty_percent=%u, mod_cond=%u, cw_cond=%u tc_cdiv=%u",
pwm_freq[pwm_freq_idx], duty_percent, mod_conductance, cw_conductance,
cdivs[cdiv_idx]);
return 0;
}
//===============================================================================================
void AT91F_USART_OPEN(AT91_USART_ID idPort, long BaudRate, int mode)
{
portENTER_CRITICAL();
{
switch (idPort)
{
case AT91_USART_COM0_ID:
COM0.id = idPort;
COM0.hPort = AT91C_BASE_US0;
COM0.hError = ErrorCreate("US0_Error");
COM0.hPDC = AT91C_BASE_PDC_US0;
AT91F_PDC_Open(COM0.hPDC);
// AT91F_US0_CfgPIO(); //* Define RXD and TXD as peripheral
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, // PIO controller base address
(((unsigned int) AT91C_PA5_RXD0)
| ((unsigned int) AT91C_PA6_TXD0)), // Peripheral A
0);
AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, 1 << AT91C_ID_US0); // First, enable the clock of the PIOB
AT91F_US_Configure(COM0.hPort, MCK, mode, BaudRate, 0); // Usart Configure
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_US0,
USART_INTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
(void(*)(void)) AT91_US0_ISR_ENTRY);
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_US0);
COM0.hRxQueue = xQueueCreate(1, sizeof(int));
while (COM0.hRxQueue == 0)
; // Queue was not created and must not be used.
COM0.hTxQueue = xQueueCreate(1, sizeof(int));
while (COM0.hTxQueue == 0)
; // Queue was not created and must not be used.
break;
case AT91_USART_COM1_ID:
COM1.id = idPort;
COM1.hPort = AT91C_BASE_US1;
COM1.hPDC = AT91C_BASE_PDC_US1;
COM1.hError = ErrorCreate("US1_Error");
AT91F_PDC_DisableTx(COM1.hPDC);
AT91F_PDC_DisableRx(COM1.hPDC);
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, // PIO controller base address
(((unsigned int) AT91C_PA21_RXD1)
| ((unsigned int) AT91C_PA22_TXD1)), // Peripheral A
0);
AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, 1 << AT91C_ID_US1); // First, enable the clock of the PIOB
AT91F_US_Configure(COM1.hPort, MCK, mode, BaudRate, 0); // Usart Configure
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_US1,
USART_INTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
(void(*)(void)) AT91_US1_ISR_ENTRY);
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_US1);
COM1.hRxQueue = xQueueCreate(1, sizeof(int));
while (COM1.hRxQueue == 0)
; // Queue was not created and must not be used.
COM1.hTxQueue = xQueueCreate(1, sizeof(int));
while (COM1.hTxQueue == 0)
; // Queue was not created and must not be used.
break;
default:
while (1)
;// error port notfound;
}
}
portEXIT_CRITICAL();
}
////////////////////////////////////////////////////////////////////////////////
// Konfiguracja USART0 w trybie DMA (DMA tylko do nadawania)
// Odbi�r danych za pomoc� przerwania
////////////////////////////////////////////////////////////////////////////////
void UART0_DMA_Configure(unsigned long baudrate) {
float podzielnik_float;
int calkowity, ulamkowy;
unsigned int mode = AT91C_US_USMODE_NORMAL | /* Normal Mode */
AT91C_US_CLKS_CLOCK | /* Clock = MCK */
AT91C_US_CHRL_8_BITS | /* 8-bit Data */
AT91C_US_PAR_NONE | /* No Parity */
AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */
//W��czenie zegara dla UART0
PMC_EnablePeripheral(AT91C_ID_US0);
// AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1 << AT91C_ID_US0 );
USART_Configure(AT91C_BASE_US0, mode, baudrate, BOARD_MCK);
//wylaczenie przyjmowania przerwan
AT91C_BASE_US0->US_IDR = 0xFFFFFFFF;
USART_SetReceiverEnabled(AT91C_BASE_US0, 0);
USART_SetTransmitterEnabled(AT91C_BASE_US0, 0);
// //reset portu
// AT91C_BASE_US0->US_CR = AT91C_US_RSTRX | /* Reset Receiver */
// AT91C_US_RSTTX | /* Reset Transmitter */
// AT91C_US_RXDIS | /* Receiver Disable */
// AT91C_US_TXDIS; /* Transmitter Disable */
//wylaczenie DMA
PDC_Disable(AT91C_BASE_PDC_US0);
// //konfiguracja USART0
// AT91C_BASE_US0->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */
// AT91C_US_CLKS_CLOCK | /* Clock = MCK */
// AT91C_US_CHRL_8_BITS | /* 8-bit Data */
// AT91C_US_PAR_NONE | /* No Parity */
// AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */
//predkosc
//AT91C_BASE_US0->US_BRGR = (MCK/16/baudrate);
//wyliczenie podzielnikow zegara MCLK
podzielnik_float = ((float) MCK / 16.0 / (float) baudrate);
calkowity = podzielnik_float;
podzielnik_float = (podzielnik_float - calkowity) * 8;
ulamkowy = podzielnik_float;
AT91C_BASE_US0->US_BRGR = (calkowity) | (ulamkowy << 16); /* podzielnik calkowity + podzielnik ulamkowy */
//konfiguracja przerwania
AIC_ConfigureIT(AT91C_ID_US0, 0x3 | AT91C_AIC_SRCTYPE_HIGH_LEVEL,
UART0_DMA_irq_handler);
// AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, AT91C_ID_US0, 0x3, AT91C_AIC_SRCTYPE_HIGH_LEVEL, UART0_DMA_irq_handler);
AIC_EnableIT(AT91C_ID_US0);
// AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_US0);
//w��czenie USART0
USART_SetReceiverEnabled(AT91C_BASE_US0, 1);
USART_SetTransmitterEnabled(AT91C_BASE_US0, 1);
// AT91C_BASE_US0->US_CR = AT91C_US_RXEN | /* Receiver Enable */
// AT91C_US_TXEN; /* Transmitter Enable */
//wlaczenie DMA (nadawanie)
PDC_Enable(AT91C_BASE_PDC_US0);
//konfiguracja wyprowadzen
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, (AT91C_PA5_RXD0 | AT91C_PA6_TXD0), 0);
//wlaczenie przerwania od odbiornika
AT91C_BASE_US0->US_IER = (0x1 << 0); //RXRDY
}
__noreturn int main()
{
s16 result;
u32 ul;
__disable_interrupt();
//*** Hardware Init ***
/* When using the JTAG debugger the hardware is not always initialised to
the correct default state. This line just ensures that this does not
cause all interrupts to be masked at the start. */
AT91C_BASE_AIC->AIC_EOICR = 0;
/* Enable the peripheral clock. */
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA );
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOB ) ;
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_EMAC ) ;
// This Pull ups are disabled
*AT91C_PIOB_PPUDR = (AT91C_PIO_PB5|AT91C_PIO_PB6|AT91C_PIO_PB13|AT91C_PIO_PB14|AT91C_PIO_PB26);
AT91F_PIO_CfgPeriph(PIOA, 0, 0);
AT91F_PIO_CfgPeriph(PIOB, 0, 0);
CLR_PIN(PIOB, AT91C_PB18_EF100);
SET_OUTPUT(PIOA, AT91C_PA22_TK|AT91C_PA21_TF|AT91C_PA0_RXD0);
SET_OUTPUT(PIOB, AT91C_PIO_PB21);
// Release Reset of the CODEC
NET_init(RX_buf, TX_buf);
EMAC_Init();
__enable_interrupt();
u8 buf[10];
buf[0] = 0x03;
buf[1] = 0x4B;
I2C_Init(100);
CODEC_init();
RING_init(_CODEC_DATA_START_ADR, _CODEC_DATABLOCK_SIZE, _CODEC_NUM_OF_BUFS);
// Init the UWSDR sub system
UWSDR_init();
//CODEC_start();
//*********** THE MAIN LOOP ************
_DBG_STATE_POS(_DBG_STATE_MAIN);
while(1) {
result = EMAC_Poll();
_DBG_STATE_POS(_DBG_STATE_MAIN);
if(result == _NET_GOT_RX_DATA) {
NET_process();
}
_DBG_STATE_POS(_DBG_STATE_MAIN);
ul = AT91C_BASE_SSC->SSC_SR;
if((ul & AT91C_SSC_ENDRX) && CODEC_IS_MODE(CODEC_MODE_RX)) {
// DBG_LED1_ON();
CODEC_SSC_ISR();
UWSDR_upload();
// DBG_LED1_OFF();
}
if(ul & AT91C_SSC_ENDRX && CODEC_IS_MODE(CODEC_MODE_TX)) {
CODEC_SSC_ISR();
}
_DBG_STATE_POS(_DBG_STATE_MAIN);
}
}