/*
* ATIVGAWonderPreInit --
*
* This function is called to initialise the VGA Wonder part of an ATIHWRec
* that is common to all modes generated by the driver.
*/
void
ATIVGAWonderPreInit
(
ATIPtr pATI,
ATIHWPtr pATIHW
)
{
pATIHW->b3 = ATIGetExtReg(0xB3U) & 0x20U;
pATIHW->b6 = 0x04U;
pATIHW->b6 |= 0x01U;
pATIHW->bf = ATIGetExtReg(0xBFU) & 0x5FU;
pATIHW->a3 = ATIGetExtReg(0xA3U) & 0x67U;
pATIHW->ab = ATIGetExtReg(0xABU) & 0xE7U;
pATIHW->ae = ATIGetExtReg(0xAEU) & 0xE0U;
}
/*
* ATIVGAWonderPreInit --
*
* This function is called to initialise the VGA Wonder part of an ATIHWRec
* that is common to all modes generated by the driver.
*/
void
ATIVGAWonderPreInit
(
ATIPtr pATI,
ATIHWPtr pATIHW
)
{
pATIHW->b3 = ATIGetExtReg(0xB3U) & 0x20U;
if (pATI->depth <= 4)
pATIHW->b6 = 0x40U;
else
pATIHW->b6 = 0x04U;
if (pATI->Chip <= ATI_CHIP_18800)
pATIHW->ba = 0x08U;
else if (pATI->Chip >= ATI_CHIP_28800_2)
{
if (pATI->VideoRAM > 256)
pATIHW->b6 |= 0x01U;
pATIHW->bf = ATIGetExtReg(0xBFU) & 0x5FU;
pATIHW->a3 = ATIGetExtReg(0xA3U) & 0x67U;
pATIHW->ab = ATIGetExtReg(0xABU) & 0xE7U;
pATIHW->ae = ATIGetExtReg(0xAEU) & 0xE0U;
}
}
/*
* ATIVGAWonderSave --
*
* This function is called to save the VGA Wonder portion of the current video
* state.
*/
void
ATIVGAWonderSave
(
ATIPtr pATI,
ATIHWPtr pATIHW
)
{
pATIHW->b0 = ATIGetExtReg(0xB0U);
pATIHW->b1 = ATIGetExtReg(0xB1U);
pATIHW->b2 = ATIGetExtReg(0xB2U);
pATIHW->b3 = ATIGetExtReg(0xB3U);
pATIHW->b5 = ATIGetExtReg(0xB5U);
pATIHW->b6 = ATIGetExtReg(0xB6U);
pATIHW->b8 = ATIGetExtReg(0xB8U);
pATIHW->b9 = ATIGetExtReg(0xB9U);
pATIHW->ba = ATIGetExtReg(0xBAU);
pATIHW->bd = ATIGetExtReg(0xBDU);
if (pATI->Chip > ATI_CHIP_18800)
{
pATIHW->be = ATIGetExtReg(0xBEU);
if (pATI->Chip >= ATI_CHIP_28800_2)
{
pATIHW->bf = ATIGetExtReg(0xBFU);
pATIHW->a3 = ATIGetExtReg(0xA3U);
pATIHW->a6 = ATIGetExtReg(0xA6U);
pATIHW->a7 = ATIGetExtReg(0xA7U);
pATIHW->ab = ATIGetExtReg(0xABU);
pATIHW->ac = ATIGetExtReg(0xACU);
pATIHW->ad = ATIGetExtReg(0xADU);
pATIHW->ae = ATIGetExtReg(0xAEU);
}
}
}
/*
* ATIVGAWonderCalculate --
*
* This function fills in the VGA Wonder portion of an ATIHWRec structure
* occurrence.
*/
void
ATIVGAWonderCalculate
(
ATIPtr pATI,
ATIHWPtr pATIHW,
DisplayModePtr pMode
)
{
/* Set up the default horizontal display enable skew */
if ((pATI->Chip >= ATI_CHIP_28800_2) && (pATI->Chip <= ATI_CHIP_28800_6) &&
!(pMode->Flags & V_HSKEW))
{
/*
* Modes using the higher clock frequencies need a non-zero Display
* Enable Skew. The following number has been empirically determined
* to be somewhere between 4.2 and 4.7 MHz.
*/
# define DisplayEnableSkewThreshold 4500
/* Set a reasonable default Display Enable Skew */
pMode->HSkew = pMode->CrtcHSkew =
ATIDivide(pMode->SynthClock, DisplayEnableSkewThreshold, 0, 0);
}
pMode->Flags |= V_HSKEW;
/*
* Fill in mode-specific VGA Wonder data.
*/
pATIHW->b0 = 0x00U;
if (pATI->depth >= 8)
pATIHW->b0 = 0x20U;
if (pATI->Chip >= ATI_CHIP_28800_2)
{
if (pATI->VideoRAM > 512)
pATIHW->b0 |= 0x08U;
else if (pATI->VideoRAM > 256)
pATIHW->b0 |= 0x10U;
}
else if (pATI->depth <= 4)
{
if (pATI->VideoRAM > 256)
pATIHW->b0 |= 0x08U;
}
else
{
if (pATI->VideoRAM > 256)
pATIHW->b0 |= 0x18U;
else
pATIHW->b0 |= 0x06U;
}
pATIHW->b1 = ATIGetExtReg(0xB1U) & 0x04U;
/*
* Setting the following bit causes hangs on return to text mode from
* packed modes on 18800-1's. The hang occurs because the adapter's I/O
* response is completely disabled when the register is rewritten. The
* adapter can then only be re-enabled with a powerdown. The bit, when on,
* blanks out the overscan.
*/
if ((pATI->Chip == ATI_CHIP_18800_1) && (pATI->depth >= 8))
pATIHW->b5 = 0x00U;
else
pATIHW->b5 = 0x01U;
pATIHW->b8 = ATIGetExtReg(0xB8U) & 0xC0U;
pATIHW->b9 = ATIGetExtReg(0xB9U) & 0x7FU;
pATIHW->bd = ATIGetExtReg(0xBDU) & 0x02U;
if (pATI->Chip <= ATI_CHIP_18800)
pATIHW->b2 = ATIGetExtReg(0xB2U) & 0xC0U;
else
{
pATIHW->b2 = 0x00U;
pATIHW->be = (ATIGetExtReg(0xBEU) & 0x30U) | 0x09U;
if (pATI->Chip >= ATI_CHIP_28800_2)
{
pATIHW->a6 = (ATIGetExtReg(0xA6U) & 0x38U) | 0x04U;
pATIHW->a7 = (ATIGetExtReg(0xA7U) & 0xBEU) ;
pATIHW->ac = (ATIGetExtReg(0xACU) & 0x8EU) ;
}
}
if (pMode->Flags & V_INTERLACE)
{ /* Enable interlace */
if (pATI->Chip <= ATI_CHIP_18800)
pATIHW->b2 |= 0x01U;
else
pATIHW->be |= 0x02U;
}
#if 0 /* This is no longer needed but is left in for reference */
if (pMode->Flags & V_DBLSCAN) /* Enable doublescan */
pATIHW->b1 |= 0x08U;
#endif
if (pATI->OptionCSync || (pMode->Flags & (V_CSYNC | V_PCSYNC)))
pATIHW->bd |= 0x08U; /* Enable composite sync */
if (pMode->Flags & V_NCSYNC)
pATIHW->bd |= 0x09U; /* Invert composite sync */
if (pMode->HSkew > 0)
{
if (pMode->HSkew <= 3)
pATIHW->b5 |= 0x04U;
else if (pATI->Chip >= ATI_CHIP_28800_2)
switch ((pMode->HSkew + 4) >> 3)
{
case 1: /* Use ATI override */
pATIHW->crt[3] &= ~0x60U;
pATIHW->b0 |= 0x01U;
break;
case 2: /* Use ATI override */
pATIHW->crt[3] &= ~0x60U;
pATIHW->a6 |= 0x01U;
break;
case 3:
pATIHW->crt[3] |= 0x60U;
break;
case 4:
pATIHW->a7 |= 0x40U;
break;
case 5:
pATIHW->ac |= 0x10U;
break;
case 6:
pATIHW->ac |= 0x20U;
break;
default:
break;
}
}
}
/*
* ATIUnlock --
*
* This function is entered to unlock registers and disable unwanted
* emulations. It saves the current state for later restoration by ATILock().
*/
void
ATIUnlock
(
ATIPtr pATI
)
{
CARD32 tmp;
#ifndef AVOID_CPIO
CARD32 saved_lcd_gen_ctrl = 0, lcd_gen_ctrl = 0;
#endif /* AVOID_CPIO */
if (pATI->Unlocked)
return;
pATI->Unlocked = TRUE;
{
/* Reset everything */
pATI->LockData.bus_cntl = inr(BUS_CNTL);
if (pATI->Chip < ATI_CHIP_264VT4)
{
pATI->LockData.bus_cntl =
(pATI->LockData.bus_cntl & ~BUS_HOST_ERR_INT_EN) |
BUS_HOST_ERR_INT;
if (pATI->Chip < ATI_CHIP_264VTB)
pATI->LockData.bus_cntl =
(pATI->LockData.bus_cntl & ~BUS_FIFO_ERR_INT_EN) |
BUS_FIFO_ERR_INT;
}
tmp = pATI->LockData.bus_cntl & ~BUS_ROM_DIS;
if (pATI->Chip < ATI_CHIP_264VTB)
tmp |= SetBits(15, BUS_FIFO_WS);
else
tmp &= ~BUS_MASTER_DIS;
if (pATI->Chip >= ATI_CHIP_264VT)
tmp |= BUS_EXT_REG_EN; /* Enable Block 1 */
outr(BUS_CNTL, tmp);
pATI->LockData.crtc_int_cntl = inr(CRTC_INT_CNTL);
outr(CRTC_INT_CNTL, (pATI->LockData.crtc_int_cntl & ~CRTC_INT_ENS) |
CRTC_INT_ACKS);
#ifdef XF86DRI_DEVEL
if (pATI->irq > 0)
outr(CRTC_INT_CNTL, (inr(CRTC_INT_CNTL) & ~CRTC_INT_ACKS) |
CRTC_VBLANK_INT_EN); /* Enable VBLANK interrupt - handled by DRM */
#endif /* XF86DRI_DEVEL */
pATI->LockData.gen_test_cntl = inr(GEN_TEST_CNTL) &
(GEN_OVR_OUTPUT_EN | GEN_OVR_POLARITY | GEN_CUR_EN |
GEN_BLOCK_WR_EN);
tmp = pATI->LockData.gen_test_cntl & ~GEN_CUR_EN;
outr(GEN_TEST_CNTL, tmp | GEN_GUI_EN);
outr(GEN_TEST_CNTL, tmp);
outr(GEN_TEST_CNTL, tmp | GEN_GUI_EN);
tmp = pATI->LockData.crtc_gen_cntl = inr(CRTC_GEN_CNTL) &
~(CRTC_EN | CRTC_LOCK_REGS);
if (pATI->Chip >= ATI_CHIP_264XL)
tmp = (tmp & ~CRTC_INT_ENS_X) | CRTC_INT_ACKS_X;
outr(CRTC_GEN_CNTL, tmp | CRTC_EN);
outr(CRTC_GEN_CNTL, tmp);
outr(CRTC_GEN_CNTL, tmp | CRTC_EN);
if ((pATI->LCDPanelID >= 0) && (pATI->Chip != ATI_CHIP_264LT))
{
pATI->LockData.lcd_index = inr(LCD_INDEX);
if (pATI->Chip >= ATI_CHIP_264XL)
outr(LCD_INDEX, pATI->LockData.lcd_index &
~(LCD_MONDET_INT_EN | LCD_MONDET_INT));
/*
* Prevent BIOS initiated display switches on dual-CRT controllers.
*/
if (!pATI->OptionBIOSDisplay && (pATI->Chip != ATI_CHIP_264XL))
{
#ifdef TV_OUT
pATI->LockData.scratch_reg3 = inr(SCRATCH_REG3) & ~DISPLAY_SWITCH_DISABLE;
outr(SCRATCH_REG3, pATI->LockData.scratch_reg3);
#else
pATI->LockData.scratch_reg3 = inr(SCRATCH_REG3);
outr(SCRATCH_REG3,
pATI->LockData.scratch_reg3 | DISPLAY_SWITCH_DISABLE);
#endif /* TV_OUT */
}
}
pATI->LockData.mem_cntl = inr(MEM_CNTL);
if (pATI->Chip < ATI_CHIP_264CT)
outr(MEM_CNTL, pATI->LockData.mem_cntl &
~(CTL_MEM_BNDRY | CTL_MEM_BNDRY_EN));
/* Disable feature connector on integrated controllers */
tmp = pATI->LockData.dac_cntl = inr(DAC_CNTL);
if (pATI->Chip >= ATI_CHIP_264CT)
tmp &= ~DAC_FEA_CON_EN;
#ifndef AVOID_CPIO
/* Ensure VGA aperture is enabled */
pATI->LockData.config_cntl = inr(CONFIG_CNTL);
tmp |= DAC_VGA_ADR_EN;
outr(CONFIG_CNTL, pATI->LockData.config_cntl & ~CFG_VGA_DIS);
#endif /* AVOID_CPIO */
outr(DAC_CNTL, tmp);
if (pATI->Chip >= ATI_CHIP_264VTB)
{
pATI->LockData.mpp_config = inr(MPP_CONFIG);
pATI->LockData.mpp_strobe_seq = inr(MPP_STROBE_SEQ);
pATI->LockData.tvo_cntl = inr(TVO_CNTL);
if (pATI->Chip >= ATI_CHIP_264GT2C)
{
pATI->LockData.hw_debug = inr(HW_DEBUG);
if (pATI->Chip >= ATI_CHIP_264GTPRO)
{
if (!(pATI->LockData.hw_debug & CMDFIFO_SIZE_EN))
outr(HW_DEBUG,
pATI->LockData.hw_debug | CMDFIFO_SIZE_EN);
pATI->LockData.i2c_cntl_0 =
inr(I2C_CNTL_0) | (I2C_CNTL_STAT | I2C_CNTL_HPTR_RST);
outr(I2C_CNTL_0,
pATI->LockData.i2c_cntl_0 & ~I2C_CNTL_INT_EN);
pATI->LockData.i2c_cntl_1 = inr(I2C_CNTL_1);
}
else
{
if (pATI->LockData.hw_debug & CMDFIFO_SIZE_DIS)
outr(HW_DEBUG,
pATI->LockData.hw_debug & ~CMDFIFO_SIZE_DIS);
}
}
}
}
#ifndef AVOID_CPIO
if (pATI->VGAAdapter)
{
if (pATI->CPIO_VGAWonder)
{
/*
* Ensure all registers are read/write and disable all non-VGA
* emulations.
*/
pATI->LockData.b1 = ATIGetExtReg(0xB1U);
ATIModifyExtReg(pATI, 0xB1U, pATI->LockData.b1, 0xFCU, 0x00U);
pATI->LockData.b4 = ATIGetExtReg(0xB4U);
ATIModifyExtReg(pATI, 0xB4U, pATI->LockData.b4, 0x00U, 0x00U);
pATI->LockData.b5 = ATIGetExtReg(0xB5U);
ATIModifyExtReg(pATI, 0xB5U, pATI->LockData.b5, 0xBFU, 0x00U);
pATI->LockData.b6 = ATIGetExtReg(0xB6U);
ATIModifyExtReg(pATI, 0xB6U, pATI->LockData.b6, 0xDDU, 0x00U);
pATI->LockData.b8 = ATIGetExtReg(0xB8U);
ATIModifyExtReg(pATI, 0xB8U, pATI->LockData.b8, 0xC0U, 0x00U);
pATI->LockData.b9 = ATIGetExtReg(0xB9U);
ATIModifyExtReg(pATI, 0xB9U, pATI->LockData.b9, 0x7FU, 0x00U);
{
pATI->LockData.be = ATIGetExtReg(0xBEU);
ATIModifyExtReg(pATI, 0xBEU, pATI->LockData.be, 0xFAU, 0x01U);
{
pATI->LockData.a6 = ATIGetExtReg(0xA6U);
ATIModifyExtReg(pATI, 0xA6U, pATI->LockData.a6,
0x7FU, 0x00U);
pATI->LockData.ab = ATIGetExtReg(0xABU);
ATIModifyExtReg(pATI, 0xABU, pATI->LockData.ab,
0xE7U, 0x00U);
}
}
}
if (pATI->LCDPanelID >= 0)
{
if (pATI->Chip == ATI_CHIP_264LT)
{
saved_lcd_gen_ctrl = inr(LCD_GEN_CTRL);
/* Setup to unlock non-shadow registers */
lcd_gen_ctrl = saved_lcd_gen_ctrl & ~SHADOW_RW_EN;
outr(LCD_GEN_CTRL, lcd_gen_ctrl);
}
else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) ||
(pATI->Chip == ATI_CHIP_264XL) ||
(pATI->Chip == ATI_CHIP_MOBILITY)) */
{
saved_lcd_gen_ctrl = ATIMach64GetLCDReg(LCD_GEN_CNTL);
/* Setup to unlock non-shadow registers */
lcd_gen_ctrl = saved_lcd_gen_ctrl &
~(CRTC_RW_SELECT | SHADOW_RW_EN);
ATIMach64PutLCDReg(LCD_GEN_CNTL, lcd_gen_ctrl);
}
}
ATISetVGAIOBase(pATI, inb(R_GENMO));
/*
* There's a bizarre interaction here. If bit 0x80 of CRTC[17] is on,
* then CRTC[3] is read-only. If bit 0x80 of CRTC[3] is off, then
* CRTC[17] is write-only (or a read attempt actually returns bits from
* C/EGA's light pen position). This means that if both conditions are
* met, CRTC[17]'s value on server entry cannot be retrieved.
*/
pATI->LockData.crt03 = tmp = GetReg(CRTX(pATI->CPIO_VGABase), 0x03U);
if ((tmp & 0x80U) ||
((outb(CRTD(pATI->CPIO_VGABase), tmp | 0x80U),
tmp = inb(CRTD(pATI->CPIO_VGABase))) & 0x80U))
{
/* CRTC[16-17] should be readable */
pATI->LockData.crt11 = tmp =
GetReg(CRTX(pATI->CPIO_VGABase), 0x11U);
if (tmp & 0x80U) /* Unprotect CRTC[0-7] */
outb(CRTD(pATI->CPIO_VGABase), tmp & 0x7FU);
}
else
{
/*
* Could not make CRTC[17] readable, so unprotect CRTC[0-7]
* replacing VSyncEnd with zero. This zero will be replaced after
* acquiring the needed access.
*/
unsigned int VSyncEnd, VBlankStart, VBlankEnd;
CARD8 crt07, crt09;
PutReg(CRTX(pATI->CPIO_VGABase), 0x11U, 0x20U);
/* Make CRTC[16-17] readable */
PutReg(CRTX(pATI->CPIO_VGABase), 0x03U, tmp | 0x80U);
/* Make vertical synch pulse as wide as possible */
crt07 = GetReg(CRTX(pATI->CPIO_VGABase), 0x07U);
crt09 = GetReg(CRTX(pATI->CPIO_VGABase), 0x09U);
VBlankStart = (((crt09 & 0x20U) << 4) | ((crt07 & 0x08U) << 5) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x15U)) + 1;
VBlankEnd = (VBlankStart & 0x0300U) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x16U);
if (VBlankEnd <= VBlankStart)
VBlankEnd += 0x0100U;
VSyncEnd = (((crt07 & 0x80U) << 2) | ((crt07 & 0x04U) << 6) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x10U)) + 0x0FU;
if (VSyncEnd >= VBlankEnd)
VSyncEnd = VBlankEnd - 1;
pATI->LockData.crt11 = (VSyncEnd & 0x0FU) | 0x20U;
PutReg(CRTX(pATI->CPIO_VGABase), 0x11U, pATI->LockData.crt11);
pATI->LockData.crt11 |= 0x80U;
}
if (pATI->LCDPanelID >= 0)
{
/* Setup to unlock shadow registers */
lcd_gen_ctrl |= SHADOW_RW_EN;
if (pATI->Chip == ATI_CHIP_264LT)
outr(LCD_GEN_CTRL, lcd_gen_ctrl);
else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) ||
(pATI->Chip == ATI_CHIP_264XL) ||
(pATI->Chip == ATI_CHIP_MOBILITY)) */
ATIMach64PutLCDReg(LCD_GEN_CNTL, lcd_gen_ctrl);
/* Unlock shadow registers */
ATISetVGAIOBase(pATI, inb(R_GENMO));
pATI->LockData.shadow_crt03 = tmp =
GetReg(CRTX(pATI->CPIO_VGABase), 0x03U);
if ((tmp & 0x80U) ||
((outb(CRTD(pATI->CPIO_VGABase), tmp | 0x80U),
tmp = inb(CRTD(pATI->CPIO_VGABase))) & 0x80U))
{
/* CRTC[16-17] should be readable */
pATI->LockData.shadow_crt11 = tmp =
GetReg(CRTX(pATI->CPIO_VGABase), 0x11U);
if (tmp & 0x80U) /* Unprotect CRTC[0-7] */
{
outb(CRTD(pATI->CPIO_VGABase), tmp & 0x7FU);
}
else if (!tmp && pATI->LockData.crt11)
{
pATI->LockData.shadow_crt11 = tmp = pATI->LockData.crt11;
outb(CRTD(pATI->CPIO_VGABase), tmp & 0x7FU);
}
}
else
{
/*
* Could not make CRTC[17] readable, so unprotect CRTC[0-7]
* replacing VSyncEnd with zero. This zero will be replaced
* after acquiring the needed access.
*/
unsigned int VSyncEnd, VBlankStart, VBlankEnd;
CARD8 crt07, crt09;
PutReg(CRTX(pATI->CPIO_VGABase), 0x11U, 0x20U);
/* Make CRTC[16-17] readable */
PutReg(CRTX(pATI->CPIO_VGABase), 0x03U, tmp | 0x80U);
/* Make vertical synch pulse as wide as possible */
crt07 = GetReg(CRTX(pATI->CPIO_VGABase), 0x07U);
crt09 = GetReg(CRTX(pATI->CPIO_VGABase), 0x09U);
VBlankStart = (((crt09 & 0x20U) << 4) |
((crt07 & 0x08U) << 5) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x15U)) + 1;
VBlankEnd = (VBlankStart & 0x0300U) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x16U);
if (VBlankEnd <= VBlankStart)
VBlankEnd += 0x0100U;
VSyncEnd = (((crt07 & 0x80U) << 2) | ((crt07 & 0x04U) << 6) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x10U)) + 0x0FU;
if (VSyncEnd >= VBlankEnd)
VSyncEnd = VBlankEnd - 1;
pATI->LockData.shadow_crt11 = (VSyncEnd & 0x0FU) | 0x20U;
PutReg(CRTX(pATI->CPIO_VGABase), 0x11U,
pATI->LockData.shadow_crt11);
pATI->LockData.shadow_crt11 |= 0x80U;
}
/* Restore selection */
if (pATI->Chip == ATI_CHIP_264LT)
{
outr(LCD_GEN_CTRL, saved_lcd_gen_ctrl);
}
else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) ||
(pATI->Chip == ATI_CHIP_264XL) ||
(pATI->Chip == ATI_CHIP_MOBILITY)) */
{
ATIMach64PutLCDReg(LCD_GEN_CNTL, saved_lcd_gen_ctrl);
/* Restore LCD index */
out8(LCD_INDEX, GetByte(pATI->LockData.lcd_index, 0));
}
}
}
#endif /* AVOID_CPIO */
}