/**Function*************************************************************
Synopsis [Performs ternary simulation of one frame.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
unsigned * Saig_ManBmcTerSimOne( Aig_Man_t * p, unsigned * pPrev )
{
Aig_Obj_t * pObj, * pObjLi;
unsigned * pInfo;
int i, Val0, Val1;
pInfo = ABC_CALLOC( unsigned, Aig_BitWordNum(2 * Aig_ManObjNumMax(p)) );
Saig_ManBmcSimInfoSet( pInfo, Aig_ManConst1(p), SAIG_TER_ONE );
Saig_ManForEachPi( p, pObj, i )
Saig_ManBmcSimInfoSet( pInfo, pObj, SAIG_TER_UND );
if ( pPrev == NULL )
{
Saig_ManForEachLo( p, pObj, i )
Saig_ManBmcSimInfoSet( pInfo, pObj, SAIG_TER_ZER );
}
else
{
Saig_ManForEachLiLo( p, pObjLi, pObj, i )
Saig_ManBmcSimInfoSet( pInfo, pObj, Saig_ManBmcSimInfoGet(pPrev, pObjLi) );
}
Aig_ManForEachNode( p, pObj, i )
{
Val0 = Saig_ManBmcSimInfoGet( pInfo, Aig_ObjFanin0(pObj) );
Val1 = Saig_ManBmcSimInfoGet( pInfo, Aig_ObjFanin1(pObj) );
if ( Aig_ObjFaninC0(pObj) )
Val0 = Saig_ManBmcSimInfoNot( Val0 );
if ( Aig_ObjFaninC1(pObj) )
Val1 = Saig_ManBmcSimInfoNot( Val1 );
Saig_ManBmcSimInfoSet( pInfo, pObj, Saig_ManBmcSimInfoAnd(Val0, Val1) );
}
/**Function*************************************************************
Synopsis [Create the new node assuming it does not exist.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_ObjCreate( Aig_Man_t * p, Aig_Obj_t * pGhost )
{
Aig_Obj_t * pObj;
assert( !Aig_IsComplement(pGhost) );
assert( Aig_ObjIsHash(pGhost) );
// assert( pGhost == &p->Ghost );
// get memory for the new object
pObj = Aig_ManFetchMemory( p );
pObj->Type = pGhost->Type;
// add connections
Aig_ObjConnect( p, pObj, pGhost->pFanin0, pGhost->pFanin1 );
// update node counters of the manager
p->nObjs[Aig_ObjType(pObj)]++;
assert( pObj->pData == NULL );
if ( p->pManHaig )
{
pGhost->pFanin0 = Aig_ObjHaig( pGhost->pFanin0 );
pGhost->pFanin1 = Aig_ObjHaig( pGhost->pFanin1 );
pObj->pHaig = Aig_ObjCreate( p->pManHaig, pGhost );
assert( !Aig_IsComplement(pObj->pHaig) );
// printf( "Creating HAIG node %d equivalent to node %d.\n", pObj->pHaig->Id, pObj->Id );
}
// create the power counter
if ( p->vProbs )
{
float Prob0 = Aig_Int2Float( Vec_IntEntry( p->vProbs, Aig_ObjFaninId0(pObj) ) );
float Prob1 = Aig_Int2Float( Vec_IntEntry( p->vProbs, Aig_ObjFaninId1(pObj) ) );
Prob0 = Aig_ObjFaninC0(pObj)? 1.0 - Prob0 : Prob0;
Prob1 = Aig_ObjFaninC1(pObj)? 1.0 - Prob1 : Prob1;
Vec_IntSetEntry( p->vProbs, pObj->Id, Aig_Float2Int(Prob0 * Prob1) );
}
return pObj;
}
static inline void Saig_ObjDualFanin( Aig_Man_t * pAigNew, Vec_Ptr_t * vCopies, Aig_Obj_t * pObj, int iFanin, Aig_Obj_t ** ppRes0, Aig_Obj_t ** ppRes1 ) {
Aig_Obj_t * pTemp0, * pTemp1, * pCare;
int fCompl;
assert( iFanin == 0 || iFanin == 1 );
if ( iFanin == 0 )
{
pTemp0 = Saig_ObjDual( vCopies, Aig_ObjFaninId0(pObj), 0 );
pTemp1 = Saig_ObjDual( vCopies, Aig_ObjFaninId0(pObj), 1 );
fCompl = Aig_ObjFaninC0( pObj );
}
else
{
pTemp0 = Saig_ObjDual( vCopies, Aig_ObjFaninId1(pObj), 0 );
pTemp1 = Saig_ObjDual( vCopies, Aig_ObjFaninId1(pObj), 1 );
fCompl = Aig_ObjFaninC1( pObj );
}
if ( fCompl )
{
pCare = Aig_Or( pAigNew, pTemp0, pTemp1 );
*ppRes0 = Aig_And( pAigNew, pTemp1, pCare );
*ppRes1 = Aig_And( pAigNew, pTemp0, pCare );
}
else
{
*ppRes0 = pTemp0;
*ppRes1 = pTemp1;
}
}
/**Function*************************************************************
Synopsis [Creates fast simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Saig_SimObj_t * Saig_ManCreateMan( Aig_Man_t * p )
{
Saig_SimObj_t * pAig, * pEntry;
Aig_Obj_t * pObj;
int i;
pAig = ABC_CALLOC( Saig_SimObj_t, Aig_ManObjNumMax(p)+1 );
// printf( "Allocating %7.2f Mb.\n", 1.0 * sizeof(Saig_SimObj_t) * (Aig_ManObjNumMax(p)+1)/(1<<20) );
Aig_ManForEachObj( p, pObj, i )
{
pEntry = pAig + i;
pEntry->Type = pObj->Type;
if ( Aig_ObjIsPi(pObj) || i == 0 )
{
if ( Saig_ObjIsLo(p, pObj) )
{
pEntry->iFan0 = (Saig_ObjLoToLi(p, pObj)->Id << 1);
pEntry->iFan1 = -1;
}
continue;
}
pEntry->iFan0 = (Aig_ObjFaninId0(pObj) << 1) | Aig_ObjFaninC0(pObj);
if ( Aig_ObjIsPo(pObj) )
continue;
assert( Aig_ObjIsNode(pObj) );
pEntry->iFan1 = (Aig_ObjFaninId1(pObj) << 1) | Aig_ObjFaninC1(pObj);
}
/**Function*************************************************************
Synopsis [Creates the canonical form of the node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_CanonPair_rec( Aig_Man_t * p, Aig_Obj_t * pGhost )
{
Aig_Obj_t * pResult, * pLat0, * pLat1;
int fCompl0, fCompl1;
Aig_Type_t Type;
assert( Aig_ObjIsNode(pGhost) );
// consider the case when the pair is canonical
if ( !Aig_ObjIsLatch(Aig_ObjFanin0(pGhost)) || !Aig_ObjIsLatch(Aig_ObjFanin1(pGhost)) )
{
if ( (pResult = Aig_TableLookup( p, pGhost )) )
return pResult;
return Aig_ObjCreate( p, pGhost );
}
/// remember the latches
pLat0 = Aig_ObjFanin0(pGhost);
pLat1 = Aig_ObjFanin1(pGhost);
// remember type and compls
Type = Aig_ObjType(pGhost);
fCompl0 = Aig_ObjFaninC0(pGhost);
fCompl1 = Aig_ObjFaninC1(pGhost);
// call recursively
pResult = Aig_Oper( p, Aig_NotCond(Aig_ObjChild0(pLat0), fCompl0), Aig_NotCond(Aig_ObjChild0(pLat1), fCompl1), Type );
// build latch on top of this
return Aig_Latch( p, pResult, (Type == AIG_OBJ_AND)? fCompl0 & fCompl1 : fCompl0 ^ fCompl1 );
}
// procedure to detect an EXOR gate
static inline int Aig_ObjIsExorType( Aig_Obj_t * p0, Aig_Obj_t * p1, Aig_Obj_t ** ppFan0, Aig_Obj_t ** ppFan1 )
{
if ( !Aig_IsComplement(p0) || !Aig_IsComplement(p1) )
return 0;
p0 = Aig_Regular(p0);
p1 = Aig_Regular(p1);
if ( !Aig_ObjIsAnd(p0) || !Aig_ObjIsAnd(p1) )
return 0;
if ( Aig_ObjFanin0(p0) != Aig_ObjFanin0(p1) || Aig_ObjFanin1(p0) != Aig_ObjFanin1(p1) )
return 0;
if ( Aig_ObjFaninC0(p0) == Aig_ObjFaninC0(p1) || Aig_ObjFaninC1(p0) == Aig_ObjFaninC1(p1) )
return 0;
*ppFan0 = Aig_ObjChild0(p0);
*ppFan1 = Aig_ObjChild1(p0);
return 1;
}
// hashing the node
static unsigned long Aig_Hash( Aig_Obj_t * pObj, int TableSize )
{
unsigned long Key = Aig_ObjIsExor(pObj) * 1699;
Key ^= Aig_ObjFanin0(pObj)->Id * 7937;
Key ^= Aig_ObjFanin1(pObj)->Id * 2971;
Key ^= Aig_ObjFaninC0(pObj) * 911;
Key ^= Aig_ObjFaninC1(pObj) * 353;
return Key % TableSize;
}
/**Function*************************************************************
Synopsis [Computes truth table of the cut.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
unsigned * Aig_ManCutTruthOne( Aig_Obj_t * pNode, unsigned * pTruth, int nWords )
{
unsigned * pTruth0, * pTruth1;
int i;
pTruth0 = Aig_ObjFanin0(pNode)->pData;
pTruth1 = Aig_ObjFanin1(pNode)->pData;
if ( Aig_ObjIsExor(pNode) )
for ( i = 0; i < nWords; i++ )
pTruth[i] = pTruth0[i] ^ pTruth1[i];
else if ( !Aig_ObjFaninC0(pNode) && !Aig_ObjFaninC1(pNode) )
for ( i = 0; i < nWords; i++ )
pTruth[i] = pTruth0[i] & pTruth1[i];
else if ( !Aig_ObjFaninC0(pNode) && Aig_ObjFaninC1(pNode) )
for ( i = 0; i < nWords; i++ )
pTruth[i] = pTruth0[i] & ~pTruth1[i];
else if ( Aig_ObjFaninC0(pNode) && !Aig_ObjFaninC1(pNode) )
for ( i = 0; i < nWords; i++ )
pTruth[i] = ~pTruth0[i] & pTruth1[i];
else // if ( Aig_ObjFaninC0(pNode) && Aig_ObjFaninC1(pNode) )
for ( i = 0; i < nWords; i++ )
pTruth[i] = ~pTruth0[i] & ~pTruth1[i];
return pTruth;
}
/**Function*************************************************************
Synopsis [Derives the global BDD for one AIG node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
DdNode * Bbr_NodeGlobalBdds_rec( DdManager * dd, Aig_Obj_t * pNode, int nBddSizeMax, int fDropInternal, ProgressBar * pProgress, int * pCounter, int fVerbose )
{
DdNode * bFunc, * bFunc0, * bFunc1;
assert( !Aig_IsComplement(pNode) );
if ( Cudd_ReadKeys(dd)-Cudd_ReadDead(dd) > (unsigned)nBddSizeMax )
{
// Extra_ProgressBarStop( pProgress );
if ( fVerbose )
printf( "The number of live nodes reached %d.\n", nBddSizeMax );
fflush( stdout );
return NULL;
}
// if the result is available return
if ( Aig_ObjGlobalBdd(pNode) == NULL )
{
// compute the result for both branches
bFunc0 = Bbr_NodeGlobalBdds_rec( dd, Aig_ObjFanin0(pNode), nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose );
if ( bFunc0 == NULL )
return NULL;
Cudd_Ref( bFunc0 );
bFunc1 = Bbr_NodeGlobalBdds_rec( dd, Aig_ObjFanin1(pNode), nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose );
if ( bFunc1 == NULL )
return NULL;
Cudd_Ref( bFunc1 );
bFunc0 = Cudd_NotCond( bFunc0, Aig_ObjFaninC0(pNode) );
bFunc1 = Cudd_NotCond( bFunc1, Aig_ObjFaninC1(pNode) );
// get the final result
bFunc = Cudd_bddAnd( dd, bFunc0, bFunc1 ); Cudd_Ref( bFunc );
Cudd_RecursiveDeref( dd, bFunc0 );
Cudd_RecursiveDeref( dd, bFunc1 );
// add the number of used nodes
(*pCounter)++;
// set the result
assert( Aig_ObjGlobalBdd(pNode) == NULL );
Aig_ObjSetGlobalBdd( pNode, bFunc );
// increment the progress bar
// if ( pProgress )
// Extra_ProgressBarUpdate( pProgress, *pCounter, NULL );
}
// prepare the return value
bFunc = Aig_ObjGlobalBdd(pNode);
// dereference BDD at the node
if ( --pNode->nRefs == 0 && fDropInternal )
{
Cudd_Deref( bFunc );
Aig_ObjSetGlobalBdd( pNode, NULL );
}
return bFunc;
}
/**Function*************************************************************
Synopsis [Returns the array of constraint candidates.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
DdNode * Llb_ManComputeIndCase_rec( Aig_Man_t * p, Aig_Obj_t * pObj, DdManager * dd, Vec_Ptr_t * vBdds )
{
DdNode * bBdd0, * bBdd1;
DdNode * bFunc = (DdNode *)Vec_PtrEntry( vBdds, Aig_ObjId(pObj) );
if ( bFunc != NULL )
return bFunc;
assert( Aig_ObjIsNode(pObj) );
bBdd0 = Llb_ManComputeIndCase_rec( p, Aig_ObjFanin0(pObj), dd, vBdds );
bBdd1 = Llb_ManComputeIndCase_rec( p, Aig_ObjFanin1(pObj), dd, vBdds );
bBdd0 = Cudd_NotCond( bBdd0, Aig_ObjFaninC0(pObj) );
bBdd1 = Cudd_NotCond( bBdd1, Aig_ObjFaninC1(pObj) );
bFunc = Cudd_bddAnd( dd, bBdd0, bBdd1 ); Cudd_Ref( bFunc );
Vec_PtrWriteEntry( vBdds, Aig_ObjId(pObj), bFunc );
return bFunc;
}
/**Function*************************************************************
Synopsis [Performs one retiming step backward.]
Description [Returns the pointer to node after retiming.]
SideEffects [Remember to run Aig_ManSetCioIds() in advance.]
SeeAlso []
***********************************************************************/
Aig_Obj_t * Saig_ManRetimeNodeBwd( Aig_Man_t * p, Aig_Obj_t * pObjLo )
{
Aig_Obj_t * pFanin0, * pFanin1;
Aig_Obj_t * pLo0New, * pLo1New;
Aig_Obj_t * pLi0New, * pLi1New;
Aig_Obj_t * pObj, * pObjNew, * pObjLi;
int fCompl0, fCompl1;
assert( Saig_ManRegNum(p) > 0 );
assert( Aig_ObjCioId(pObjLo) > 0 );
assert( Saig_ObjIsLo(p, pObjLo) );
// get the corresponding latch input
pObjLi = Saig_ManLi( p, Aig_ObjCioId(pObjLo) - Saig_ManPiNum(p) );
// get the node
pObj = Aig_ObjFanin0(pObjLi);
if ( !Aig_ObjIsNode(pObj) )
return NULL;
// get the fanins
pFanin0 = Aig_ObjFanin0(pObj);
pFanin1 = Aig_ObjFanin1(pObj);
// get the complemented attributes of the fanins
fCompl0 = Aig_ObjFaninC0(pObj) ^ Aig_ObjFaninC0(pObjLi);
fCompl1 = Aig_ObjFaninC1(pObj) ^ Aig_ObjFaninC0(pObjLi);
// create latch inputs
pLi0New = Aig_ObjCreateCo( p, Aig_NotCond(pFanin0, fCompl0) );
pLi0New->CioId = Aig_ManCoNum(p) - 1;
pLi1New = Aig_ObjCreateCo( p, Aig_NotCond(pFanin1, fCompl1) );
pLi1New->CioId = Aig_ManCoNum(p) - 1;
// create latch outputs
pLo0New = Aig_ObjCreateCi(p);
pLo0New->CioId = Aig_ManCiNum(p) - 1;
pLo1New = Aig_ObjCreateCi(p);
pLo1New->CioId = Aig_ManCiNum(p) - 1;
pLo0New = Aig_NotCond( pLo0New, fCompl0 );
pLo1New = Aig_NotCond( pLo1New, fCompl1 );
p->nRegs += 2;
// create node
pObjNew = Aig_And( p, pLo0New, pLo1New );
// assert( pObjNew->fPhase == 0 );
return pObjNew;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
// hashing the node
static unsigned long Aig_Hash( Aig_Obj_t * pObj, int TableSize )
{
unsigned long Key = Aig_ObjIsExor(pObj) * 1699;
Key ^= Aig_ObjFanin0(pObj)->Id * 7937;
Key ^= Aig_ObjFanin1(pObj)->Id * 2971;
Key ^= Aig_ObjFaninC0(pObj) * 911;
Key ^= Aig_ObjFaninC1(pObj) * 353;
return Key % TableSize;
}
/**Function*************************************************************
Synopsis [Adds relevant constraints.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Abc_NtkConstructCare_rec( Aig_Man_t * pCare, Aig_Obj_t * pObj, Aig_Man_t * pMan )
{
Aig_Obj_t * pObj0, * pObj1;
if ( Aig_ObjIsTravIdCurrent( pCare, pObj ) )
return (Aig_Obj_t *)pObj->pData;
Aig_ObjSetTravIdCurrent( pCare, pObj );
if ( Aig_ObjIsPi(pObj) )
return (Aig_Obj_t *)(pObj->pData = NULL);
pObj0 = Abc_NtkConstructCare_rec( pCare, Aig_ObjFanin0(pObj), pMan );
if ( pObj0 == NULL )
return (Aig_Obj_t *)(pObj->pData = NULL);
pObj1 = Abc_NtkConstructCare_rec( pCare, Aig_ObjFanin1(pObj), pMan );
if ( pObj1 == NULL )
return (Aig_Obj_t *)(pObj->pData = NULL);
pObj0 = Aig_NotCond( pObj0, Aig_ObjFaninC0(pObj) );
pObj1 = Aig_NotCond( pObj1, Aig_ObjFaninC1(pObj) );
return (Aig_Obj_t *)(pObj->pData = Aig_And( pMan, pObj0, pObj1 ));
}
/**Function*************************************************************
Synopsis [Performs ternary simulation for one node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Saig_ManExtendOneEval2( Vec_Ptr_t * vSimInfo, Aig_Obj_t * pObj, int iFrame )
{
int Value0, Value1, Value;
Value0 = Saig_ManSimInfo2Get( vSimInfo, Aig_ObjFanin0(pObj), iFrame );
if ( Aig_ObjFaninC0(pObj) )
Value0 = Saig_ManSimInfo2Not( Value0 );
if ( Aig_ObjIsCo(pObj) )
{
Saig_ManSimInfo2Set( vSimInfo, pObj, iFrame, Value0 );
return Value0;
}
assert( Aig_ObjIsNode(pObj) );
Value1 = Saig_ManSimInfo2Get( vSimInfo, Aig_ObjFanin1(pObj), iFrame );
if ( Aig_ObjFaninC1(pObj) )
Value1 = Saig_ManSimInfo2Not( Value1 );
Value = Saig_ManSimInfo2And( Value0, Value1 );
Saig_ManSimInfo2Set( vSimInfo, pObj, iFrame, Value );
return Value;
}
/**Function*************************************************************
Synopsis [Drive implications of the given node towards primary outputs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Saig_ManSetAndDriveImplications_rec( Aig_Man_t * p, Aig_Obj_t * pObj, int f, int fMax, Vec_Ptr_t * vSimInfo )
{
Aig_Obj_t * pFanout;
int k, iFanout = -1, Value0, Value1;
int Value = Saig_ManSimInfo2Get( vSimInfo, pObj, f );
assert( !Saig_ManSimInfo2IsOld( Value ) );
Saig_ManSimInfo2Set( vSimInfo, pObj, f, Saig_ManSimInfo2SetOld(Value) );
if ( (Aig_ObjIsCo(pObj) && f == fMax) || Saig_ObjIsPo(p, pObj) )
return;
if ( Saig_ObjIsLi( p, pObj ) )
{
assert( f < fMax );
pFanout = Saig_ObjLiToLo(p, pObj);
Value = Saig_ManSimInfo2Get( vSimInfo, pFanout, f+1 );
if ( !Saig_ManSimInfo2IsOld( Value ) )
Saig_ManSetAndDriveImplications_rec( p, pFanout, f+1, fMax, vSimInfo );
return;
}
assert( Aig_ObjIsCi(pObj) || Aig_ObjIsNode(pObj) || Aig_ObjIsConst1(pObj) );
Aig_ObjForEachFanout( p, pObj, pFanout, iFanout, k )
{
Value = Saig_ManSimInfo2Get( vSimInfo, pFanout, f );
if ( Saig_ManSimInfo2IsOld( Value ) )
continue;
if ( Aig_ObjIsCo(pFanout) )
{
Saig_ManSetAndDriveImplications_rec( p, pFanout, f, fMax, vSimInfo );
continue;
}
assert( Aig_ObjIsNode(pFanout) );
Value0 = Saig_ManSimInfo2Get( vSimInfo, Aig_ObjFanin0(pFanout), f );
Value1 = Saig_ManSimInfo2Get( vSimInfo, Aig_ObjFanin1(pFanout), f );
if ( Aig_ObjFaninC0(pFanout) )
Value0 = Saig_ManSimInfo2Not( Value0 );
if ( Aig_ObjFaninC1(pFanout) )
Value1 = Saig_ManSimInfo2Not( Value1 );
if ( Value0 == SAIG_ZER_OLD || Value1 == SAIG_ZER_OLD ||
(Value0 == SAIG_ONE_OLD && Value1 == SAIG_ONE_OLD) )
Saig_ManSetAndDriveImplications_rec( p, pFanout, f, fMax, vSimInfo );
}
/**Function*************************************************************
Synopsis [Load the network into FPGA manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
If_Man_t * Nwk_ManToIf( Aig_Man_t * p, If_Par_t * pPars, Vec_Ptr_t * vAigToIf )
{
extern Vec_Int_t * Saig_ManComputeSwitchProbs( Aig_Man_t * p, int nFrames, int nPref, int fProbOne );
Vec_Int_t * vSwitching = NULL, * vSwitching2 = NULL;
float * pSwitching = NULL, * pSwitching2 = NULL;
If_Man_t * pIfMan;
If_Obj_t * pIfObj;
Aig_Obj_t * pNode, * pFanin, * pPrev;
int i;
abctime clk = Abc_Clock();
// set the number of registers (switch activity will be combinational)
Aig_ManSetRegNum( p, 0 );
if ( pPars->fPower )
{
vSwitching = Saig_ManComputeSwitchProbs( p, 48, 16, 0 );
if ( pPars->fVerbose )
{
ABC_PRT( "Computing switching activity", Abc_Clock() - clk );
}
pSwitching = (float *)vSwitching->pArray;
vSwitching2 = Vec_IntStart( Aig_ManObjNumMax(p) );
pSwitching2 = (float *)vSwitching2->pArray;
}
// start the mapping manager and set its parameters
pIfMan = If_ManStart( pPars );
pIfMan->vSwitching = vSwitching2;
// load the AIG into the mapper
Aig_ManForEachObj( p, pNode, i )
{
if ( Aig_ObjIsAnd(pNode) )
{
pIfObj = If_ManCreateAnd( pIfMan,
If_NotCond( (If_Obj_t *)Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ),
If_NotCond( (If_Obj_t *)Aig_ObjFanin1(pNode)->pData, Aig_ObjFaninC1(pNode) ) );
// printf( "no%d=%d\n ", If_ObjId(pIfObj), If_ObjLevel(pIfObj) );
}
else if ( Aig_ObjIsCi(pNode) )
{
pIfObj = If_ManCreateCi( pIfMan );
If_ObjSetLevel( pIfObj, Aig_ObjLevel(pNode) );
// printf( "pi%d=%d\n ", If_ObjId(pIfObj), If_ObjLevel(pIfObj) );
if ( pIfMan->nLevelMax < (int)pIfObj->Level )
pIfMan->nLevelMax = (int)pIfObj->Level;
}
else if ( Aig_ObjIsCo(pNode) )
{
pIfObj = If_ManCreateCo( pIfMan, If_NotCond( (If_Obj_t *)Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ) );
// printf( "po%d=%d\n ", If_ObjId(pIfObj), If_ObjLevel(pIfObj) );
}
else if ( Aig_ObjIsConst1(pNode) )
pIfObj = If_ManConst1( pIfMan );
else // add the node to the mapper
assert( 0 );
// save the result
assert( Vec_PtrEntry(vAigToIf, i) == NULL );
Vec_PtrWriteEntry( vAigToIf, i, pIfObj );
pNode->pData = pIfObj;
if ( vSwitching2 )
pSwitching2[pIfObj->Id] = pSwitching[pNode->Id];
// set up the choice node
if ( Aig_ObjIsChoice( p, pNode ) )
{
for ( pPrev = pNode, pFanin = Aig_ObjEquiv(p, pNode); pFanin; pPrev = pFanin, pFanin = Aig_ObjEquiv(p, pFanin) )
If_ObjSetChoice( (If_Obj_t *)pPrev->pData, (If_Obj_t *)pFanin->pData );
If_ManCreateChoice( pIfMan, (If_Obj_t *)pNode->pData );
}
// assert( If_ObjLevel(pIfObj) == Aig_ObjLevel(pNode) );
}
if ( vSwitching )
Vec_IntFree( vSwitching );
return pIfMan;
}
static inline int Aig_ObjGetXsimFanin1( Aig_Obj_t * pObj )
{
int RetValue;
RetValue = Aig_ObjGetXsim(Aig_ObjFanin1(pObj));
return Aig_ObjFaninC1(pObj)? Aig_XsimInv(RetValue) : RetValue;
}
static inline Aig_Obj_t * Aig_ObjChild1Frames( Aig_Obj_t ** pObjMap, int nFs, Aig_Obj_t * pObj, int i ) { return Aig_ObjFanin1(pObj)? Aig_NotCond(Aig_ObjFrames(pObjMap,nFs,Aig_ObjFanin1(pObj),i), Aig_ObjFaninC1(pObj)) : NULL; }
static inline int Gia_ObjChild1Copy( Aig_Obj_t * pObj ) { return Gia_LitNotCond( Aig_ObjFanin1(pObj)->iData, Aig_ObjFaninC1(pObj) ); }
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Performs one retiming step forward.]
Description [Returns the pointer to the register output after retiming.]
SideEffects [Remember to run Aig_ManSetCioIds() in advance.]
SeeAlso []
***********************************************************************/
Aig_Obj_t * Saig_ManRetimeNodeFwd( Aig_Man_t * p, Aig_Obj_t * pObj, int fMakeBug )
{
Aig_Obj_t * pFanin0, * pFanin1;
Aig_Obj_t * pInput0, * pInput1;
Aig_Obj_t * pObjNew, * pObjLi, * pObjLo;
int fCompl;
assert( Saig_ManRegNum(p) > 0 );
assert( Aig_ObjIsNode(pObj) );
// get the fanins
pFanin0 = Aig_ObjFanin0(pObj);
pFanin1 = Aig_ObjFanin1(pObj);
// skip of they are not primary inputs
if ( !Aig_ObjIsCi(pFanin0) || !Aig_ObjIsCi(pFanin1) )
return NULL;
// skip of they are not register outputs
if ( !Saig_ObjIsLo(p, pFanin0) || !Saig_ObjIsLo(p, pFanin1) )
return NULL;
assert( Aig_ObjCioId(pFanin0) > 0 );
assert( Aig_ObjCioId(pFanin1) > 0 );
// skip latch guns
if ( !Aig_ObjIsTravIdCurrent(p, pFanin0) && !Aig_ObjIsTravIdCurrent(p, pFanin1) )
return NULL;
// get the inputs of these registers
pInput0 = Saig_ManLi( p, Aig_ObjCioId(pFanin0) - Saig_ManPiNum(p) );
pInput1 = Saig_ManLi( p, Aig_ObjCioId(pFanin1) - Saig_ManPiNum(p) );
pInput0 = Aig_ObjChild0( pInput0 );
pInput1 = Aig_ObjChild0( pInput1 );
pInput0 = Aig_NotCond( pInput0, Aig_ObjFaninC0(pObj) );
pInput1 = Aig_NotCond( pInput1, Aig_ObjFaninC1(pObj) );
// get the condition when the register should be complemetned
fCompl = Aig_ObjFaninC0(pObj) && Aig_ObjFaninC1(pObj);
if ( fMakeBug )
{
printf( "Introducing bug during retiming.\n" );
pInput1 = Aig_Not( pInput1 );
}
// create new node
pObjNew = Aig_And( p, pInput0, pInput1 );
// create new register input
pObjLi = Aig_ObjCreateCo( p, Aig_NotCond(pObjNew, fCompl) );
pObjLi->CioId = Aig_ManCoNum(p) - 1;
// create new register output
pObjLo = Aig_ObjCreateCi( p );
pObjLo->CioId = Aig_ManCiNum(p) - 1;
p->nRegs++;
// make sure the register is retimable.
Aig_ObjSetTravIdCurrent(p, pObjLo);
//printf( "Reg = %4d. Reg = %4d. Compl = %d. Phase = %d.\n",
// pFanin0->PioNum, pFanin1->PioNum, Aig_IsComplement(pObjNew), fCompl );
// return register output
return Aig_NotCond( pObjLo, fCompl );
}
