/**
* Initializes remaining bits of the Minimal provider.
* This is called after initializing HM and almost all other VMM components.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
VMMR3_INT_DECL(int) gimR3MinimalInitCompleted(PVM pVM)
{
/*
* Expose a generic hypervisor-agnostic leaf (originally defined VMware).
* The leaves range from 0x40000010 to 0x400000FF.
*
* This is done in the init. completed routine as we need PDM to be
* initialized (otherwise PDMApicGetTimerFreq() would fail).
*/
CPUMCPUIDLEAF HyperLeaf;
int rc = CPUMR3CpuIdGetLeaf(pVM, &HyperLeaf, 0x40000000, 0 /* uSubLeaf */);
if (RT_SUCCESS(rc))
{
HyperLeaf.uEax = UINT32_C(0x40000010); /* Maximum leaf we implement. */
rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
/*
* Insert missing zero leaves (you never know what missing leaves are
* going to return when read).
*/
for (uint32_t uLeaf = UINT32_C(0x40000001); uLeaf < UINT32_C(0x40000010); uLeaf++)
{
rc = CPUMR3CpuIdGetLeaf(pVM, &HyperLeaf, uLeaf, 0 /* uSubLeaf */);
if (RT_FAILURE(rc))
{
RT_ZERO(HyperLeaf);
HyperLeaf.uLeaf = uLeaf;
rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
}
}
/*
* Add the timing information hypervisor leaf.
* MacOS X uses this to determine the TSC, bus frequency. See @bugref{7270}.
*
* EAX - TSC frequency in KHz.
* EBX - APIC frequency in KHz.
* ECX, EDX - Reserved.
*/
uint64_t uApicFreq;
rc = PDMApicGetTimerFreq(pVM, &uApicFreq);
AssertLogRelRCReturn(rc, rc);
RT_ZERO(HyperLeaf);
HyperLeaf.uLeaf = UINT32_C(0x40000010);
HyperLeaf.uEax = TMCpuTicksPerSecond(pVM) / UINT64_C(1000);
HyperLeaf.uEbx = (uApicFreq + 500) / UINT64_C(1000);
rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
}
else
LogRel(("GIM: Minimal: failed to get hypervisor leaf 0x40000000.\n"));
return VINF_SUCCESS;
}
HRESULT VirtualBoxSDS::FinalConstruct()
{
LogRelFlowThisFuncEnter();
int vrc = RTCritSectRwInit(&m_MapCritSect);
AssertLogRelRCReturn(vrc, E_FAIL);
#ifdef WITH_WATCHER
vrc = RTCritSectInit(&m_WatcherCritSect);
AssertLogRelRCReturn(vrc, E_FAIL);
#endif
LogRelFlowThisFuncLeave();
return S_OK;
}
/**
* Initializes remaining bits of the Hyper-V provider.
*
* This is called after initializing HM and almost all other VMM components.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
VMMR3_INT_DECL(int) gimR3HvInitCompleted(PVM pVM)
{
PGIMHV pHv = &pVM->gim.s.u.Hv;
/*
* Determine interface capabilities based on the version.
*/
if (!pVM->gim.s.u32Version)
{
/* Hypervisor capabilities; features used by the hypervisor. */
pHv->uHyperCaps = HMIsNestedPagingActive(pVM) ? GIM_HV_HOST_FEAT_NESTED_PAGING : 0;
pHv->uHyperCaps |= HMAreMsrBitmapsAvailable(pVM) ? GIM_HV_HOST_FEAT_MSR_BITMAP : 0;
}
CPUMCPUIDLEAF HyperLeaf;
RT_ZERO(HyperLeaf);
HyperLeaf.uLeaf = UINT32_C(0x40000006);
HyperLeaf.uEax = pHv->uHyperCaps;
HyperLeaf.uEbx = 0;
HyperLeaf.uEcx = 0;
HyperLeaf.uEdx = 0;
int rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
return rc;
}
/**
* Initializes remaining bits of the KVM provider.
*
* This is called after initializing HM and almost all other VMM components.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
VMMR3_INT_DECL(int) gimR3KvmInitCompleted(PVM pVM)
{
PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
pKvm->cTscTicksPerSecond = TMCpuTicksPerSecond(pVM);
if (TMR3CpuTickIsFixedRateMonotonic(pVM, true /* fWithParavirtEnabled */))
{
/** @todo We might want to consider just enabling this bit *always*. As far
* as I can see in the Linux guest, the "TSC_STABLE" bit is only
* translated as a "monotonic" bit which even in Async systems we
* -should- be reporting a strictly monotonic TSC to the guest. */
pKvm->uBaseFeat |= GIM_KVM_BASE_FEAT_TSC_STABLE;
CPUMCPUIDLEAF HyperLeaf;
RT_ZERO(HyperLeaf);
HyperLeaf.uLeaf = UINT32_C(0x40000001);
HyperLeaf.uEax = pKvm->uBaseFeat;
HyperLeaf.uEbx = 0;
HyperLeaf.uEcx = 0;
HyperLeaf.uEdx = 0;
int rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
}
return VINF_SUCCESS;
}
/**
* Fudges the MSRs that guest are known to access in some odd cases.
*
* A typical example is a VM that has been moved between different hosts where
* for instance the cpu vendor differs.
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
*/
int cpumR3MsrApplyFudge(PVM pVM)
{
/*
* Basic.
*/
static CPUMMSRRANGE const s_aFudgeMsrs[] =
{
MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
MVO(0x00000017, "IA32_PLATFORM_ID", 0),
MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
MVI(0x0000008b, "BIOS_SIGN", 0),
MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
};
int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
AssertLogRelRCReturn(rc, rc);
/*
* XP might mistake opterons and other newer CPUs for P4s.
*/
if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
{
static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
{
MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
};
rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
AssertLogRelRCReturn(rc, rc);
}
return rc;
}
/**
* Read the current CPU timestamp counter.
*
* @returns Gets the CPU tsc.
* @param pVCpu The cross context virtual CPU structure.
* @param fCheckTimers Whether to check timers.
*/
DECLINLINE(uint64_t) tmCpuTickGetInternal(PVMCPU pVCpu, bool fCheckTimers)
{
uint64_t u64;
if (RT_LIKELY(pVCpu->tm.s.fTSCTicking))
{
PVM pVM = pVCpu->CTX_SUFF(pVM);
switch (pVM->tm.s.enmTSCMode)
{
case TMTSCMODE_REAL_TSC_OFFSET:
u64 = SUPReadTsc();
break;
case TMTSCMODE_VIRT_TSC_EMULATED:
case TMTSCMODE_DYNAMIC:
u64 = tmCpuTickGetRawVirtual(pVM, fCheckTimers);
break;
#ifndef IN_RC
case TMTSCMODE_NATIVE_API:
{
u64 = 0;
int rcNem = NEMHCQueryCpuTick(pVCpu, &u64, NULL);
AssertLogRelRCReturn(rcNem, SUPReadTsc());
break;
}
#endif
default:
AssertFailedBreakStmt(u64 = SUPReadTsc());
}
u64 -= pVCpu->tm.s.offTSCRawSrc;
/* Always return a value higher than what the guest has already seen. */
if (RT_LIKELY(u64 > pVCpu->tm.s.u64TSCLastSeen))
pVCpu->tm.s.u64TSCLastSeen = u64;
else
{
STAM_COUNTER_INC(&pVM->tm.s.StatTSCUnderflow);
pVCpu->tm.s.u64TSCLastSeen += 64; /** @todo choose a good increment here */
u64 = pVCpu->tm.s.u64TSCLastSeen;
}
}
else
u64 = pVCpu->tm.s.u64TSC;
return u64;
}
/**
* Reads the CFGM configuration of the DBGC.
*
* Popuplates the PDBGC::pszHistoryFile, PDBGC::pszGlobalInitScript and
* PDBGC::pszLocalInitScript members.
*
* @returns VBox status code.
* @param pDbgc The console instance.
* @param pUVM The user mode VM handle.
*/
static int dbgcReadConfig(PDBGC pDbgc, PUVM pUVM)
{
/*
* Get and validate the configuration node.
*/
PCFGMNODE pNode = CFGMR3GetChild(CFGMR3GetRootU(pUVM), "DBGC");
int rc = CFGMR3ValidateConfig(pNode, "/DBGC/",
"Enabled|"
"HistoryFile|"
"LocalInitScript|"
"GlobalInitScript",
"", "DBGC", 0);
AssertRCReturn(rc, rc);
/*
* Query the values.
*/
char szHomeDefault[RTPATH_MAX];
rc = RTPathUserHome(szHomeDefault, sizeof(szHomeDefault) - 32);
AssertLogRelRCReturn(rc, rc);
size_t cchHome = strlen(szHomeDefault);
/** @cfgm{/DBGC/HistoryFile, string, ${HOME}/.vboxdbgc-history}
* The command history file of the VBox debugger. */
rc = RTPathAppend(szHomeDefault, sizeof(szHomeDefault), ".vboxdbgc-history");
AssertLogRelRCReturn(rc, rc);
char szPath[RTPATH_MAX];
rc = CFGMR3QueryStringDef(pNode, "HistoryFile", szPath, sizeof(szPath), szHomeDefault);
AssertLogRelRCReturn(rc, rc);
pDbgc->pszHistoryFile = RTStrDup(szPath);
AssertReturn(pDbgc->pszHistoryFile, VERR_NO_STR_MEMORY);
/** @cfgm{/DBGC/GlobalInitFile, string, ${HOME}/.vboxdbgc-init}
* The global init script of the VBox debugger. */
szHomeDefault[cchHome] = '\0';
rc = RTPathAppend(szHomeDefault, sizeof(szHomeDefault), ".vboxdbgc-init");
AssertLogRelRCReturn(rc, rc);
rc = CFGMR3QueryStringDef(pNode, "GlobalInitScript", szPath, sizeof(szPath), szHomeDefault);
AssertLogRelRCReturn(rc, rc);
pDbgc->pszGlobalInitScript = RTStrDup(szPath);
AssertReturn(pDbgc->pszGlobalInitScript, VERR_NO_STR_MEMORY);
/** @cfgm{/DBGC/LocalInitFile, string, none}
* The VM local init script of the VBox debugger. */
rc = CFGMR3QueryString(pNode, "LocalInitScript", szPath, sizeof(szPath));
if (RT_SUCCESS(rc))
{
pDbgc->pszLocalInitScript = RTStrDup(szPath);
AssertReturn(pDbgc->pszLocalInitScript, VERR_NO_STR_MEMORY);
}
else
{
AssertLogRelReturn(rc == VERR_CFGM_VALUE_NOT_FOUND || rc == VERR_CFGM_NO_PARENT, rc);
pDbgc->pszLocalInitScript = NULL;
}
return VINF_SUCCESS;
}
/**
* @interface_method_impl{Construct a NAT network transport driver instance,
* PDMDRVREG,pfnDestruct}
*/
static DECLCALLBACK(int) drvR3NetShaperConstruct(PPDMDRVINS pDrvIns, PCFGMNODE pCfg, uint32_t fFlags)
{
PDRVNETSHAPER pThis = PDMINS_2_DATA(pDrvIns, PDRVNETSHAPER);
LogFlow(("drvNetShaperConstruct:\n"));
PDMDRV_CHECK_VERSIONS_RETURN(pDrvIns);
/*
* Init the static parts.
*/
pThis->pDrvInsR3 = pDrvIns;
pThis->pDrvInsR0 = PDMDRVINS_2_R0PTR(pDrvIns);
/* IBase */
pDrvIns->IBase.pfnQueryInterface = drvR3NetShaperIBase_QueryInterface;
pThis->IBaseR0.pfnQueryInterface = drvR3NetShaperIBaseR0_QueryInterface;
pThis->IBaseRC.pfnQueryInterface = drvR3NetShaperIBaseRC_QueryInterface;
/* INetworkUp */
pThis->INetworkUpR3.pfnBeginXmit = drvNetShaperUp_BeginXmit;
pThis->INetworkUpR3.pfnAllocBuf = drvNetShaperUp_AllocBuf;
pThis->INetworkUpR3.pfnFreeBuf = drvNetShaperUp_FreeBuf;
pThis->INetworkUpR3.pfnSendBuf = drvNetShaperUp_SendBuf;
pThis->INetworkUpR3.pfnEndXmit = drvNetShaperUp_EndXmit;
pThis->INetworkUpR3.pfnSetPromiscuousMode = drvNetShaperUp_SetPromiscuousMode;
pThis->INetworkUpR3.pfnNotifyLinkChanged = drvR3NetShaperUp_NotifyLinkChanged;
/* Resolve the ring-0 context interface addresses. */
int rc = pDrvIns->pHlpR3->pfnLdrGetR0InterfaceSymbols(pDrvIns, &pThis->INetworkUpR0,
sizeof(pThis->INetworkUpR0),
"drvNetShaperUp_", PDMINETWORKUP_SYM_LIST);
AssertLogRelRCReturn(rc, rc);
/* INetworkDown */
pThis->INetworkDown.pfnWaitReceiveAvail = drvR3NetShaperDown_WaitReceiveAvail;
pThis->INetworkDown.pfnReceive = drvR3NetShaperDown_Receive;
pThis->INetworkDown.pfnReceiveGso = drvR3NetShaperDown_ReceiveGso;
pThis->INetworkDown.pfnXmitPending = drvR3NetShaperDown_XmitPending;
/* INetworkConfig */
pThis->INetworkConfig.pfnGetMac = drvR3NetShaperDownCfg_GetMac;
pThis->INetworkConfig.pfnGetLinkState = drvR3NetShaperDownCfg_GetLinkState;
pThis->INetworkConfig.pfnSetLinkState = drvR3NetShaperDownCfg_SetLinkState;
/*
* Create the locks.
*/
rc = PDMDrvHlpCritSectInit(pDrvIns, &pThis->XmitLock, RT_SRC_POS, "NetShaper");
AssertRCReturn(rc, rc);
/*
* Validate the config.
*/
if (!CFGMR3AreValuesValid(pCfg, "BwGroup\0"))
return VERR_PDM_DRVINS_UNKNOWN_CFG_VALUES;
/*
* Find the bandwidth group we have to attach to.
*/
rc = CFGMR3QueryStringAlloc(pCfg, "BwGroup", &pThis->pszBwGroup);
if (RT_FAILURE(rc) && rc != VERR_CFGM_VALUE_NOT_FOUND)
{
rc = PDMDRV_SET_ERROR(pDrvIns, rc,
N_("DrvNetShaper: Configuration error: Querying \"BwGroup\" as string failed"));
return rc;
}
else
rc = VINF_SUCCESS;
pThis->Filter.pIDrvNetR3 = &pThis->INetworkDown;
rc = PDMDrvHlpNetShaperAttach(pDrvIns, pThis->pszBwGroup, &pThis->Filter);
if (RT_FAILURE(rc))
{
rc = PDMDRV_SET_ERROR(pDrvIns, rc,
N_("DrvNetShaper: Configuration error: Failed to attach to bandwidth group"));
return rc;
}
/*
* Query the network port interface.
*/
pThis->pIAboveNet = PDMIBASE_QUERY_INTERFACE(pDrvIns->pUpBase, PDMINETWORKDOWN);
if (!pThis->pIAboveNet)
{
AssertMsgFailed(("Configuration error: the above device/driver didn't export the network port interface!\n"));
return VERR_PDM_MISSING_INTERFACE_ABOVE;
}
/*
* Query the network config interface.
*/
pThis->pIAboveConfig = PDMIBASE_QUERY_INTERFACE(pDrvIns->pUpBase, PDMINETWORKCONFIG);
if (!pThis->pIAboveConfig)
{
AssertMsgFailed(("Configuration error: the above device/driver didn't export the network config interface!\n"));
return VERR_PDM_MISSING_INTERFACE_ABOVE;
}
/*
* Query the network connector interface.
*/
PPDMIBASE pBaseDown;
rc = PDMDrvHlpAttach(pDrvIns, fFlags, &pBaseDown);
if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
|| rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
{
pThis->pIBelowNetR3 = NULL;
pThis->pIBelowNetR0 = NIL_RTR0PTR;
}
else if (RT_SUCCESS(rc))
{
pThis->pIBelowNetR3 = PDMIBASE_QUERY_INTERFACE(pBaseDown, PDMINETWORKUP);
if (!pThis->pIBelowNetR3)
{
AssertMsgFailed(("Configuration error: the driver below didn't export the network connector interface!\n"));
return VERR_PDM_MISSING_INTERFACE_BELOW;
}
PPDMIBASER0 pBaseR0 = PDMIBASE_QUERY_INTERFACE(pBaseDown, PDMIBASER0);
pThis->pIBelowNetR0 = pBaseR0 ? pBaseR0->pfnQueryInterface(pBaseR0, PDMINETWORKUP_IID) : NIL_RTR0PTR;
}
else
{
AssertMsgFailed(("Failed to attach to driver below! rc=%Rrc\n", rc));
return rc;
}
/*
* Register statistics.
*/
PDMDrvHlpSTAMRegCounterEx(pDrvIns, &pThis->StatXmitBytesRequested, "Bytes/Tx/Requested", STAMUNIT_BYTES, "Number of requested TX bytes.");
PDMDrvHlpSTAMRegCounterEx(pDrvIns, &pThis->StatXmitBytesDenied, "Bytes/Tx/Denied", STAMUNIT_BYTES, "Number of denied TX bytes.");
PDMDrvHlpSTAMRegCounterEx(pDrvIns, &pThis->StatXmitBytesGranted, "Bytes/Tx/Granted", STAMUNIT_BYTES, "Number of granted TX bytes.");
PDMDrvHlpSTAMRegCounter(pDrvIns, &pThis->StatXmitPktsRequested, "Packets/Tx/Requested", "Number of requested TX packets.");
PDMDrvHlpSTAMRegCounter(pDrvIns, &pThis->StatXmitPktsDenied, "Packets/Tx/Denied", "Number of denied TX packets.");
PDMDrvHlpSTAMRegCounter(pDrvIns, &pThis->StatXmitPktsGranted, "Packets/Tx/Granted", "Number of granted TX packets.");
PDMDrvHlpSTAMRegCounter(pDrvIns, &pThis->StatXmitPendingCalled, "Tx/WakeUp", "Number of wakeup TX calls.");
return VINF_SUCCESS;
}
/**
* Initializes the Hyper-V GIM provider.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param uVersion The interface version this VM should use.
*/
VMMR3_INT_DECL(int) gimR3HvInit(PVM pVM)
{
AssertReturn(pVM, VERR_INVALID_PARAMETER);
AssertReturn(pVM->gim.s.enmProviderId == GIMPROVIDERID_HYPERV, VERR_INTERNAL_ERROR_5);
int rc;
PGIMHV pHv = &pVM->gim.s.u.Hv;
/*
* Determine interface capabilities based on the version.
*/
if (!pVM->gim.s.u32Version)
{
/* Basic features. */
pHv->uBaseFeat = 0
//| GIM_HV_BASE_FEAT_VP_RUNTIME_MSR
| GIM_HV_BASE_FEAT_PART_TIME_REF_COUNT_MSR
//| GIM_HV_BASE_FEAT_BASIC_SYNTH_IC
//| GIM_HV_BASE_FEAT_SYNTH_TIMER_MSRS
| GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS
| GIM_HV_BASE_FEAT_HYPERCALL_MSRS
| GIM_HV_BASE_FEAT_VP_ID_MSR
| GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR
//| GIM_HV_BASE_FEAT_STAT_PAGES_MSR
| GIM_HV_BASE_FEAT_PART_REF_TSC_MSR
//| GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR
| GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS
//| GIM_HV_BASE_FEAT_DEBUG_MSRS
;
/* Miscellaneous features. */
pHv->uMiscFeat = GIM_HV_MISC_FEAT_TIMER_FREQ;
/* Hypervisor recommendations to the guest. */
pHv->uHyperHints = GIM_HV_HINT_MSR_FOR_SYS_RESET
| GIM_HV_HINT_RELAX_TIME_CHECKS;
}
/*
* Populate the required fields in MMIO2 region records for registering.
*/
AssertCompile(GIM_HV_PAGE_SIZE == PAGE_SIZE);
PGIMMMIO2REGION pRegion = &pHv->aMmio2Regions[GIM_HV_HYPERCALL_PAGE_REGION_IDX];
pRegion->iRegion = GIM_HV_HYPERCALL_PAGE_REGION_IDX;
pRegion->fRCMapping = false;
pRegion->cbRegion = PAGE_SIZE;
pRegion->GCPhysPage = NIL_RTGCPHYS;
RTStrCopy(pRegion->szDescription, sizeof(pRegion->szDescription), "Hyper-V hypercall page");
pRegion = &pHv->aMmio2Regions[GIM_HV_REF_TSC_PAGE_REGION_IDX];
pRegion->iRegion = GIM_HV_REF_TSC_PAGE_REGION_IDX;
pRegion->fRCMapping = false;
pRegion->cbRegion = PAGE_SIZE;
pRegion->GCPhysPage = NIL_RTGCPHYS;
RTStrCopy(pRegion->szDescription, sizeof(pRegion->szDescription), "Hyper-V TSC page");
/*
* Make sure the CPU ID bit are in accordance to the Hyper-V
* requirement and other paranoia checks.
* See "Requirements for implementing the Microsoft hypervisor interface" spec.
*/
Assert(!(pHv->uPartFlags & ( GIM_HV_PART_FLAGS_CREATE_PART
| GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL
| GIM_HV_PART_FLAGS_ACCESS_PART_ID
| GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS
| GIM_HV_PART_FLAGS_CREATE_PORT
| GIM_HV_PART_FLAGS_ACCESS_STATS
| GIM_HV_PART_FLAGS_CPU_MGMT
| GIM_HV_PART_FLAGS_CPU_PROFILER)));
Assert((pHv->uBaseFeat & (GIM_HV_BASE_FEAT_HYPERCALL_MSRS | GIM_HV_BASE_FEAT_VP_ID_MSR))
== (GIM_HV_BASE_FEAT_HYPERCALL_MSRS | GIM_HV_BASE_FEAT_VP_ID_MSR));
for (unsigned i = 0; i < RT_ELEMENTS(pHv->aMmio2Regions); i++)
{
PCGIMMMIO2REGION pcCur = &pHv->aMmio2Regions[i];
Assert(!pcCur->fRCMapping);
Assert(!pcCur->fMapped);
Assert(pcCur->GCPhysPage == NIL_RTGCPHYS);
}
/*
* Expose HVP (Hypervisor Present) bit to the guest.
*/
CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
/*
* Modify the standard hypervisor leaves for Hyper-V.
*/
CPUMCPUIDLEAF HyperLeaf;
RT_ZERO(HyperLeaf);
HyperLeaf.uLeaf = UINT32_C(0x40000000);
HyperLeaf.uEax = UINT32_C(0x40000006); /* Minimum value for Hyper-V is 0x40000005. */
HyperLeaf.uEbx = 0x7263694D; /* 'Micr' */
HyperLeaf.uEcx = 0x666F736F; /* 'osof' */
HyperLeaf.uEdx = 0x76482074; /* 't Hv' */
rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
HyperLeaf.uLeaf = UINT32_C(0x40000001);
HyperLeaf.uEax = 0x31237648; /* 'Hv#1' */
HyperLeaf.uEbx = 0; /* Reserved */
HyperLeaf.uEcx = 0; /* Reserved */
HyperLeaf.uEdx = 0; /* Reserved */
rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
/*
* Add Hyper-V specific leaves.
*/
HyperLeaf.uLeaf = UINT32_C(0x40000002); /* MBZ until MSR_GIM_HV_GUEST_OS_ID is set by the guest. */
HyperLeaf.uEax = 0;
HyperLeaf.uEbx = 0;
HyperLeaf.uEcx = 0;
HyperLeaf.uEdx = 0;
rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
HyperLeaf.uLeaf = UINT32_C(0x40000003);
HyperLeaf.uEax = pHv->uBaseFeat;
HyperLeaf.uEbx = pHv->uPartFlags;
HyperLeaf.uEcx = pHv->uPowMgmtFeat;
HyperLeaf.uEdx = pHv->uMiscFeat;
rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
HyperLeaf.uLeaf = UINT32_C(0x40000004);
HyperLeaf.uEax = pHv->uHyperHints;
HyperLeaf.uEbx = 0xffffffff;
HyperLeaf.uEcx = 0;
HyperLeaf.uEdx = 0;
rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
/*
* Insert all MSR ranges of Hyper-V.
*/
for (unsigned i = 0; i < RT_ELEMENTS(g_aMsrRanges_HyperV); i++)
{
rc = CPUMR3MsrRangesInsert(pVM, &g_aMsrRanges_HyperV[i]);
AssertLogRelRCReturn(rc, rc);
}
return VINF_SUCCESS;
}
static int pdmacFileInitialize(PPDMASYNCCOMPLETIONEPCLASS pClassGlobals, PCFGMNODE pCfgNode)
{
PPDMASYNCCOMPLETIONEPCLASSFILE pEpClassFile = (PPDMASYNCCOMPLETIONEPCLASSFILE)pClassGlobals;
RTFILEAIOLIMITS AioLimits; /** < Async I/O limitations. */
int rc = RTFileAioGetLimits(&AioLimits);
#ifdef DEBUG
if (RT_SUCCESS(rc) && RTEnvExist("VBOX_ASYNC_IO_FAILBACK"))
rc = VERR_ENV_VAR_NOT_FOUND;
#endif
if (RT_FAILURE(rc))
{
LogRel(("AIO: Async I/O manager not supported (rc=%Rrc). Falling back to simple manager\n",
rc));
pEpClassFile->enmMgrTypeOverride = PDMACEPFILEMGRTYPE_SIMPLE;
pEpClassFile->enmEpBackendDefault = PDMACFILEEPBACKEND_BUFFERED;
}
else
{
pEpClassFile->uBitmaskAlignment = AioLimits.cbBufferAlignment ? ~((RTR3UINTPTR)AioLimits.cbBufferAlignment - 1) : RTR3UINTPTR_MAX;
pEpClassFile->cReqsOutstandingMax = AioLimits.cReqsOutstandingMax;
if (pCfgNode)
{
/* Query the default manager type */
char *pszVal = NULL;
rc = CFGMR3QueryStringAllocDef(pCfgNode, "IoMgr", &pszVal, "Async");
AssertLogRelRCReturn(rc, rc);
rc = pdmacFileMgrTypeFromName(pszVal, &pEpClassFile->enmMgrTypeOverride);
MMR3HeapFree(pszVal);
if (RT_FAILURE(rc))
return rc;
LogRel(("AIOMgr: Default manager type is \"%s\"\n", pdmacFileMgrTypeToName(pEpClassFile->enmMgrTypeOverride)));
/* Query default backend type */
rc = CFGMR3QueryStringAllocDef(pCfgNode, "FileBackend", &pszVal, "NonBuffered");
AssertLogRelRCReturn(rc, rc);
rc = pdmacFileBackendTypeFromName(pszVal, &pEpClassFile->enmEpBackendDefault);
MMR3HeapFree(pszVal);
if (RT_FAILURE(rc))
return rc;
LogRel(("AIOMgr: Default file backend is \"%s\"\n", pdmacFileBackendTypeToName(pEpClassFile->enmEpBackendDefault)));
#ifdef RT_OS_LINUX
if ( pEpClassFile->enmMgrTypeOverride == PDMACEPFILEMGRTYPE_ASYNC
&& pEpClassFile->enmEpBackendDefault == PDMACFILEEPBACKEND_BUFFERED)
{
LogRel(("AIOMgr: Linux does not support buffered async I/O, changing to non buffered\n"));
pEpClassFile->enmEpBackendDefault = PDMACFILEEPBACKEND_NON_BUFFERED;
}
#endif
}
else
{
/* No configuration supplied, set defaults */
pEpClassFile->enmEpBackendDefault = PDMACFILEEPBACKEND_NON_BUFFERED;
pEpClassFile->enmMgrTypeOverride = PDMACEPFILEMGRTYPE_ASYNC;
}
}
/* Init critical section. */
rc = RTCritSectInit(&pEpClassFile->CritSect);
#ifdef VBOX_WITH_DEBUGGER
/* Install the error injection handler. */
if (RT_SUCCESS(rc))
{
rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
AssertRC(rc);
}
#ifdef PDM_ASYNC_COMPLETION_FILE_WITH_DELAY
rc = TMR3TimerCreateInternal(pEpClassFile->Core.pVM, TMCLOCK_REAL, pdmacR3TimerCallback, pEpClassFile, "AC Delay", &pEpClassFile->pTimer);
AssertRC(rc);
pEpClassFile->cMilliesNext = UINT64_MAX;
#endif
#endif
return rc;
}
/**
* Initializes the KVM GIM provider.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param uVersion The interface version this VM should use.
*/
VMMR3_INT_DECL(int) gimR3KvmInit(PVM pVM)
{
AssertReturn(pVM, VERR_INVALID_PARAMETER);
AssertReturn(pVM->gim.s.enmProviderId == GIMPROVIDERID_KVM, VERR_INTERNAL_ERROR_5);
int rc;
PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
/*
* Determine interface capabilities based on the version.
*/
if (!pVM->gim.s.u32Version)
{
/* Basic features. */
pKvm->uBaseFeat = 0
| GIM_KVM_BASE_FEAT_CLOCK_OLD
//| GIM_KVM_BASE_FEAT_NOP_IO_DELAY
//| GIM_KVM_BASE_FEAT_MMU_OP
| GIM_KVM_BASE_FEAT_CLOCK
//| GIM_KVM_BASE_FEAT_ASYNC_PF
//| GIM_KVM_BASE_FEAT_STEAL_TIME
//| GIM_KVM_BASE_FEAT_PV_EOI
| GIM_KVM_BASE_FEAT_PV_UNHALT
;
/* Rest of the features are determined in gimR3KvmInitCompleted(). */
}
/*
* Expose HVP (Hypervisor Present) bit to the guest.
*/
CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
/*
* Modify the standard hypervisor leaves for KVM.
*/
CPUMCPUIDLEAF HyperLeaf;
RT_ZERO(HyperLeaf);
HyperLeaf.uLeaf = UINT32_C(0x40000000);
HyperLeaf.uEax = UINT32_C(0x40000001); /* Minimum value for KVM is 0x40000001. */
HyperLeaf.uEbx = 0x4B4D564B; /* 'KVMK' */
HyperLeaf.uEcx = 0x564B4D56; /* 'VMKV' */
HyperLeaf.uEdx = 0x0000004D; /* 'M000' */
rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
/*
* Add KVM specific leaves.
*/
HyperLeaf.uLeaf = UINT32_C(0x40000001);
HyperLeaf.uEax = pKvm->uBaseFeat;
HyperLeaf.uEbx = 0; /* Reserved */
HyperLeaf.uEcx = 0; /* Reserved */
HyperLeaf.uEdx = 0; /* Reserved */
rc = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
AssertLogRelRCReturn(rc, rc);
/*
* Insert all MSR ranges of KVM.
*/
for (unsigned i = 0; i < RT_ELEMENTS(g_aMsrRanges_Kvm); i++)
{
rc = CPUMR3MsrRangesInsert(pVM, &g_aMsrRanges_Kvm[i]);
AssertLogRelRCReturn(rc, rc);
}
/*
* Setup hypercall and #UD handling.
*/
for (VMCPUID i = 0; i < pVM->cCpus; i++)
VMMHypercallsEnable(&pVM->aCpus[i]);
if (ASMIsAmdCpu())
{
pKvm->fTrapXcptUD = true;
pKvm->uOpCodeNative = OP_VMMCALL;
}
else
{
Assert(ASMIsIntelCpu() || ASMIsViaCentaurCpu());
pKvm->fTrapXcptUD = false;
pKvm->uOpCodeNative = OP_VMCALL;
}
/* We always need to trap VMCALL/VMMCALL hypercall using #UDs for raw-mode VMs. */
if (!HMIsEnabled(pVM))
pKvm->fTrapXcptUD = true;
return VINF_SUCCESS;
}
/**
* Initializes the interpreted execution manager.
*
* This must be called after CPUM as we're quering information from CPUM about
* the guest and host CPUs.
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
*/
VMMR3DECL(int) IEMR3Init(PVM pVM)
{
uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
{
PVMCPU pVCpu = &pVM->aCpus[idCpu];
pVCpu->iem.s.pCtxR3 = CPUMQueryGuestCtxPtr(pVCpu);
pVCpu->iem.s.pCtxR0 = VM_R0_ADDR(pVM, pVCpu->iem.s.pCtxR3);
pVCpu->iem.s.pCtxRC = VM_RC_ADDR(pVM, pVCpu->iem.s.pCtxR3);
pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
"Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
"Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
"Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
#ifdef VBOX_WITH_STATISTICS
STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
#endif
STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
"Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
"Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
"Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
"Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
"Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
"Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
/* Allocate instruction statistics and register them. */
pVCpu->iem.s.pStatsR3 = (PIEMINSTRSTATS)MMR3HeapAllocZ(pVM, MM_TAG_IEM, sizeof(IEMINSTRSTATS));
AssertLogRelReturn(pVCpu->iem.s.pStatsR3, VERR_NO_MEMORY);
int rc = MMHyperAlloc(pVM, sizeof(IEMINSTRSTATS), sizeof(uint64_t), MM_TAG_IEM, (void **)&pVCpu->iem.s.pStatsCCR3);
AssertLogRelRCReturn(rc, rc);
pVCpu->iem.s.pStatsR0 = MMHyperR3ToR0(pVM, pVCpu->iem.s.pStatsCCR3);
pVCpu->iem.s.pStatsRC = MMHyperR3ToR0(pVM, pVCpu->iem.s.pStatsCCR3);
# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
STAMR3RegisterF(pVM, &pVCpu->iem.s.pStatsCCR3->a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
STAMR3RegisterF(pVM, &pVCpu->iem.s.pStatsR3->a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
# include "IEMInstructionStatisticsTmpl.h"
# undef IEM_DO_INSTR_STAT
#endif
/*
* Host and guest CPU information.
*/
if (idCpu == 0)
{
pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
{
case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
}
LogRel(("IEM: TargetCpu=%s, Microarch=%s\n", iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMR3MicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch)));
#endif
}
else
{
pVCpu->iem.s.enmCpuVendor = pVM->aCpus[0].iem.s.enmCpuVendor;
pVCpu->iem.s.enmHostCpuVendor = pVM->aCpus[0].iem.s.enmHostCpuVendor;
#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
pVCpu->iem.s.uTargetCpu = pVM->aCpus[0].iem.s.uTargetCpu;
#endif
}
/*
* Mark all buffers free.
*/
uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
while (iMemMap-- > 0)
pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
}
return VINF_SUCCESS;
}
