static int mtk_afe_dl1_awb_probe(struct snd_soc_platform *platform)
{
printk("mtk_afe_dl1_awb_probe\n");
AudDrv_Allocate_mem_Buffer(platform->dev, Soc_Aud_Digital_Block_MEM_AWB, AWB_MAX_BUFFER_SIZE);
Awb_Capture_dma_buf = Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_AWB);
return 0;
}
static int mtk_pcm_fmtx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct snd_dma_buffer *dma_buf = &substream->dma_buffer;
int ret = 0;
PRINTK_AUD_FMTX("mtk_pcm_fmtx_hw_params \n");
if (fake_buffer)
{
/* runtime->dma_bytes has to be set manually to allow mmap */
substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
// here to allcoate sram to hardware ---------------------------
AudDrv_Allocate_mem_Buffer(mDev, Soc_Aud_Digital_Block_MEM_DL1, substream->runtime->dma_bytes);
substream->runtime->dma_area = (unsigned char *)Get_Afe_SramBase_Pointer();
substream->runtime->dma_addr = AFE_INTERNAL_SRAM_PHY_BASE;
// -------------------------------------------------------
PRINTK_AUD_FMTX("1 dma_bytes = %d dma_area = %p dma_addr = 0x%x\n",
substream->runtime->dma_bytes, substream->runtime->dma_area, substream->runtime->dma_addr);
return 0;
}
else
{
dma_buf->dev.type = SNDRV_DMA_TYPE_DEV;
dma_buf->dev.dev = substream->pcm->card->dev;
dma_buf->private_data = NULL;
ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
}
PRINTK_AUD_FMTX("2 dma_bytes = %d dma_area = %p dma_addr = 0x%x\n",
substream->runtime->dma_bytes, substream->runtime->dma_area, substream->runtime->dma_addr);
return ret;
}
static int mtk_asoc_bt_dai_probe(struct snd_soc_platform *platform)
{
printk("mtk_asoc_bt_dai_probe\n");
AudDrv_Allocate_mem_Buffer(Soc_Aud_Digital_Block_MEM_DAI, BT_DAI_MAX_BUFFER_SIZE);
Bt_Dai_Capture_dma_buf = Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_DAI);
return 0;
}
static int mtk_afe_capture_probe(struct snd_soc_platform *platform)
{
printk("mtk_afe_capture_probe\n");
AudDrv_Allocate_mem_Buffer(platform->dev, Soc_Aud_Digital_Block_MEM_VUL, UL1_MAX_BUFFER_SIZE);
Capture_dma_buf = Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_VUL);
mAudioDigitalI2S = kzalloc(sizeof(AudioDigtalI2S), GFP_KERNEL);
return 0;
}
static int mtk_asoc_dl1_probe(struct snd_soc_platform *platform)
{
PRINTK_AUDDRV("mtk_asoc_dl1_probe\n");
// allocate dram
AudDrv_Allocate_mem_Buffer(platform->dev, Soc_Aud_Digital_Block_MEM_DL1, Dl1_MAX_BUFFER_SIZE);
Dl1_Playback_dma_buf = Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_DL1);
return 0;
}
static int mtk_afe_I2S0dl1_probe(struct snd_soc_platform *platform)
{
snd_soc_add_platform_controls(platform, Audio_snd_I2S0dl1_controls,
ARRAY_SIZE(Audio_snd_I2S0dl1_controls));
// allocate dram
AudDrv_Allocate_mem_Buffer(Soc_Aud_Digital_Block_MEM_DL1, Dl1_MAX_BUFFER_SIZE);
Dl1_Playback_dma_buf = Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_DL1);
return 0;
}
static int mtk_afe_fmtx_probe(struct snd_soc_platform *platform)
{
PRINTK_AUD_FMTX("mtk_afe_afe_probe\n");
snd_soc_add_platform_controls(platform, Audio_snd_fmtx_controls,
ARRAY_SIZE(Audio_snd_fmtx_controls));
AudDrv_Allocate_mem_Buffer(platform->dev, Soc_Aud_Digital_Block_MEM_DL1, Dl1_MAX_BUFFER_SIZE);
FMTX_Playback_dma_buf = Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_DL1);
return 0;
}
static int mtk_pcm_dl1bt_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
int ret = 0;
PRINTK_AUDDRV("mtk_pcm_dl1bt_hw_params\n");
/* runtime->dma_bytes has to be set manually to allow mmap */
substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
/* here to allcoate sram to hardware --------------------------- */
AudDrv_Allocate_mem_Buffer(mDev, Soc_Aud_Digital_Block_MEM_DL1, substream->runtime->dma_bytes);
/* substream->runtime->dma_bytes = AFE_INTERNAL_SRAM_SIZE; */
substream->runtime->dma_area = (unsigned char *)Get_Afe_SramBase_Pointer();
substream->runtime->dma_addr = AFE_INTERNAL_SRAM_PHY_BASE;
PRINTK_AUDDRV(" dma_bytes = %zu dma_area = %p dma_addr = 0x%lx\n",
substream->runtime->dma_bytes, substream->runtime->dma_area, (long)substream->runtime->dma_addr);
return ret;
}
static int mtk_pcm_I2S0dl1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
int ret = 0;
substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
//printk("mtk_pcm_hw_params dma_bytes = %d\n",substream->runtime->dma_bytes);
#if 1
if (mPlaybackSramState == SRAM_STATE_PLAYBACKFULL)
{
//substream->runtime->dma_bytes = AFE_INTERNAL_SRAM_SIZE;
substream->runtime->dma_area = (unsigned char *)Get_Afe_SramBase_Pointer();
substream->runtime->dma_addr = AFE_INTERNAL_SRAM_PHY_BASE;
AudDrv_Allocate_DL1_Buffer(mDev, substream->runtime->dma_bytes);
}
else
{
substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
substream->runtime->dma_area = Dl1_Playback_dma_buf->area;
substream->runtime->dma_addr = Dl1_Playback_dma_buf->addr;
SetDL1Buffer(substream, hw_params);
}
#else //old
// here to allcoate sram to hardware ---------------------------
AudDrv_Allocate_mem_Buffer(Soc_Aud_Digital_Block_MEM_DL1, substream->runtime->dma_bytes);
#ifdef AUDIO_MEMORY_SRAM
//substream->runtime->dma_bytes = AFE_INTERNAL_SRAM_SIZE;
substream->runtime->dma_area = (unsigned char *)Get_Afe_SramBase_Pointer();
substream->runtime->dma_addr = AFE_INTERNAL_SRAM_PHY_BASE;
#else
pI2S0dl1MemControl = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_DL1);
Afe_Block = &pI2S0dl1MemControl->rBlock;;
substream->runtime->dma_area = (unsigned char *)Afe_Block->pucVirtBufAddr;
substream->runtime->dma_addr = Afe_Block->pucPhysBufAddr;
#endif
// -------------------------------------------------------
#endif
printk("1 dma_bytes = %zu dma_area = %p dma_addr = 0x%lx\n",
substream->runtime->dma_bytes, substream->runtime->dma_area, (long)substream->runtime->dma_addr);
return ret;
}
static int mtk_afe_mrgrx_awb_probe(struct snd_soc_platform *platform)
{
printk("mtk_afe_mrgrx_awb_probe\n");
AudDrv_Allocate_mem_Buffer(platform->dev, Soc_Aud_Digital_Block_MEM_AWB, MRGRX_MAX_BUFFER_SIZE);
Awb_Capture_dma_buf = Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_AWB);
if (Mrgrx_Awb_Capture_dma_buf == NULL)
{
Mrgrx_Awb_Capture_dma_buf = kzalloc(sizeof(struct snd_dma_buffer), GFP_KERNEL);
if(Mrgrx_Awb_Capture_dma_buf != NULL)
{
Mrgrx_Awb_Capture_dma_buf->area = dma_alloc_coherent(platform->dev, MRGRX_MAX_BUFFER_SIZE, &Mrgrx_Awb_Capture_dma_buf->addr, GFP_KERNEL);
}
if (Mrgrx_Awb_Capture_dma_buf->area)
{
Mrgrx_Awb_Capture_dma_buf->bytes = MRGRX_MAX_BUFFER_SIZE;
}
}
return 0;
}
static int mtk_btcvsd_rx_probe(struct platform_device *pdev)
{
int ret = 0;
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
if (!pdev->dev.dma_mask)
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
if (pdev->dev.of_node)
dev_set_name(&pdev->dev, "%s", MT_SOC_BTCVSD_RX_PCM);
pr_warn("%s: dev name %s\n", __func__, dev_name(&pdev->dev));
mDev_btcvsd_rx = &pdev->dev;
#ifdef CONFIG_OF
Auddrv_BTCVSD_Irq_Map();
#endif
ret = Register_BTCVSD_Irq(pdev, btcvsd_irq_number);
if (ret < 0)
pr_warn("%s request_irq btcvsd_irq_number(%d) Fail\n", __func__, btcvsd_irq_number);
/* inremap to INFRA sys */
#ifdef CONFIG_OF
Auddrv_BTCVSD_Address_Map();
INFRA_MISC_ADDRESS = (volatile kal_uint32 *)(infra_base + infra_misc_offset);
#else
AUDIO_INFRA_BASE_VIRTUAL = ioremap_nocache(AUDIO_INFRA_BASE_PHYSICAL, 0x1000);
INFRA_MISC_ADDRESS = (volatile kal_uint32 *)(AUDIO_INFRA_BASE_VIRTUAL + INFRA_MISC_OFFSET);
#endif
pr_warn("[BTCVSD probe] INFRA_MISC_ADDRESS = %p\n", INFRA_MISC_ADDRESS);
pr_warn("%s disable BT IRQ disableBTirq = %d,irq=%d\n", __func__, disableBTirq, btcvsd_irq_number);
if (disableBTirq == 0) {
disable_irq(btcvsd_irq_number);
Disable_CVSD_Wakeup();
disableBTirq = 1;
}
if (!isProbeDone) {
memset((void *)&BT_CVSD_Mem, 0, sizeof(CVSD_MEMBLOCK_T));
isProbeDone = 1;
}
memset((void *)&btsco, 0, sizeof(btsco));
btsco.uTXState = BT_SCO_TXSTATE_IDLE;
btsco.uRXState = BT_SCO_RXSTATE_IDLE;
/* ioremap to BT HW register base address */
#ifdef CONFIG_OF
BTSYS_PKV_BASE_ADDRESS = (void *)btsys_pkv_physical_base;
BTSYS_SRAM_BANK2_BASE_ADDRESS = (void *)btsys_sram_bank2_physical_base;
bt_hw_REG_PACKET_R = BTSYS_PKV_BASE_ADDRESS + cvsd_mcu_read_offset;
bt_hw_REG_PACKET_W = BTSYS_PKV_BASE_ADDRESS + cvsd_mcu_write_offset;
bt_hw_REG_CONTROL = BTSYS_PKV_BASE_ADDRESS + cvsd_packet_indicator;
#else
BTSYS_PKV_BASE_ADDRESS = ioremap_nocache(AUDIO_BTSYS_PKV_PHYSICAL_BASE, 0x10000);
BTSYS_SRAM_BANK2_BASE_ADDRESS = ioremap_nocache(AUDIO_BTSYS_SRAM_BANK2_PHYSICAL_BASE, 0x10000);
bt_hw_REG_PACKET_R = (volatile kal_uint32 *)(BTSYS_PKV_BASE_ADDRESS + CVSD_MCU_READ_OFFSET);
bt_hw_REG_PACKET_W = (volatile kal_uint32 *)(BTSYS_PKV_BASE_ADDRESS + CVSD_MCU_WRITE_OFFSET);
bt_hw_REG_CONTROL = (volatile kal_uint32 *)(BTSYS_PKV_BASE_ADDRESS + CVSD_PACKET_INDICATOR);
#endif
pr_debug("[BTCVSD probe] BTSYS_PKV_BASE_ADDRESS = %p BTSYS_SRAM_BANK2_BASE_ADDRESS = %p\n",
BTSYS_PKV_BASE_ADDRESS, BTSYS_SRAM_BANK2_BASE_ADDRESS);
/* allocate dram */
AudDrv_Allocate_mem_Buffer(mDev_btcvsd_rx, Soc_Aud_Digital_Block_MEM_BTCVSD_RX, sizeof(BT_SCO_RX_T));
BT_CVSD_Mem.RX_btcvsd_dma_buf = Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_BTCVSD_RX);
return snd_soc_register_platform(&pdev->dev, &mtk_btcvsd_rx_soc_platform);
}
