/**
* \note This routine refers to derived texture matrix values to
* compute the ENABLE_TEXMAT flags, but is only called on
* _NEW_TEXTURE_OBJECT/STATE. On changes to _NEW_TEXTURE_MATRIX,
* the ENABLE_TEXMAT flags are updated by _mesa_update_texture_matrices,
* above.
*
* \param ctx GL context.
*/
void
_mesa_update_texture_state(struct gl_context *ctx)
{
struct gl_program *prog[MESA_SHADER_STAGES];
int i;
int old_max_unit = ctx->Texture._MaxEnabledTexImageUnit;
BITSET_DECLARE(enabled_texture_units, MAX_COMBINED_TEXTURE_IMAGE_UNITS);
memcpy(prog, ctx->_Shader->CurrentProgram, sizeof(prog));
if (prog[MESA_SHADER_FRAGMENT] == NULL &&
_mesa_arb_fragment_program_enabled(ctx)) {
prog[MESA_SHADER_FRAGMENT] = ctx->FragmentProgram.Current;
}
/* TODO: only set this if there are actual changes */
ctx->NewState |= _NEW_TEXTURE_OBJECT | _NEW_TEXTURE_STATE;
ctx->Texture._GenFlags = 0x0;
ctx->Texture._TexMatEnabled = 0x0;
ctx->Texture._TexGenEnabled = 0x0;
ctx->Texture._MaxEnabledTexImageUnit = -1;
ctx->Texture._EnabledCoordUnits = 0x0;
memset(&enabled_texture_units, 0, sizeof(enabled_texture_units));
/* First, walk over our programs pulling in all the textures for them.
* Programs dictate specific texture targets to be enabled, and for a draw
* call to be valid they can't conflict about which texture targets are
* used.
*/
update_program_texture_state(ctx, prog, enabled_texture_units);
/* Also pull in any textures necessary for fixed function fragment shading.
*/
if (!prog[MESA_SHADER_FRAGMENT])
update_ff_texture_state(ctx, enabled_texture_units);
/* Now, clear out the _Current of any disabled texture units. */
for (i = 0; i <= ctx->Texture._MaxEnabledTexImageUnit; i++) {
if (!BITSET_TEST(enabled_texture_units, i))
_mesa_reference_texobj(&ctx->Texture.Unit[i]._Current, NULL);
}
for (i = ctx->Texture._MaxEnabledTexImageUnit + 1; i <= old_max_unit; i++) {
_mesa_reference_texobj(&ctx->Texture.Unit[i]._Current, NULL);
}
/* add fallback texture for SampleMapATI if there is nothing */
if (_mesa_ati_fragment_shader_enabled(ctx) &&
ctx->ATIFragmentShader.Current->Program)
fix_missing_textures_for_atifs(ctx,
ctx->ATIFragmentShader.Current->Program,
enabled_texture_units);
if (!prog[MESA_SHADER_FRAGMENT] || !prog[MESA_SHADER_VERTEX])
update_texgen(ctx);
}
/**
* \note This routine refers to derived texture matrix values to
* compute the ENABLE_TEXMAT flags, but is only called on
* _NEW_TEXTURE. On changes to _NEW_TEXTURE_MATRIX, the ENABLE_TEXMAT
* flags are updated by _mesa_update_texture_matrices, above.
*
* \param ctx GL context.
*/
static void
update_texture_state( struct gl_context *ctx )
{
struct gl_program *prog[MESA_SHADER_STAGES];
int i;
int old_max_unit = ctx->Texture._MaxEnabledTexImageUnit;
BITSET_DECLARE(enabled_texture_units, MAX_COMBINED_TEXTURE_IMAGE_UNITS);
for (i = 0; i < MESA_SHADER_STAGES; i++) {
if (ctx->_Shader->CurrentProgram[i] &&
ctx->_Shader->CurrentProgram[i]->LinkStatus) {
prog[i] = ctx->_Shader->CurrentProgram[i]->_LinkedShaders[i]->Program;
} else {
if (i == MESA_SHADER_FRAGMENT && ctx->FragmentProgram._Enabled)
prog[i] = &ctx->FragmentProgram.Current->Base;
else
prog[i] = NULL;
}
}
/* TODO: only set this if there are actual changes */
ctx->NewState |= _NEW_TEXTURE;
ctx->Texture._GenFlags = 0x0;
ctx->Texture._TexMatEnabled = 0x0;
ctx->Texture._TexGenEnabled = 0x0;
ctx->Texture._MaxEnabledTexImageUnit = -1;
ctx->Texture._EnabledCoordUnits = 0x0;
memset(&enabled_texture_units, 0, sizeof(enabled_texture_units));
/* First, walk over our programs pulling in all the textures for them.
* Programs dictate specific texture targets to be enabled, and for a draw
* call to be valid they can't conflict about which texture targets are
* used.
*/
update_program_texture_state(ctx, prog, enabled_texture_units);
/* Also pull in any textures necessary for fixed function fragment shading.
*/
if (!prog[MESA_SHADER_FRAGMENT])
update_ff_texture_state(ctx, enabled_texture_units);
/* Now, clear out the _Current of any disabled texture units. */
for (i = 0; i <= ctx->Texture._MaxEnabledTexImageUnit; i++) {
if (!BITSET_TEST(enabled_texture_units, i))
_mesa_reference_texobj(&ctx->Texture.Unit[i]._Current, NULL);
}
for (i = ctx->Texture._MaxEnabledTexImageUnit + 1; i <= old_max_unit; i++) {
_mesa_reference_texobj(&ctx->Texture.Unit[i]._Current, NULL);
}
if (!prog[MESA_SHADER_FRAGMENT] || !prog[MESA_SHADER_VERTEX])
update_texgen(ctx);
}
void
fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
struct fd5_emit *emit)
{
struct stage s[MAX_STAGES];
uint32_t pos_regid, psize_regid, color_regid[8];
uint32_t face_regid, coord_regid, zwcoord_regid;
uint32_t vcoord_regid, vertex_regid, instance_regid;
enum a3xx_threadsize fssz;
uint8_t psize_loc = ~0;
int i, j;
setup_stages(emit, s);
fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
if (s[FS].v->color0_mrt) {
color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
} else {
color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
}
/* TODO get these dynamically: */
face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
vcoord_regid = (s[FS].v->total_in > 0) ? s[FS].v->pos_regid : regid(63,0);
/* we could probably divide this up into things that need to be
* emitted if frag-prog is dirty vs if vert-prog is dirty..
*/
OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5);
OUT_RING(ring, A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED));
OUT_RING(ring, A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED));
OUT_RING(ring, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED));
OUT_RING(ring, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED));
OUT_RING(ring, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED));
OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
OUT_RING(ring, 0x00000000);
OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
OUT_RING(ring, A5XX_HLSQ_VS_CNTL_INSTRLEN(s[VS].instrlen) |
COND(s[VS].v && s[VS].v->has_ssbo, A5XX_HLSQ_VS_CNTL_SSBO_ENABLE));
OUT_RING(ring, A5XX_HLSQ_FS_CNTL_INSTRLEN(s[FS].instrlen) |
COND(s[FS].v && s[FS].v->has_ssbo, A5XX_HLSQ_FS_CNTL_SSBO_ENABLE));
OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen) |
COND(s[HS].v && s[HS].v->has_ssbo, A5XX_HLSQ_HS_CNTL_SSBO_ENABLE));
OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen) |
COND(s[DS].v && s[DS].v->has_ssbo, A5XX_HLSQ_DS_CNTL_SSBO_ENABLE));
OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen) |
COND(s[GS].v && s[GS].v->has_ssbo, A5XX_HLSQ_GS_CNTL_SSBO_ENABLE));
OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5);
OUT_RING(ring, A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
COND(s[VS].v, A5XX_SP_VS_CONFIG_ENABLED));
OUT_RING(ring, A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
COND(s[FS].v, A5XX_SP_FS_CONFIG_ENABLED));
OUT_RING(ring, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
COND(s[HS].v, A5XX_SP_HS_CONFIG_ENABLED));
OUT_RING(ring, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
COND(s[DS].v, A5XX_SP_DS_CONFIG_ENABLED));
OUT_RING(ring, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
COND(s[GS].v, A5XX_SP_GS_CONFIG_ENABLED));
OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
OUT_RING(ring, 0x00000000);
OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */
OUT_RING(ring, s[VS].instrlen); /* HLSQ_VS_INSTRLEN */
OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */
OUT_RING(ring, s[FS].instrlen); /* HLSQ_FS_INSTRLEN */
OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */
OUT_RING(ring, s[HS].instrlen); /* HLSQ_HS_INSTRLEN */
OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */
OUT_RING(ring, s[DS].instrlen); /* HLSQ_DS_INSTRLEN */
OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2);
OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */
OUT_RING(ring, s[GS].instrlen); /* HLSQ_GS_INSTRLEN */
OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
OUT_RING(ring, 0x00000000); /* HLSQ_CS_CONSTLEN */
OUT_RING(ring, 0x00000000); /* HLSQ_CS_INSTRLEN */
OUT_PKT4(ring, REG_A5XX_SP_VS_CTRL_REG0, 1);
OUT_RING(ring, A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
0x6 | /* XXX seems to be always set? */
A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
COND(s[VS].v->has_samp, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
struct ir3_shader_linkage l = {0};
ir3_link_shaders(&l, s[VS].v, s[FS].v);
if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
!emit->key.binning_pass)
link_stream_out(&l, s[VS].v);
BITSET_DECLARE(varbs, 128) = {0};
uint32_t *varmask = (uint32_t *)varbs;
for (i = 0; i < l.cnt; i++)
for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
BITSET_SET(varbs, l.var[i].loc + j);
OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
/* a5xx appends pos/psize to end of the linkage map: */
if (pos_regid != regid(63,0))
ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
if (psize_regid != regid(63,0)) {
psize_loc = l.max_loc;
ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
}
if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
!emit->key.binning_pass) {
emit_stream_out(ring, s[VS].v, &l);
OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
OUT_RING(ring, 0x00000000);
} else {
OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
}
for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
uint32_t reg = 0;
OUT_PKT4(ring, REG_A5XX_SP_VS_OUT_REG(i), 1);
reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
j++;
reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
j++;
OUT_RING(ring, reg);
}
for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
uint32_t reg = 0;
OUT_PKT4(ring, REG_A5XX_SP_VS_VPC_DST_REG(i), 1);
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
OUT_RING(ring, reg);
}
OUT_PKT4(ring, REG_A5XX_SP_VS_OBJ_START_LO, 2);
OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
if (s[VS].instrlen)
fd5_emit_shader(ring, s[VS].v);
// TODO depending on other bits in this reg (if any) set somewhere else?
OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
OUT_RING(ring, COND(s[VS].v->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE));
OUT_PKT4(ring, REG_A5XX_SP_PRIMITIVE_CNTL, 1);
OUT_RING(ring, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1);
OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l.max_loc) |
COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) |
COND(s[FS].v->frag_coord, A5XX_VPC_CNTL_0_VARYING) |
0x10000); // XXX
fd5_context(ctx)->max_loc = l.max_loc;
if (emit->key.binning_pass) {
OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
} else {
OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
}
OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(TWO_QUADS) |
0x00000880); /* XXX HLSQ_CONTROL_0 */
OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
0xfcfcfc00); /* XXX */
OUT_RING(ring, A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
0xfcfcfc00); /* XXX */
OUT_RING(ring, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
0x0000fcfc); /* XXX */
OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
COND(s[FS].v->frag_coord, A5XX_SP_FS_CTRL_REG0_VARYING) |
0x40006 | /* XXX set pretty much everywhere */
A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
COND(s[FS].v->has_samp, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
OUT_RING(ring, 0x020fffff); /* XXX */
OUT_PKT4(ring, REG_A5XX_VPC_GS_SIV_CNTL, 1);
OUT_RING(ring, 0x0000ffff); /* XXX */
OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
OUT_RING(ring, 0x00000010); /* XXX */
OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_GRAS_CNTL_VARYING) |
COND(s[FS].v->frag_coord, A5XX_GRAS_CNTL_XCOORD |
A5XX_GRAS_CNTL_YCOORD |
A5XX_GRAS_CNTL_ZCOORD |
A5XX_GRAS_CNTL_WCOORD |
A5XX_GRAS_CNTL_UNK3) |
COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_UNK3));
OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2);
OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_RB_RENDER_CONTROL0_VARYING) |
COND(s[FS].v->frag_coord, A5XX_RB_RENDER_CONTROL0_XCOORD |
A5XX_RB_RENDER_CONTROL0_YCOORD |
A5XX_RB_RENDER_CONTROL0_ZCOORD |
A5XX_RB_RENDER_CONTROL0_WCOORD |
A5XX_RB_RENDER_CONTROL0_UNK3) |
COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_UNK3));
OUT_RING(ring, COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS));
OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_REG(0), 8);
for (i = 0; i < 8; i++) {
OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
COND(emit->key.half_precision,
A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
}
OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
A5XX_VPC_PACK_PSIZELOC(psize_loc));
if (!emit->key.binning_pass) {
uint32_t vinterp[8], vpsrepl[8];
memset(vinterp, 0, sizeof(vinterp));
memset(vpsrepl, 0, sizeof(vpsrepl));
/* looks like we need to do int varyings in the frag
* shader on a5xx (no flatshad reg? or a420.0 bug?):
*
* (sy)(ss)nop
* (sy)ldlv.u32 r0.x,l[r0.x], 1
* ldlv.u32 r0.y,l[r0.x+1], 1
* (ss)bary.f (ei)r63.x, 0, r0.x
* (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
* (rpt5)nop
* sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
*
* Possibly on later a5xx variants we'll be able to use
* something like the code below instead of workaround
* in the shader:
*/
/* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
/* NOTE: varyings are packed, so if compmask is 0xb
* then first, third, and fourth component occupy
* three consecutive varying slots:
*/
unsigned compmask = s[FS].v->inputs[j].compmask;
uint32_t inloc = s[FS].v->inputs[j].inloc;
if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
(s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
uint32_t loc = inloc;
for (i = 0; i < 4; i++) {
if (compmask & (1 << i)) {
vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
//flatshade[loc / 32] |= 1 << (loc % 32);
loc++;
}
}
}
gl_varying_slot slot = s[FS].v->inputs[j].slot;
/* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
if (slot >= VARYING_SLOT_VAR0) {
unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
/* Replace the .xy coordinates with S/T from the point sprite. Set
* interpolation bits for .zw such that they become .01
*/
if (emit->sprite_coord_enable & texmask) {
/* mask is two 2-bit fields, where:
* '01' -> S
* '10' -> T
* '11' -> 1 - T (flip mode)
*/
unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
uint32_t loc = inloc;
if (compmask & 0x1) {
vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
loc++;
}
if (compmask & 0x2) {
vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
loc++;
}