{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) }
};
#define FIF_NAME "IMSAI"
static const char* fif_description(DEVICE *dptr) {
return FIF_NAME;
}
static REG fif_reg[] = {
{ DRDATAD (DISK, current_disk, 4,
"Current selected disk") },
{ DRDATAD (DSKWL, warnLevelDSK, 32,
"Warn level register") },
{ BRDATAD (WARNATTACHED, warnAttached, 10, 32, NUM_OF_DSK,
"Count for selection of unattached disk register array"), REG_CIRC + REG_RO },
{ DRDATAD (WARNDSK11, warnDSK11, 4,
"Count of IN/OUT(9) on unattached disk register"), REG_RO },
{ NULL }
};
static MTAB fif_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE",
&set_iobase, &show_iobase, NULL, "Sets disk controller I/O base address" },
/* quiet, no warning messages */
{ UNIT_DSK_VERBOSE, 0, "QUIET", "QUIET",
NULL, NULL, NULL, "No verbose messages for unit " FIF_NAME "n" },
/* verbose, show warning messages */
{ UNIT_DSK_VERBOSE, UNIT_DSK_VERBOSE, "VERBOSE", "VERBOSE",
&fif_set_verbose, NULL, NULL, "Verbose messages for unit " FIF_NAME "n" },
{ 0 }
UNIT fl_unit = { UDATA (&fl_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, FL_SIZE) };
REG fl_reg[] = {
{ HRDATAD (FNC, fl_fnc, 8, "function select") },
{ HRDATAD (ES, fl_esr, 8, "error status") },
{ HRDATAD (ECODE, fl_ecode, 8, "error code") },
{ HRDATAD (TA, fl_track, 8, "track address") },
{ HRDATAD (SA, fl_sector, 8, "sector address") },
{ DRDATAD (PSTATE, fl_state, 4, "protocol state"), REG_RO },
{ DRDATAD (BPTR, fl_bptr, 7, "data buffer pointer") },
{ DRDATAD (CTIME, fl_cwait, 24, "command initiation delay"), PV_LEFT },
{ DRDATAD (STIME, fl_swait, 24, "seek time delay, per track"), PV_LEFT },
{ DRDATAD (XTIME, fl_xwait, 24, "transfer time delay, per byte"), PV_LEFT },
{ FLDATAD (STOP_IOE, fl_stopioe, 0, "stop on I/O error") },
{ BRDATAD (DBUF, fl_buf, 16, 8, FL_NUMBY, "data buffer") },
{ BRDATAD (COMM, comm_region, 16, 8, COMM_LNT, "comm region") },
{ NULL }
};
MTAB fl_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL, NULL, NULL, "Write enable floppy drive" },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL, NULL, NULL, "Write lock floppy drive" },
{ 0 }
};
DEVICE fl_dev = {
"CS", &fl_unit, fl_reg, fl_mod,
1, DEV_RDX, 20, 1, DEV_RDX, 8,
NULL, NULL, &fl_reset,
NULL, NULL, NULL,
"Number of sectors per track"), },
{ DRDATAD (SECTSIZE, sectsize, 11,
"Sector size not including pre/postamble"), },
{ HRDATAD (SEL_DRIVE, disk3_info_data.sel_drive, 3,
"Currently selected drive"), },
{ HRDATAD (MODE, disk3_info_data.mode, 8,
"Mode (0xFF=absolute, 0x00=logical)"), },
{ HRDATAD (RETRIES, disk3_info_data.retries, 8,
"Number of retries to attempt"), },
{ HRDATAD (NDRIVES, disk3_info_data.ndrives, 8,
"Number of drives attached to the controller"), },
{ HRDATAD (LINK_ADDR, disk3_info_data.link_addr, 32,
"Link address for next IOPB"), },
{ HRDATAD (DMA_ADDR, disk3_info_data.dma_addr, 32,
"DMA address for the current IOPB"), },
{ BRDATAD (IOPB, &disk3_info_data.iopb[DISK3_IOPB_CMD], 16, 8, 16,
"IOPB command register"), } ,
{ NULL }
};
#define DISK3_NAME "Compupro ST-506 Disk Controller DISK3"
static MTAB disk3_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE",
&set_iobase, &show_iobase, NULL, "Sets disk controller I/O base address" },
/* quiet, no warning messages */
{ UNIT_DISK3_VERBOSE, 0, "QUIET", "QUIET",
NULL, NULL, NULL, "No verbose messages for unit " DISK3_NAME "n" },
/* verbose, show warning messages */
{ UNIT_DISK3_VERBOSE, UNIT_DISK3_VERBOSE, "VERBOSE", "VERBOSE",
NULL, NULL, NULL, "Verbose messages for unit " DISK3_NAME "n" },
{ 0 }
/* TTIx data structures
ttix_dev TTIx device descriptor
ttix_unit TTIx unit descriptor
ttix_reg TTIx register list
ttix_mod TTIx modifiers list
*/
DIB ttix_dib = { DEV_KJ8, 8,
{ &ttix, &ttox, &ttix, &ttox, &ttix, &ttox, &ttix, &ttox } };
UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), SERIAL_IN_WAIT };
REG ttix_reg[] = {
{ BRDATAD (BUF, ttix_buf, 8, 8, TTX_LINES, "input buffer, lines 0 to 3") },
{ GRDATAD (DONE, dev_done, 8, TTX_LINES, INT_V_TTI1, "device done flag (line 0 rightmost)") },
{ GRDATAD (ENABLE, int_enable, 8, TTX_LINES, INT_V_TTI1, "interrupt enable flag") },
{ GRDATAD (INT, int_req, 8, TTX_LINES, INT_V_TTI1, "interrupt pending flag") },
{ DRDATAD (TIME, ttix_unit.wait, 24, "initial polling interval"), REG_NZ + PV_LEFT },
{ DRDATAD (TPS, ttx_tps, 10, "polls per second after calibration"), REG_NZ + PV_LEFT },
{ ORDATA (DEVNUM, ttix_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB ttix_mod[] = {
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
{ HRDATAD (RX_BUF, td_regval,16, "input buffer register") },
{ HRDATAD (TX_CSR, td_regval,16, "output control/status register") },
{ HRDATAD (TX_BUF, td_regval,16, "output buffer register") },
{ DRDATAD (P_STATE,td_regval, 4, "protocol state"), REG_RO },
{ DRDATAD (O_STATE,td_regval, 4, "output state"), REG_RO },
{ DRDATAD (IBPTR, td_regval, 9, "input buffer pointer") },
{ DRDATAD (OBPTR, td_regval, 9, "output buffer pointer") },
{ DRDATAD (ILEN, td_regval, 9, "input length") },
{ DRDATAD (OLEN, td_regval, 9, "output length") },
{ DRDATAD (TXSIZE, td_regval, 9, "remaining transfer size") },
{ DRDATAD (OFFSET, td_regval, 9, "offset into current transfer") },
{ DRDATAD (CTIME, td_regval,24, "command time"), PV_LEFT },
{ DRDATAD (STIME, td_regval,24, "seek, per block"), PV_LEFT },
{ DRDATAD (XTIME, td_regval,24, "tr set time"), PV_LEFT },
{ DRDATAD (ITIME, td_regval,24, "init time"), PV_LEFT },
{ BRDATAD (IBUF, &td_regval,16, 8, 512, "input buffer"), },
{ BRDATAD (OBUF, &td_regval,16, 8, 512, "output buffer"), },
{ NULL }
};
MTAB td_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL, NULL, NULL, "Write enable TU58 drive" },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL, NULL, NULL, "Write lock TU58 drive" },
{ 0 }
};
DEVICE td_dev = {
"TD", &td_unit, td_reg, td_mod,
1, DEV_RDX, 20, 1, DEV_RDX, 8,
NULL, NULL, &td_reset,
NULL, NULL, NULL,
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO|
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) },
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO|
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) },
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO|
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) },
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO|
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) },
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO|
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) },
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO|
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) }
};
REG rs_reg[] = {
{ BRDATAD (CS1, rscs1, DEV_RDX, 16, RS_NUMDR, "control/status 1") },
{ BRDATAD (DA, rsda, DEV_RDX, 16, RS_NUMDR, "track/sector") },
{ BRDATAD (DS, rsds, DEV_RDX, 16, RS_NUMDR, "drive status") },
{ BRDATAD (ER, rser, DEV_RDX, 16, RS_NUMDR, "error status") },
{ BRDATAD (MR, rsmr, DEV_RDX, 16, RS_NUMDR, "maint register") },
{ BRDATAD (WLKS, rswlk, DEV_RDX, 6, RS_NUMDR, "write lock switches") },
{ DRDATAD (TIME, rs_wait, 24, "rotate time"), REG_NZ + PV_LEFT },
{ URDATAD (CAPAC, rs_unit[0].capac, 10, T_ADDR_W, 0,
RS_NUMDR, PV_LEFT | REG_HRO, "Capacity") },
{ FLDATAD (STOP_IOE, rs_stopioe, 0, "stop on I/O error") },
{ NULL }
};
MTAB rs_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "MASSBUS", NULL, NULL, &mba_show_num, NULL, "Display Massbus Address" },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL, NULL, NULL, "Write enable disk drive" },
{ HRDATAD (DR, uba_dr, 32, "diagnostic control register") },
{ FLDATAD (INT, uba_int, 0, "UBA interrupt") },
{ FLDATAD (NEXINT, nexus_req[IPL_UBA], TR_UBA, "") },
{ FLDATAD (AIIP, uba_aiip, 0, "adapter interrupt in progress") },
{ FLDATAD (UIIP, uba_uiip, 0, "Unibus interrupt in progress") },
{ HRDATAD (FMER, uba_fmer, 32, "failing map register") },
{ HRDATAD (FUBAR, uba_fubar, 32, "failing Unibus address") },
{ HRDATAD (BRSVR0, uba_svr[0], 32, "diagnostic register 0") },
{ HRDATAD (BRSVR1, uba_svr[1], 32, "diagnostic register 1") },
{ HRDATAD (BRSVR2, uba_svr[2], 32, "diagnostic register 2") },
{ HRDATAD (BRSVR3, uba_svr[3], 32, "diagnostic register 3") },
{ HRDATAD (BRRVR4, uba_rvr[0], 32, "vector register 0") },
{ HRDATAD (BRRVR5, uba_rvr[1], 32, "vector register 1") },
{ HRDATAD (BRRVR6, uba_rvr[2], 32, "vector register 2") },
{ HRDATAD (BRRVR7, uba_rvr[3], 32, "vector register 3") },
{ BRDATAD (DPR, uba_dpr, 16, 32, 16, "number data paths") },
{ BRDATAD (MAP, uba_map, 16, 32, 496, "Unibus map registers") },
{ DRDATAD (AITIME, uba_aitime, 24, "adapter init time"), PV_LEFT + REG_NZ },
{ DRDATAD (UITIME, uba_uitime, 24, "Unibus init time"), PV_LEFT + REG_NZ },
{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
{ NULL }
};
MTAB uba_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_UBA, "NEXUS", NULL,
NULL, &show_nexus, NULL, "Display nexus" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace, NULL, "Display IO address space assignments" },
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon, NULL, "Enable/Display autoconfiguration" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
UNIT lp62_unit = {
UDATA (&lp62_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 0), SERIAL_OUT_WAIT
};
REG lp62_reg[] = {
{ ORDATAD (BUF, lp62_unit.buf, 8, "last data item processed") },
{ FLDATAD (INT, int_hwre[API_LPT], INT_V_LPT, "interrupt pending flag") },
{ FLDATAD (DONE, int_hwre[API_LPT], INT_V_LPT, "device done flag") },
{ FLDATAD (SPC, int_hwre[API_LPTSPC], INT_V_LPTSPC, "spacing done flag") },
{ DRDATAD (BPTR, lp62_bp, 6, "print buffer pointer") },
{ ORDATA (STATE, lp62_spc, 6), REG_HRO },
{ FLDATA (OVRPR, lp62_ovrpr, 0), REG_HRO },
{ DRDATAD (POS, lp62_unit.pos, T_ADDR_W, "position in the output file"), PV_LEFT },
{ DRDATAD (TIME, lp62_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ FLDATAD (STOP_IOE, lp62_stopioe, 0, "stop on I/O error") },
{ BRDATAD (LBUF, lp62_buf, 8, 8, LP62_BSIZE, "line buffer") },
{ ORDATA (DEVNO, lp62_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB lp62_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },
{ 0 }
};
DEVICE lp62_dev = {
"LPT", &lp62_unit, lp62_reg, lp62_mod,
1, 10, 31, 1, 8, 8,
NULL, NULL, &lp62_reset,
NULL, NULL, NULL,
&lp62_dib, DEV_DISABLE
mctl_reg MCTL register list
mctl_mod MCTL modifier list
*/
#define IOLN_MEM 040
DIB mctl_dib = {
IOBA_AUTO, IOLN_MEM, &mctl_rd, &mctl_wr,
1, 0, 0, { NULL }
};
UNIT mctl_unit = { UDATA (NULL, 0, 0) };
REG mctl_reg[] = {
{ DRDATAD (COUNT, mctl_count, 16, "Memory Module Count") },
{ BRDATAD (CSR, mctl_csr, DEV_RDX, 16, MAX_MCTL_COUNT, "control/status registers") },
{ NULL }
};
DEVICE mctl_dev = {
"MCTL", &mctl_unit, mctl_reg, NULL,
1, DEV_RDX, 20, 1, DEV_RDX, 8,
NULL, NULL, &mctl_reset,
NULL, NULL, NULL,
&mctl_dib, DEV_QBUS, 0, NULL, NULL, NULL, NULL, NULL, NULL,
&mctl_description
};
/* I/O dispatch routines */
t_stat mctl_rd (int32 *data, int32 PA, int32 access)
t_stat wtc_show (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat wtc_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
const char *wtc_description (DEVICE *dptr);
t_stat wtc_reset (DEVICE *dptr);
void wtc_set_valid (void);
void wtc_set_invalid (void);
UNIT wtc_unit = { UDATA (NULL, 0, 0) };
REG wtc_reg[] = {
{ HRDATADF (CSRA, wtc_csra, 8, "CSRA", wtc_csra_bits) },
{ HRDATADF (CSRB, wtc_csrb, 8, "CSRB", wtc_csrb_bits) },
{ HRDATADF (CSRC, wtc_csrc, 8, "CSRC", wtc_csrc_bits) },
{ HRDATADF (CSRD, wtc_csrd, 8, "CSRD", wtc_csrd_bits) },
{ HRDATADF (MODE, wtc_mode, 8, "Watch Mode", wtc_mode_bits) },
{ BRDATAD (RAM, wtc_ram, 8, 8, sizeof (wtc_ram), "RAM") },
{ NULL }
};
MTAB wtc_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "TIME", "TIME={VMS|STD}", &wtc_set, &wtc_show, NULL, "Display watch time mode" },
{ 0 }
};
/* debugging bitmaps */
#define DBG_REG 0x0001 /* trace read/write registers */
DEBTAB wtc_debug[] = {
{"REG", DBG_REG},
{0}
};
mbax_reg MBA register list
*/
DIB mba0_dib = { TR_MBA0, 0, &mba_rdreg, &mba_wrreg, 0, NVCL (MBA0) };
UNIT mba0_unit = { UDATA (NULL, 0, 0) };
REG mba0_reg[] = {
{ HRDATAD (CNFR, mba_cnf[0], 32, "config register") },
{ HRDATAD (CR, mba_cr[0], 4, "control register") },
{ HRDATAD (SR, mba_sr[0], 32, "status register") },
{ HRDATAD (VA, mba_va[0], 17, "virtual address register") },
{ HRDATAD (BC, mba_bc[0], 16, "byte count register") },
{ HRDATAD (DR, mba_dr[0], 32, "diag register") },
{ HRDATAD (SMR, mba_dr[0], 32, "sel map register") },
{ BRDATAD (MAP, mba_map[0], 16, 32, MBA_NMAPR, "map registers") },
{ FLDATAD (NEXINT, nexus_req[IPL_MBA0], TR_MBA0, "nexus interrupt request") },
{ NULL }
};
MTAB mba0_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_MBA0, "NEXUS", NULL,
NULL, &show_nexus, NULL, "Display nexus" },
{ 0 }
};
DIB mba1_dib = { TR_MBA1, 0, &mba_rdreg, &mba_wrreg, 0, NVCL (MBA1) };
UNIT mba1_unit = { UDATA (NULL, 0, 0) };
MTAB mba1_mod[] = {
dci_dev DCI device descriptor
dci_unit DCI unit descriptor
dci_reg DCI register list
*/
#define IOLN_DC 010
DIB dci_dib = {
IOBA_AUTO, IOLN_DC * DCX_LINES, &dcx_rd, &dcx_wr,
2, IVCL (DCI), VEC_AUTO, { &dci_iack, &dco_iack }, IOLN_DC,
};
UNIT dci_unit = { UDATA (&dci_svc, 0, 0), TMLN_SPD_9600_BPS };
REG dci_reg[] = {
{ BRDATAD (BUF, dci_buf, DEV_RDX, 8, DCX_LINES, "input control/stats register") },
{ BRDATAD (CSR, dci_csr, DEV_RDX, 16, DCX_LINES, "input buffer") },
{ GRDATAD (IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0, "interrupt requests") },
{ DRDATAD (TIME, dci_unit.wait, 24, "input polling interval"), PV_LEFT },
{ DRDATA (LINES, dcx_desc.lines, 6), REG_HRO },
{ GRDATA (DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, dci_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB dci_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dcx_desc, "Disconnect a specific line" },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &dcx_desc, "Display a summary of line states" },
