void
bx_cpu_c::XOR_EdGd(BxInstruction_t *i)
{
/* for 32 bit operand size mode */
Bit32u op2_32, op1_32, result_32;
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn);
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 ^ op2_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdGdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 &= op2_32;
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->rm());
op1_32 ^= op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_NEXT_INSTR(i);
}
void
bx_cpu_c::JMP_Ed(BxInstruction_t *i)
{
Bit32u new_EIP;
Bit32u op1_32;
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
invalidate_prefetch_q();
new_EIP = op1_32;
#if BX_CPU_LEVEL >= 2
if (protected_mode()) {
if (new_EIP > bx_cpu. sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
BX_PANIC(("jmp_ev: IP out of CS limits!"));
exception(BX_GP_EXCEPTION, 0, 0);
}
}
#endif
bx_cpu. eip = new_EIP;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_JMP, new_EIP);
}
void BX_CPU_C::BSR_GdEd(bxInstruction_c *i)
{
/* for 32 bit operand size mode */
Bit32u op1_32, op2_32;
/* op2_32 is a register or memory reference */
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
if (op2_32 == 0) {
assert_ZF(); /* op1_32 undefined */
return;
}
op1_32 = 31;
while ( (op2_32 & 0x80000000) == 0 ) {
op1_32--;
op2_32 <<= 1;
}
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_BITSCAN32);
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
}
void
bx_cpu_c::AND_EdId(BxInstruction_t *i)
{
Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id;
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 & op2_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_ERX(bxInstruction_c *i)
{
Bit32u val32 = BX_READ_32BIT_REG(i->rm());
BX_WRITE_32BIT_REGZ(i->rm(), bx_bswap32(val32));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = ~op1_32;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_MdGd(bxInstruction_c *i)
{
Bit32u val32 = BX_READ_32BIT_REG(i->nnn());
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
write_virtual_dword(i->seg(), eaddr, bx_bswap32(val32));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdIdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 &= i->Id();
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_NEXT_INSTR(i);
}
void BX_CPU_C::XCHG_EdGd(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
write_RMW_virtual_dword(op2_32);
}
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
}
void BX_CPU_C::XOR_EdGd(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, result_32;
op2_32 = BX_READ_32BIT_REG(i->nnn());
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
result_32 = op1_32 ^ op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
result_32 = op1_32 ^ op2_32;
write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_RESULT_32(result_32, BX_INSTR_LOGIC32);
}
void BX_CPU_C::XCHG_ERXEAX(bxInstruction_c *i)
{
#if BX_SUPPORT_X86_64
if (i->opcodeReg() == 0) // 'xchg eax, eax' is NOP even in 64-bit mode
return;
#endif
Bit32u temp32 = EAX;
RAX = BX_READ_32BIT_REG(i->opcodeReg());
BX_WRITE_32BIT_REGZ(i->opcodeReg(), temp32);
}
void BX_CPU_C::XOR_GdEd(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, result_32;
unsigned nnn = i->nnn();
op1_32 = BX_READ_32BIT_REG(nnn);
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
result_32 = op1_32 ^ op2_32;
BX_WRITE_32BIT_REGZ(nnn, result_32);
SET_FLAGS_OSZAPC_RESULT_32(result_32, BX_INSTR_LOGIC32);
}
void
bx_cpu_c::TEST_EdGd(BxInstruction_t *i)
{
Bit32u op2_32, op1_32, result_32;
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn);
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 & op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
}
void BX_CPU_C::TEST_EdGd(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
op2_32 = BX_READ_32BIT_REG(i->nnn());
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
#if defined(BX_HostAsm_Test32)
Bit32u flags32;
asmTest32(op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
Bit32u result_32 = op1_32 & op2_32;
SET_FLAGS_OSZAPC_RESULT_32(result_32, BX_INSTR_LOGIC32);
#endif
}
void BX_CPU_C::AND_EdGd(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, result_32;
op2_32 = BX_READ_32BIT_REG(i->nnn());
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
#if defined(BX_HostAsm_And32)
Bit32u flags32;
asmAnd32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
result_32 = op1_32 & op2_32;
#endif
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
#if defined(BX_HostAsm_And32)
Bit32u flags32;
asmAnd32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
result_32 = op1_32 & op2_32;
#endif
write_RMW_virtual_dword(result_32);
}
#if !defined(BX_HostAsm_And32)
SET_FLAGS_OSZAPC_RESULT_32(result_32, BX_INSTR_LOGIC32);
#endif
}
void BX_CPU_C::CMOV_GdEd(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 6) || (BX_CPU_LEVEL_HACKED >= 6)
// Note: CMOV accesses a memory source operand (read), regardless
// of whether condition is true or not. Thus, exceptions may
// occur even if the MOV does not take place.
bx_bool condition = 0;
Bit32u op2_32;
switch (i->b1()) {
// CMOV opcodes:
case 0x140: condition = get_OF(); break;
case 0x141: condition = !get_OF(); break;
case 0x142: condition = get_CF(); break;
case 0x143: condition = !get_CF(); break;
case 0x144: condition = get_ZF(); break;
case 0x145: condition = !get_ZF(); break;
case 0x146: condition = get_CF() || get_ZF(); break;
case 0x147: condition = !get_CF() && !get_ZF(); break;
case 0x148: condition = get_SF(); break;
case 0x149: condition = !get_SF(); break;
case 0x14A: condition = get_PF(); break;
case 0x14B: condition = !get_PF(); break;
case 0x14C: condition = getB_SF() != getB_OF(); break;
case 0x14D: condition = getB_SF() == getB_OF(); break;
case 0x14E: condition = get_ZF() || (getB_SF() != getB_OF()); break;
case 0x14F: condition = !get_ZF() && (getB_SF() == getB_OF()); break;
default:
BX_PANIC(("CMOV_GdEd: default case"));
}
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
if (condition) {
BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
}
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOV_GdEd: -enable-cpu-level=6 required"));
UndefinedOpcode(i);
#endif
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdGdM(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 ^= op2_32;
write_RMW_virtual_dword(op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_NEXT_INSTR(i);
}
void BX_CPU_C::NOT_Ed(bxInstruction_c *i)
{
Bit32u op1_32, result_32;
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
result_32 = ~op1_32;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
result_32 = ~op1_32;
write_RMW_virtual_dword(result_32);
}
}
void
bx_cpu_c::CALL_Ed(BxInstruction_t *i)
{
Bit32u temp_ESP;
Bit32u op1_32;
#if BX_DEBUGGER
bx_cpu. show_flag |= Flag_call;
#endif
if (bx_cpu. sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
temp_ESP = ESP;
else
temp_ESP = SP;
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
read_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
invalidate_prefetch_q();
if (protected_mode()) {
if (op1_32 > bx_cpu. sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
BX_DEBUG(("call_ev: EIP out of CS limits! at %s:%d"));
exception(BX_GP_EXCEPTION, 0, 0);
}
if ( !can_push(&bx_cpu. sregs[BX_SEG_REG_SS].cache, temp_ESP, 4) ) {
BX_PANIC(("call_ev: can't push EIP"));
}
}
push_32(bx_cpu. eip);
bx_cpu. eip = op1_32;
BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_CALL, bx_cpu. eip);
}
void BX_CPU_C::BSWAP_ERX(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit32u val32, b0, b1, b2, b3;
if (i->os32L() == 0) {
BX_ERROR(("BSWAP with 16-bit opsize: undefined behavior !"));
}
val32 = BX_READ_32BIT_REG(i->opcodeReg());
b0 = val32 & 0xff; val32 >>= 8;
b1 = val32 & 0xff; val32 >>= 8;
b2 = val32 & 0xff; val32 >>= 8;
b3 = val32;
val32 = (b0<<24) | (b1<<16) | (b2<<8) | b3; // zero extended
// in 64-bit mode, hi-order 32 bits are not modified
BX_WRITE_32BIT_REGZ(i->opcodeReg(), val32);
#else
BX_INFO(("BSWAP_ERX: required CPU >= 4, use --enable-cpu-level=4 option"));
UndefinedOpcode(i);
#endif
}
void
bx_cpu_c::BSF_GvEv(BxInstruction_t *i)
{
#if BX_CPU_LEVEL < 3
BX_PANIC(("BSF_GvEv(): not supported on < 386"));
#else
if (i->os_32) { /* 32 bit operand size mode */
/* for 32 bit operand size mode */
Bit32u op1_32, op2_32;
/* op2_32 is a register or memory reference */
if (i->mod == 0xc0) {
op2_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg, i->rm_addr, &op2_32);
}
if (op2_32 == 0) {
set_ZF(1);
/* op1_32 undefined */
return;
}
op1_32 = 0;
while ( (op2_32 & 0x01) == 0 ) {
op1_32++;
op2_32 >>= 1;
}
set_ZF(0);
/* now write result back to destination */
BX_WRITE_32BIT_REG(i->nnn, op1_32);
}
void
bx_cpu_c::NOT_Ed(BxInstruction_t *i)
{
Bit32u op1_32, result_32;
/* op1 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = ~op1_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
write_RMW_virtual_dword(result_32);
}
}
void BX_CPU_C::MOV_EGdGd(bxInstruction_c *i)
{
Bit32u op2_32 = BX_READ_32BIT_REG(i->nnn());
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_ERX(bxInstruction_c *i)
{
push_32(BX_READ_32BIT_REG(i->opcodeReg()));
}
BX_CPU_C::BxResolve32BaseIndex(bxInstruction_c *i)
{
return (Bit32u) (BX_READ_32BIT_REG(i->sibBase()) + (BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale()) + i->displ32s());
}
void BX_CPU_C::MOV_GdEEd(bxInstruction_c *i)
{
// 2nd modRM operand Ex, is known to be a memory operand, Ed.
read_virtual_dword(i->seg(), RMAddr(i), &BX_READ_32BIT_REG(i->nnn()));
BX_CLEAR_64BIT_HIGH(i->nnn());
}
void BX_CPU_C::MOV_GdEGd(bxInstruction_c *i)
{
// 2nd modRM operand Ex, is known to be a general register Gd.
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
}
void BX_CPU_C::MOV_EEdGd(bxInstruction_c *i)
{
write_virtual_dword(i->seg(), RMAddr(i), &BX_READ_32BIT_REG(i->nnn()));
}
