void BX_CPU_C::BSR_GdEd(bxInstruction_c *i)
{
/* for 32 bit operand size mode */
Bit32u op1_32, op2_32;
/* op2_32 is a register or memory reference */
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
if (op2_32 == 0) {
assert_ZF(); /* op1_32 undefined */
return;
}
op1_32 = 31;
while ( (op2_32 & 0x80000000) == 0 ) {
op1_32--;
op2_32 <<= 1;
}
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_BITSCAN32);
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_ERX(bxInstruction_c *i)
{
Bit32u val32 = BX_READ_32BIT_REG(i->rm());
BX_WRITE_32BIT_REGZ(i->rm(), bx_bswap32(val32));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 = ~op1_32;
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVBE_GdMd(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u val32 = read_virtual_dword(i->seg(), eaddr);
BX_WRITE_32BIT_REGZ(i->nnn(), bx_bswap32(val32));
BX_NEXT_INSTR(i);
}
void BX_CPU_C::LEA_GdM(bxInstruction_c *i)
{
if (i->modC0()) {
BX_INFO(("LEA_GdM: op2 is a register"));
UndefinedOpcode(i);
}
/* write effective address of op2 in op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), RMAddr(i));
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdIdR(bxInstruction_c *i)
{
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
op1_32 ^= i->Id();
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_NEXT_INSTR(i);
}
void BX_CPU_C::XCHG_EdGd(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
write_RMW_virtual_dword(op2_32);
}
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
}
void BX_CPU_C::XCHG_ERXEAX(bxInstruction_c *i)
{
#if BX_SUPPORT_X86_64
if (i->opcodeReg() == 0) // 'xchg eax, eax' is NOP even in 64-bit mode
return;
#endif
Bit32u temp32 = EAX;
RAX = BX_READ_32BIT_REG(i->opcodeReg());
BX_WRITE_32BIT_REGZ(i->opcodeReg(), temp32);
}
void BX_CPU_C::MOV_EdId(bxInstruction_c *i)
{
Bit32u op2_32 = i->Id();
/* now write sum back to destination */
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}
else {
write_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
}
/* VEX.66.0F 50 (VEX.W ignore, VEX.VVV #UD) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMOVMSKB_GdUdq(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->rm());
unsigned len = i->getVL();
Bit32u mask = 0;
for (unsigned n=0; n < len; n++)
mask |= sse_pmovmskb(&op.avx128(n)) << (16*n);
BX_WRITE_32BIT_REGZ(i->nnn(), mask);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LSS_GdMp(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit16u ss = read_virtual_word(i->seg(), (eaddr + 4) & i->asize_mask());
Bit32u reg_32 = read_virtual_dword(i->seg(), eaddr);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GdEdR(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->rm());
op1_32 &= op2_32;
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_NEXT_INSTR(i);
}
void BX_CPU_C::CMOV_GdEd(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 6) || (BX_CPU_LEVEL_HACKED >= 6)
// Note: CMOV accesses a memory source operand (read), regardless
// of whether condition is true or not. Thus, exceptions may
// occur even if the MOV does not take place.
bx_bool condition = 0;
Bit32u op2_32;
switch (i->b1()) {
// CMOV opcodes:
case 0x140: condition = get_OF(); break;
case 0x141: condition = !get_OF(); break;
case 0x142: condition = get_CF(); break;
case 0x143: condition = !get_CF(); break;
case 0x144: condition = get_ZF(); break;
case 0x145: condition = !get_ZF(); break;
case 0x146: condition = get_CF() || get_ZF(); break;
case 0x147: condition = !get_CF() && !get_ZF(); break;
case 0x148: condition = get_SF(); break;
case 0x149: condition = !get_SF(); break;
case 0x14A: condition = get_PF(); break;
case 0x14B: condition = !get_PF(); break;
case 0x14C: condition = getB_SF() != getB_OF(); break;
case 0x14D: condition = getB_SF() == getB_OF(); break;
case 0x14E: condition = get_ZF() || (getB_SF() != getB_OF()); break;
case 0x14F: condition = !get_ZF() && (getB_SF() == getB_OF()); break;
default:
BX_PANIC(("CMOV_GdEd: default case"));
}
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
if (condition) {
BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
}
BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
#else
BX_INFO(("CMOV_GdEd: -enable-cpu-level=6 required"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::NOT_Ed(bxInstruction_c *i)
{
Bit32u op1_32, result_32;
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
result_32 = ~op1_32;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
result_32 = ~op1_32;
write_RMW_virtual_dword(result_32);
}
}
void BX_CPU_C::MOVSX_GdEw(bxInstruction_c *i)
{
Bit16u op2_16;
if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
/* sign extend word op2 into dword op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), (Bit16s) op2_16);
}
void BX_CPU_C::MOVSX_GdEb(bxInstruction_c *i)
{
Bit8u op2_8;
if (i->modC0()) {
op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op2_8);
}
/* sign extend byte op2 into dword op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), (Bit8s) op2_8);
}
// LES/LDS can't be called from long64 mode
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LDS_GdMp(bxInstruction_c *i)
{
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit16u ds = read_virtual_word_32(i->seg(), (eaddr + 4) & i->asize_mask());
Bit32u reg_32 = read_virtual_dword_32(i->seg(), eaddr);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
BX_NEXT_INSTR(i);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_EwSwR(bxInstruction_c *i)
{
/* Illegal to use nonexisting segments */
if (i->nnn() >= 6) {
BX_INFO(("MOV_EwSw: using of nonexisting segment register %d", i->nnn()));
UndefinedOpcode(i);
}
Bit16u seg_reg = BX_CPU_THIS_PTR sregs[i->nnn()].selector.value;
if (i->os32L()) {
BX_WRITE_32BIT_REGZ(i->rm(), seg_reg);
}
else {
BX_WRITE_16BIT_REG(i->rm(), seg_reg);
}
}
void BX_CPU_C::LDS_GdMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LDS_GdMp: invalid use of LDS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit16u ds;
Bit32u reg_32;
read_virtual_dword(i->seg(), RMAddr(i), ®_32);
read_virtual_word(i->seg(), RMAddr(i) + 4, &ds);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
}
void BX_CPU_C::XOR_EdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id();
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
result_32 = op1_32 ^ op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
result_32 = op1_32 ^ op2_32;
write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_RESULT_32(result_32, BX_INSTR_LOGIC32);
}
void BX_CPU_C::XOR_GdEd(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, result_32;
unsigned nnn = i->nnn();
op1_32 = BX_READ_32BIT_REG(nnn);
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
result_32 = op1_32 ^ op2_32;
BX_WRITE_32BIT_REGZ(nnn, result_32);
SET_FLAGS_OSZAPC_RESULT_32(result_32, BX_INSTR_LOGIC32);
}
void BX_CPU_C::BSWAP_ERX(bxInstruction_c *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit32u val32, b0, b1, b2, b3;
if (i->os32L() == 0) {
BX_ERROR(("BSWAP with 16-bit opsize: undefined behavior !"));
}
val32 = BX_READ_32BIT_REG(i->opcodeReg());
b0 = val32 & 0xff; val32 >>= 8;
b1 = val32 & 0xff; val32 >>= 8;
b2 = val32 & 0xff; val32 >>= 8;
b3 = val32;
val32 = (b0<<24) | (b1<<16) | (b2<<8) | b3; // zero extended
// in 64-bit mode, hi-order 32 bits are not modified
BX_WRITE_32BIT_REGZ(i->opcodeReg(), val32);
#else
BX_INFO(("BSWAP_ERX: required CPU >= 4, use --enable-cpu-level=4 option"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::AND_EdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id();
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
#if defined(BX_HostAsm_And32)
Bit32u flags32;
asmAnd32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
result_32 = op1_32 & op2_32;
#endif
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
#if defined(BX_HostAsm_And32)
Bit32u flags32;
asmAnd32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
result_32 = op1_32 & op2_32;
#endif
write_RMW_virtual_dword(result_32);
}
#if !defined(BX_HostAsm_And32)
SET_FLAGS_OSZAPC_RESULT_32(result_32, BX_INSTR_LOGIC32);
#endif
}
void BX_CPU_C::OR_GdEd(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, result_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
#if defined(BX_HostAsm_Or32)
Bit32u flags32;
asmOr32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
result_32 = op1_32 | op2_32;
SET_FLAGS_OSZAPC_RESULT_32(result_32, BX_INSTR_LOGIC32);
#endif
BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
}
void BX_CPU_C::MOV_ERXId(bxInstruction_c *i)
{
BX_WRITE_32BIT_REGZ(i->opcodeReg(), i->Id());
}
void BX_CPU_C::MOV_EGdGd(bxInstruction_c *i)
{
Bit32u op2_32 = BX_READ_32BIT_REG(i->nnn());
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}
void BX_CPU_C::MOV_GdEGd(bxInstruction_c *i)
{
// 2nd modRM operand Ex, is known to be a general register Gd.
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_ERX(bxInstruction_c *i)
{
BX_WRITE_32BIT_REGZ(i->opcodeReg(), pop_32());
}
