//Interrupts
CVErrorCodes V551_Sequencer::WriteInterruptVectorRegister (unsigned int statusId)
{
if (statusId > 255)
statusId = 255; //maximum value of statusId is 255
return CAENVME_WriteCycle (controllerHandle, baseAddress, &statusId, cvA32_U_DATA, cvD16);
}
//Clear Module -- Clears (just) on access @ BA + 0x4
CVErrorCodes V551_Sequencer::ClearModule ()
{
uint16_t pattern = 0; //16bit -> 16 zeros, needed just for access @ BA+0x4
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0x4, &pattern, cvA32_U_DATA, cvD16);
}
// Write Internal DAC -> Full value 0xFFF = (dec) 4095 = +5V 50mA (max)
CVErrorCodes V551_Sequencer::WriteInternalDAC (unsigned int DACValue)
{
if (DACValue > 4095)
DACValue = 4095;
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0x18, &DACValue, cvA32_U_DATA, cvD16);
}
// Write T1 Register @ BA + 0x0E (T1 = Trigger to Hold Delay)
// t1 = 500 + T1*10 ns , 0<=T1<=255
CVErrorCodes V551_Sequencer::WriteT1Register (unsigned int T1)
{
if (T1 > 255)
T1 = 255; //no need for <0 as T1 is UNsigned int
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0xE, &T1, cvA32_U_DATA, cvD16);
}
CVErrorCodes write_to_v812(uint32_t vme_addr, uint32_t data)
{
CVDataWidth data_size = cvD16;
CVAddressModifier addr_mode = cvA32_U_DATA;
vme_addr = vme_addr + V812_BASE_ADDRESS;
return CAENVME_WriteCycle(handle, vme_addr, &data, addr_mode, data_size);
}
// Write Number of channels @ BA + 0xC
CVErrorCodes V551_Sequencer::WriteNumberOfChannels (unsigned int numberOfChannels)
{
if (numberOfChannels > 2047)
numberOfChannels = 2047; // max number of channels is 2047
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0xC, &numberOfChannels, cvA32_U_DATA, cvD16);
}
// Interrupt Level @ BA + 0x2
CVErrorCodes V551_Sequencer::WriteInterruptLevelRegister (unsigned int interruptLevel)
{
if (interruptLevel > 7)
interruptLevel = 7; // 7 is the max level of IACK cycle
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0x2, &interruptLevel, cvA32_U_DATA, cvD16);
}
int CAEN_V814::SetOutputWidth()
{
int status=0;
WORD data=configuration_.outputWidth;
status |= CAENVME_WriteCycle(handle_, configuration_.baseAddress + CAEN_V814_OUT_WIDTH_0_7_ADD , &data, CAEN_V814_ADDRESSMODE,CAEN_V814_DATAWIDTH);
status |= CAENVME_WriteCycle(handle_, configuration_.baseAddress + CAEN_V814_OUT_WIDTH_8_15_ADD , &data, CAEN_V814_ADDRESSMODE,CAEN_V814_DATAWIDTH);
if (status)
{
ostringstream s; s << "[CAEN_V814]::[ERROR]::Cannot set output width for V814 @0x" << std::hex << configuration_.baseAddress << std::dec;
Log(s.str(),1);
return ERR_CONFIG;
}
return 0;
}
// Write T4 Register @ BA + 0x14 (T4 = Period of CLOCK and CONVERT sequence)
// t4 = 20 + T4*20 ns , 1<=T4<=511
CVErrorCodes V551_Sequencer::WriteT4Register (unsigned int T4)
{
if (T4 < 1)
T4 = 1;
if (T4 > 511)
T4 = 511;
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0x14, &T4, cvA32_U_DATA, cvD16);
}
// Write T3 Register @ BA + 0x12 (T3 = Active Clock Duration)
// t3 = T3*20 ns , 1<=T3<=T4 , T3<=255
CVErrorCodes V551_Sequencer::WriteT3Register (unsigned int T3)
{
if (T3 > 255)
T3 = 255;
if (T3 < 1)
T3 = 1;
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0x12, &T3, cvA32_U_DATA, cvD16);
}
// Write T2 Register @ BA + 0x10 (T2 = Hold to Sequence Delay)
// t2 = 130 + T2*20 (+/-) 10 ns , 10<=T2<=511
CVErrorCodes V551_Sequencer::WriteT2Register (unsigned int T2)
{
if (T2 > 511)
T2 = 511;
if (T2 < 10)
T2 = 10;
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0x10, &T2, cvA32_U_DATA, cvD16);
}
// Write T5 Register @ BA + 0x16 (T5 = Clock to Convert Delay)
// t5 = 40 + T5*20 ns , 2<=T5<=511
CVErrorCodes V551_Sequencer::WriteT5Register (unsigned int T5)
{
if (T5 < 2)
T5 = 2;
if (T5 > 511)
T5 = 511;
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0x16, &T5, cvA32_U_DATA, cvD16);
}
void bs_reset(void) {
int data;
//data = 0;
//CAENVME_WriteCycle(BHandle, BASEADDR + 0xF8, &data, cvA32_U_DATA, cvD16);
data = 1;
CAENVME_WriteCycle(BHandle, BASEADDR + 0xF8, &data, cvA32_U_DATA, cvD16);
//data = 0;
//CAENVME_WriteCycle(BHandle, BASEADDR + 0xF8, &data, cvA32_U_DATA, cvD16);
}
// VME Write 16 bits data for debugging. Use VME_WRITE_16 macro for tested code
int _Write16( unsigned long ad, short dt, int err ){
unsigned long a = ad;
short d = dt;
vmeStatus = CAENVME_WriteCycle( V2718_Handle, a, &d, cvA32_U_DATA, cvD16 );
if( vmeStatus != cvSuccess )
{
DO_ERROR{
sprintf( message, "Writing error %d. (%d)", err, vmeStatus );
ERROR( message );
}
}
void CaenVmeWrite(int32_t BHandle, man_par_t *man)
{
uint32_t i ;
CVErrorCodes ret,old_ret=cvSuccess;
if(man->dtsize == cvD64)
{
con_printf(" Can't execute a D64 Write Cycle");
return ;
}
con_printf_xy(X_COMM,Y_COMM+1," Write Data [hex] : ") ;
con_scanf("%x",&man->data) ;
if(man->ncyc == 0) // Infinite Loop
con_printf_xy(X_COMM,Y_COMM+2," Running ... Press any key to stop.");
for (i=0; ((man->ncyc==0) || (i<man->ncyc)) && !con_kbhit(); i++)
{
ret = CAENVME_WriteCycle(BHandle,man->addr,&man->data,man->am,man->dtsize);
if((i==0) || (ret != old_ret))
{
gotoxy(X_COMM,Y_COMM) ;
switch (ret)
{
case cvSuccess : con_printf(" Cycle(s) completed normally\n");
break ;
case cvBusError : con_printf(" Bus Error !!!");
break ;
case cvCommError : con_printf(" Communication Error !!!");
break ;
default : con_printf(" Unknown Error !!!");
break ;
}
}
old_ret = ret;
if(man->autoinc)
{
man->addr += man->dtsize; // Increment address (+1 or +2 or +4)
con_printf_xy(X_ADDR,Y_ADDR,"%08X]",man->addr); // Update the screen
}
}
if(man->ncyc == 0)
clear_line(Y_COMM+2);
}
int CAEN_V814::SetThreshold(int channel)
{
int status=0;
#ifdef CAEN_V814_VERBOSE
ostringstream s;
#endif
if (channel<0)
{
WORD data=configuration_.commonThreshold;
for (unsigned int i=0;i<CAEN_V814_CHANNELS;++i)
{
status |= CAENVME_WriteCycle(handle_, configuration_.baseAddress + CAEN_V814_THRESHOLD_ADD + i*0x2 , &data, CAEN_V814_ADDRESSMODE,CAEN_V814_DATAWIDTH);
#ifdef CAEN_V814_VERBOSE
s.str(""); s << "[CAEN_V814]::[INFO]::Set common threshold for channel " << i << " to " << configuration_.commonThreshold;
Log(s.str(),1);
#endif
}
}
else
{
WORD data=configuration_.chThreshold[channel];
status |= CAENVME_WriteCycle(handle_, configuration_.baseAddress + CAEN_V814_THRESHOLD_ADD + channel*0x2 , &data, CAEN_V814_ADDRESSMODE,CAEN_V814_DATAWIDTH);
#ifdef CAEN_V814_VERBOSE
s.str(""); s << "[CAEN_V814]::[INFO]::Set threshold for channel " << channel << " to " << configuration_.chThreshold[channel];
Log(s.str(),1);
#endif
}
if (status)
{
ostringstream s; s << "[CAEN_V814]::[ERROR]::Cannot set threshold for V814 @0x" << std::hex << configuration_.baseAddress << std::dec;
Log(s.str(),1);
return ERR_CONFIG;
}
return 0;
}
int CAEN_V814::SetPatternInhibit()
{
int status=0;
WORD data=configuration_.patternMask;
status |= CAENVME_WriteCycle(handle_, configuration_.baseAddress + CAEN_V814_PATTERN_INHIBIT_ADD , &data, CAEN_V814_ADDRESSMODE,CAEN_V814_DATAWIDTH);
if (status)
{
ostringstream s; s << "[CAEN_V814]::[ERROR]::Cannot set pattern mask for V814 @0x" << std::hex << configuration_.baseAddress << std::dec;
Log(s.str(),1);
return ERR_CONFIG;
}
return 0;
}
int CAEN_V814::SetMajorityThreshold()
{
int status=0;
WORD data=configuration_.majorityThreshold;
status |= CAENVME_WriteCycle(handle_, configuration_.baseAddress + CAEN_V814_MAJORITY_ADD , &data, CAEN_V814_ADDRESSMODE,CAEN_V814_DATAWIDTH);
if (status)
{
ostringstream s; s << "[CAEN_V814]::[ERROR]::Cannot set majority threshold for V814 @0x" << std::hex << configuration_.baseAddress << std::dec;
Log(s.str(),1);
return ERR_CONFIG;
}
return 0;
}
CAENVME_API parse_and_call_CAENVME_WriteCycle( char* arguments ){
// parse string, call CAENVMElib function
CAENVME_API caen_api_return_value;
uint32_t address;
uint16_t value;
// parse register address and input value
char * pch;
pch = strtok(arguments, " "); // blank space is the only delimeter in out case
sscanf (pch, "%x", &address);
sscanf (strtok(NULL, " "), "%x", &value);
printf("Writing %x to address %x on VME\n(bridge handle ID = %d)\n", value, address, bridge_handler);
caen_api_return_value = CAENVME_WriteCycle( bridge_handler, address, &value, cvA32_U_DATA, cvD16);
printf("Done\n");
return caen_api_return_value;
}
// Ch0 - Upper Display @ BA + 0x2
CVErrorCodes V462_GateGenerator::SetChannel0UpperDisplay (unsigned int upperDisplayCh0)
{
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0x2, &upperDisplayCh0, cvA24_U_DATA, cvD16);
}
// Generate Test Pulse
CVErrorCodes V462_GateGenerator::GenerateTestPulse ()
{
uint16_t test = 1536;
return CAENVME_WriteCycle (controllerHandle, baseAddress, &test, cvA24_U_DATA, cvD16);
}
// Write Test Register @ BA+0xA
CVErrorCodes V551_Sequencer::WriteTestRegister (bool testMode, bool clockLevel, bool shiftInLevel, bool testPulseLevel)
{
uint16_t pattern = (testPulseLevel << 3) | (shiftInLevel << 2) | (clockLevel << 1) | testMode;
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0xA, &pattern, cvA32_U_DATA, cvD16);
}
void bs_enable(void) {
int data = 1;
CAENVME_WriteCycle(BHandle, BASEADDR + 0xE8, &data, cvA32_U_DATA, cvD16);
}
// Write Status Register @ BA + 0x8
CVErrorCodes V551_Sequencer::WriteStatusRegister (bool internalDelay, bool veto, bool autoTrigger)
{
uint16_t pattern = (autoTrigger << 2) | (veto << 1) | (internalDelay);
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0x8, &pattern, cvA32_U_DATA, cvD16);
}
//Software Trigger -- Access starts conversion cycle @ BA + 0x6
CVErrorCodes V551_Sequencer::SoftwareTrigger ()
{
uint16_t pattern = 0;
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0x6, &pattern, cvA32_U_DATA, cvD16);
}
// Ch1 - Lower Display @ BA + 0x8
CVErrorCodes V462_GateGenerator::SetChannel1LowerDisplay (unsigned int lowerDisplayCh1)
{
return CAENVME_WriteCycle (controllerHandle, baseAddress + 0x8, &lowerDisplayCh1, cvA24_U_DATA, cvD16);
}
