static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
{
struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
u32 value;
if (!mtk->has_ippc)
return 0;
/* reset whole ip */
value = readl(&ippc->ip_pw_ctr0);
value |= CTRL0_IP_SW_RST;
writel(value, &ippc->ip_pw_ctr0);
udelay(1);
value = readl(&ippc->ip_pw_ctr0);
value &= ~CTRL0_IP_SW_RST;
writel(value, &ippc->ip_pw_ctr0);
/*
* device ip is default power-on in fact
* power down device ip, otherwise ip-sleep will fail
*/
value = readl(&ippc->ip_pw_ctr2);
value |= CTRL2_IP_DEV_PDN;
writel(value, &ippc->ip_pw_ctr2);
value = readl(&ippc->ip_xhci_cap);
mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
mtk->num_u2_ports, mtk->num_u3_ports);
return xhci_mtk_host_enable(mtk);
}
static int u3phy_ports_enable(void)
{
int i;
u32 value;
int u3_port_num;
int u2_port_num;
value = read32(&ippc_regs->ip_xhci_cap);
u3_port_num = CAP_U3_PORT_NUM(value);
u2_port_num = CAP_U2_PORT_NUM(value);
u3p_msg("%s u2p:%d, u3p:%d\n", __func__, u2_port_num, u3_port_num);
/* power on host ip */
clrbits_le32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN);
/* power on and enable all u3 ports */
for (i = 0; i < u3_port_num; i++) {
clrsetbits_le32(&ippc_regs->u3_ctrl_p[i],
CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS, CTRL_U3_PORT_HOST_SEL);
}
/* power on and enable all u2 ports */
for (i = 0; i < u2_port_num; i++) {
clrsetbits_le32(&ippc_regs->u2_ctrl_p[i],
CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS, CTRL_U2_PORT_HOST_SEL);
}
return check_ip_clk_status();
}
