Fd_t uart_Open(char *ifName, unsigned long flags)
{
UARTM_Start();
/* 1 ms delay */
CyDelay(1u);
/* Enable WLAN interrupt */
CC3100_InterruptEnable();
/* Clear Tx Rx Buffers */
UARTM_ClearTxBuffer();
UARTM_ClearRxBuffer();
return NONOS_RET_OK;
}
Fd_t spi_Open(char *ifName, unsigned long flags)
{
/* Select the SPI lines: MOSI/MISO on P3.0,1 CLK on P3.2 */
P3SEL |= (BIT0 + BIT1);
P3REN |= BIT1;
P3OUT |= BIT1;
P3SEL |= BIT2;
UCB0CTL1 |= UCSWRST; /* Put state machine in reset */
UCB0CTL0 = UCMSB + UCMST + UCSYNC + UCCKPH; /* 3-pin, 8-bit SPI master */
UCB0CTL1 = UCSWRST + UCSSEL_2; /* Use SMCLK, keep RESET */
/* Set SPI clock */
UCB0BR0 = 0x02; /* f_UCxCLK = 25MHz/2 */
UCB0BR1 = 0;
UCB0CTL1 &= ~UCSWRST;
/* P1.6 - WLAN enable full DS */
P1SEL &= ~BIT6;
P1OUT &= ~BIT6;
P1DIR |= BIT6;
/* Configure SPI IRQ line on P2.0 */
P2DIR &= ~BIT0;
P2SEL &= ~BIT0;
P2REN |= BIT0;
/* Configure the SPI CS to be on P2.2 */
P2OUT |= BIT2;
P2SEL &= ~BIT2;
P2DIR |= BIT2;
/* 50 ms delay */
Delay(50);
/* Enable WLAN interrupt */
CC3100_InterruptEnable();
return NONOS_RET_OK;
}
Fd_t uart_Open(char *ifName, unsigned long flags)
{
unsigned char i;
IntIsMasked = FALSE;
puartFlowctrl->JitterBufferFreeBytes = UART_READ_JITTER_BUFFER_SIZE;
puartFlowctrl->JitterBufferWriteIdx = 0;
puartFlowctrl->pActiveBuffer = puartFlowctrl->JitterBuffer;
puartFlowctrl->bActiveBufferIsJitterOne = TRUE;
puartFlowctrl->JitterBufferReadIdx = 0xFF;
for(i = 0; i < UART_READ_JITTER_BUFFER_SIZE; i++)
{
puartFlowctrl->JitterBuffer[i] = 0xCC;
}
/* P1.6 - WLAN enable full DS */
P1SEL &= ~BIT6;
P1OUT &= ~BIT6;
P1DIR |= BIT6;
/* Configure Host IRQ line on P2.0 */
P2DIR &= ~BIT0;
P2SEL &= ~BIT0;
P2REN |= BIT0;
/* Configure Pin 3.3/3.4 for RX/TX */
P3SEL |= BIT3 + BIT4; /* P4.4,5 = USCI_A0 TXD/RXD */
UCA0CTL1 |= UCSWRST; /* Put state machine in reset */
UCA0CTL0 = 0x00;
UCA0CTL1 = UCSSEL__SMCLK + UCSWRST; /* Use SMCLK, keep RESET */
UCA0BR0 = 0xD9; /* 25MHz/115200= 217.01 =0xD9 (see User's Guide) */
UCA0BR1 = 0x00; /* 25MHz/9600= 2604 =0xA2C (see User's Guide) */
UCA0MCTL = UCBRS_3 + UCBRF_0; /* Modulation UCBRSx=3, UCBRFx=0 */
UCA0CTL1 &= ~UCSWRST; /* Initialize USCI state machine */
/* Enable RX Interrupt on UART */
UCA0IFG &= ~ (UCRXIFG | UCRXIFG);
UCA0IE |= UCRXIE;
/* Configure Pin 1.3 and 1.4 as RTS as CTS */
P1SEL &= ~(BIT3 + BIT4);
P1OUT &= ~BIT4;
P1DIR |= BIT4;
P1DIR &= ~BIT3;
P1REN |= BIT3;
/* 50 ms delay */
Delay(50);
/* Enable WLAN interrupt */
CC3100_InterruptEnable();
clear_rts();
return NONOS_RET_OK;
}
Fd_t uart_Open(char *ifName, unsigned long flags)
{
/* Configure CS (PE0) and nHIB (PE4) lines */
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_4);
ROM_GPIOPinWrite(GPIO_PORTE_BASE,GPIO_PIN_4, PIN_LOW);
/* configuring UART interface */
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
GPIOPinConfigure(GPIO_PB0_U1RX);
GPIOPinConfigure(GPIO_PB1_U1TX);
ROM_GPIOPinTypeUART(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1);
GPIOPinConfigure(GPIO_PC4_U1RTS);
GPIOPinConfigure(GPIO_PC5_U1CTS);
ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
GPIOPadConfigSet(GPIO_PORTB_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
/* configure with baud rate 115200 */
ROM_UARTConfigSetExpClk(UART1_BASE, ROM_SysCtlClockGet(), 115200,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE));
UARTFlowControlSet(UART1_BASE, UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX);
UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX1_8, UART_FIFO_RX1_8);
ROM_UARTEnable(UART1_BASE);
ROM_UARTFIFOEnable(UART1_BASE);
ROM_IntEnable(INT_UART1);
ROM_UARTIntEnable(UART1_BASE, UART_INT_RX);
ROM_UARTIntDisable(UART1_BASE, UART_INT_TX | UART_INT_RT);
/* configure host IRQ line */
GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_2);
GPIOPadConfigSet(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPD);
GPIOIntTypeSet(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_RISING_EDGE);
GPIOIntClear(GPIO_PORTB_BASE,GPIO_PIN_2);
GPIOIntDisable(GPIO_PORTB_BASE,GPIO_PIN_2);
ROM_IntEnable(INT_GPIOB);
ROM_IntMasterEnable();
IntIsMasked = FALSE;
/* Enable WLAN interrupt */
CC3100_InterruptEnable();
/* 50 ms delay */
ROM_SysCtlDelay((ROM_SysCtlClockGet()/(3*1000))*50 );
return NONOS_RET_OK;
}
Fd_t spi_Open(char *ifName, unsigned long flags)
{
//
// Enable required SSI and GPIO peripherals.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_SPI_PORT);
SysCtlPeripheralEnable(SYSCTL_PERIPH_IRQ_PORT);
SysCtlPeripheralEnable(SYSCTL_PERIPH_nHIB_PORT);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SPI);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SPI_BASE);
//
// Set pin muxing to route the SPI signals to the relevant pins.
//
GPIOPinConfigure(SPI_CLK_MUX_SEL);
GPIOPinConfigure(SPI_RX_MUX_SEL);
GPIOPinConfigure(SPI_TX_MUX_SEL);
//GPIOPinConfigure(GPIO_PB5_SSI2FSS);
//
// Configure the appropriate pins to be SSI instead of GPIO
//
GPIOPinTypeSSI(SPI_PORT,(SPI_TX_PIN | SPI_RX_PIN | SPI_CLK_PIN));
//
// Ensure that the SSI is disabled before making any configuration
// changes.
//
SSIDisable(SPI_BASE);
//
// Configure SSI with 8 bit data, Polarity '0', Phase '1' and clock
// frequency of 4Mhz.
//
SSIConfigSetExpClk(SPI_BASE, g_ui32SysClock, SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 4000000, 8);
// Configure CS and nHIB/Enable lines (CS High, nHIB Low)
GPIOPinTypeGPIOOutput(SPI_CS_PORT, SPI_CS_PIN);
GPIOPinTypeGPIOOutput(SPI_GPIO_nHIB_BASE, SPI_nHIB_PIN);
GPIOPinWrite(SPI_GPIO_nHIB_BASE,SPI_nHIB_PIN, PIN_LOW); // not necesary on cc3100
GPIOPinWrite(SPI_CS_PORT,SPI_CS_PIN, PIN_HIGH);
//
// Enable the SSI now that configuration is complete.
//
SSIEnable(SPI_BASE);
//
// configure host IRQ line
//
GPIOPinTypeGPIOInput(SPI_GPIO_IRQ_BASE, SPI_IRQ_PIN);
GPIOPadConfigSet(SPI_GPIO_IRQ_BASE, SPI_IRQ_PIN, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPD);
GPIOIntTypeSet(SPI_GPIO_IRQ_BASE, SPI_IRQ_PIN, GPIO_RISING_EDGE);
GPIOIntClear(SPI_GPIO_IRQ_BASE,SPI_IRQ_PIN);
GPIOIntDisable(SPI_GPIO_IRQ_BASE,SPI_IRQ_PIN);
IntEnable(INT_GPIO_SPI);
IntMasterEnable();
/* 1 ms delay */
ROM_SysCtlDelay( (g_ui32SysClock/(3*1000))*1 );
/* Enable WLAN interrupt */
CC3100_InterruptEnable();
return NONOS_RET_OK;
}
