/*******************************************************************************
* mvCpuIfEnablePex - Enable PCI Express.
*
* DESCRIPTION:
* This function enables PCI Express access to the device address
* space.
*
* INPUT:
* pexIf - The PCI-E interface to enable.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvCpuIfEnablePex(MV_U32 pexIf)
{
MV_U32 reg;
if (mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf) == MV_TRUE) {
if (pexIf == 0) {
reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PEX_LINK_CAPABILITY_REG));
reg &= ~PXLC_MAX_LNK_SPEED_MASK;
reg |= (0x1 << PXLC_MAX_LNK_SPEED_OFFS);
MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(0, PEX_LINK_CAPABILITY_REG), reg);
}
/* CPU config register Pex enable */
MV_REG_BIT_SET(CPU_CTRL_STAT_REG, CCSR_PCI_ACCESS_MASK(pexIf));
}
}
MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType)
{
/* Set pex mode incase S@R not exist */
if( pexType == MV_PEX_END_POINT)
{
MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK);
/* Change pex mode in capability reg */
MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22);
MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20);
}
else
{
MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK);
}
/* CPU config register Pex enable */
MV_REG_BIT_SET(CPU_CTRL_STAT_REG,(CCSR_PCI_ACCESS_MASK(pexIf)));
}