bool processCode() {
enum parseType t;
void *obj;
while (ip != NULL) {
//copy the struct stuff
t = ip->t;
obj = ip->match;
//increment the up
ip = ip->next;
//processing section
switch (t) {
case tNOCODE: continue;
case tERR: return false;
case tS04:
XS04(CEX(S04_st, obj));
break;
case tS05:
XS05(CEX(S04_st, obj));
break;
case tS06:
XS06(CEX(S04_st, obj));
break;
case tS07:
XS07(CEX(S04_st, obj));
break;
case tS08:
XS08(CEX(S04_st, obj));
break;
case tS09:
XS09(CEX(S04_st, obj));
break;
case tS10:
XS10(CEX(S04_st, obj));
break;
case tS11:
XS11(CEX(S04_st, obj));
break;
case tS12:
XS12(CEX(S04_st, obj));
break;
case tS13:
XS13(CEX(S04_st, obj));
break;
case tS14:
XS14(CEX(S04_st, obj));
break;
case tS15:
XS15(CEX(S04_st, obj));
break;
case tS16:
XS16(CEX(S04_st, obj));
break;
case tS17:
XS17(CEX(S04_st, obj));
break;
case tS18:
XS18(CEX(S04_st, obj));
break;
case tS20:
XS20(CEX(S04_st, obj));
break;
default: continue;
}
}
}
cb (imm2) Bitfield position (0-31) in bits <14:10>.
cP (imm1) Coprocessor number in bits <25:24>.
cO (imm2) Coprocessor instruction in bits <23:0>.
cX (imm) 16-bit signed or unsigned immediate in bits <24:10> except MSB in <9>.
bB (imm) 22-bit branch address in bits <21:0>.
bJ (imm) 25-bit jump address in bits <24:0>. */
const struct coffee_opcode coffee_opcodes[] =
{
{"add", OP(0x01), "rD,rA,rB", F_CEX},
{"addi", OP(0x2D), "rD,rA,cI", F_CEX},
{"addiu", OP(0x28), "rD,rA,cU", F_CEX},
{"addu", OP(0x00), "rD,rA,rB", F_CEX},
{"and", OP(0x02), "rD,rA,rB", F_CEX},
{"andi", OP(0x29), "rD,rA,cU", F_CEX},
{"bc", OP(0x20)|CEX(1), "rC,bB", F_BRANCH},
{"begt", OP(0x21)|CEX(1), "rC,bB", F_BRANCH},
{"belt", OP(0x22)|CEX(1), "rC,bB", F_BRANCH},
{"beq", OP(0x23)|CEX(1), "rC,bB", F_BRANCH},
{"bgt", OP(0x24)|CEX(1), "rC,bB", F_BRANCH},
{"blt", OP(0x25)|CEX(1), "rC,bB", F_BRANCH},
{"bne", OP(0x26)|CEX(1), "rC,bB", F_BRANCH},
{"bnc", OP(0x27)|CEX(1), "rC,bB", F_BRANCH},
{"chrs", OP(0x33), "cN", 0},
{"cmp", OP(0x19), "rC,rA,rB", 0},
{"cmpi", OP(0x37), "rC,rA,cC", 0},
{"conb", OP(0x03), "rD,rA,rB", F_CEX},
{"conh", OP(0x04), "rD,rB,rA", F_CEX},
{"cop", OP(0x3C), "cP,cO", 0},
{"di", OP(0x15), "", 0},
{"ei", OP(0x16), "", 0},
