void LCD_Write(uint8 data_or_command, uint8 data_value) { CE_Write(LOW); CyDelayUs(DELAY_1_US); DC_Write(data_or_command); Send_Data(data_value); CE_Write(HIGH); CyDelayUs(DELAY_1_US); }
int main() { uint8 data; uint8 payload; char OutputString[8]; uint8 status; CyGlobalIntEnable; SPI_Start(); UART_Start(); UART_UartPutString("\n"); UART_UartPutString("Writing registers... \n"); // reflect TX_DS and MAX_RT interrupts as IRQ active low, enable 2-byte CRC, power-up, TX mode NRF24L01_WriteReg(NRF24L01_00_CONFIG, 0x4E); //01001110 // enable auto acknowledgement pipe 0 NRF24L01_WriteReg(NRF24L01_01_EN_AA, 0x01); //00000001 // 5 byte address width NRF24L01_WriteReg(NRF24L01_03_SETUP_AW, 0x03); //00000011 // 1 byte of payload on pipe 0 NRF24L01_WriteReg(NRF24L01_11_RX_PW_P0, 0x01); //00000001 UART_UartPutString("Reading registers... \n"); sprintf(OutputString, "Config: %x \n", NRF24L01_ReadReg(NRF24L01_00_CONFIG)); UART_UartPutString(OutputString); sprintf(OutputString, "EN_AA: %x \n", NRF24L01_ReadReg(NRF24L01_01_EN_AA)); UART_UartPutString(OutputString); sprintf(OutputString, "Setup_AW: %x \n", NRF24L01_ReadReg(NRF24L01_03_SETUP_AW)); UART_UartPutString(OutputString); sprintf(OutputString, "RX_PW_P0: %x \n", NRF24L01_ReadReg(NRF24L01_11_RX_PW_P0)); UART_UartPutString(OutputString); UART_UartPutString("\n"); for(;;) { //reading input LED_Write(!SW_Read()); payload = !SW_Read(); //sending data into TX FIFO NRF24L01_WritePayload(&payload, 1); //transmitting data CE_Write(1); CyDelayUs(10); CE_Write(0); //waiting for interrupt while (IRQ_Read()) ; //checking interrupt type (0x2E = TX_DS, RX FIFO empty) data = NRF24L01_ReadReg(NRF24L01_07_STATUS); sprintf(OutputString, "%x: ", data); UART_UartPutString(OutputString); // TX_DS = 0x20 MAX_RT = 0x10 if ((data & 0x20) || (data & 0x10)){ if ((data & 0x20)) UART_UartPutString("Data sent!\n"); if (data & 0x10) UART_UartPutString("Max RT achieved!\n"); } else { UART_UartPutString("Wrong interrupt?\n"); } //clearing status register NRF24L01_WriteReg(NRF24L01_07_STATUS, (1 << NRF24L01_07_RX_DR) | (1 << NRF24L01_07_TX_DS) | (1 << NRF24L01_07_MAX_RT)); //delay for debugging purposes CyDelay(750); } }