/* Record the current VLIW slot on the element at the top of the write queue.
*/
void
frv_set_write_queue_slot (SIM_CPU *current_cpu)
{
FRV_VLIW *vliw = CPU_VLIW (current_cpu);
int slot = vliw->next_slot - 1;
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu);
int ix = CGEN_WRITE_QUEUE_INDEX (q) - 1;
CGEN_WRITE_QUEUE_ELEMENT *item = CGEN_WRITE_QUEUE_ELEMENT (q, ix);
CGEN_WRITE_QUEUE_ELEMENT_PIPE (item) = (*vliw->current_vliw)[slot];
}
/* Save data written to memory into the interrupt state so that it can be
copied to the appropriate EDR register, if necessary, in the event of an
interrupt. */
void
frv_save_data_written_for_interrupts (
SIM_CPU *current_cpu, CGEN_WRITE_QUEUE_ELEMENT *item
)
{
/* Record the slot containing the insn doing the write in the
interrupt state. */
frv_interrupt_state.slot = CGEN_WRITE_QUEUE_ELEMENT_PIPE (item);
/* Now record any data written to memory in the interrupt state. */
switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
{
case CGEN_BI_WRITE:
case CGEN_QI_WRITE:
case CGEN_SI_WRITE:
case CGEN_SF_WRITE:
case CGEN_PC_WRITE:
case CGEN_FN_HI_WRITE:
case CGEN_FN_SI_WRITE:
case CGEN_FN_SF_WRITE:
case CGEN_FN_DI_WRITE:
case CGEN_FN_DF_WRITE:
case CGEN_FN_XI_WRITE:
case CGEN_FN_PC_WRITE:
break; /* Ignore writes to registers. */
case CGEN_MEM_QI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_qi_write.value;
break;
case CGEN_MEM_HI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_hi_write.value;
break;
case CGEN_MEM_SI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_si_write.value;
break;
case CGEN_MEM_DI_WRITE:
frv_interrupt_state.data_written.length = 2;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_di_write.value >> 32;
frv_interrupt_state.data_written.words[1]
= item->kinds.mem_di_write.value;
break;
case CGEN_MEM_DF_WRITE:
frv_interrupt_state.data_written.length = 2;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_df_write.value >> 32;
frv_interrupt_state.data_written.words[1]
= item->kinds.mem_df_write.value;
break;
case CGEN_MEM_XI_WRITE:
frv_interrupt_state.data_written.length = 4;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_xi_write.value[0];
frv_interrupt_state.data_written.words[1]
= item->kinds.mem_xi_write.value[1];
frv_interrupt_state.data_written.words[2]
= item->kinds.mem_xi_write.value[2];
frv_interrupt_state.data_written.words[3]
= item->kinds.mem_xi_write.value[3];
break;
case CGEN_FN_MEM_QI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_qi_write.value;
break;
case CGEN_FN_MEM_HI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_hi_write.value;
break;
case CGEN_FN_MEM_SI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_si_write.value;
break;
case CGEN_FN_MEM_DI_WRITE:
frv_interrupt_state.data_written.length = 2;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_di_write.value >> 32;
frv_interrupt_state.data_written.words[1]
= item->kinds.fn_mem_di_write.value;
break;
case CGEN_FN_MEM_DF_WRITE:
frv_interrupt_state.data_written.length = 2;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_df_write.value >> 32;
frv_interrupt_state.data_written.words[1]
= item->kinds.fn_mem_df_write.value;
break;
case CGEN_FN_MEM_XI_WRITE:
frv_interrupt_state.data_written.length = 4;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_xi_write.value[0];
frv_interrupt_state.data_written.words[1]
= item->kinds.fn_mem_xi_write.value[1];
frv_interrupt_state.data_written.words[2]
= item->kinds.fn_mem_xi_write.value[2];
frv_interrupt_state.data_written.words[3]
= item->kinds.fn_mem_xi_write.value[3];
break;
default:
{
SIM_DESC sd = CPU_STATE (current_cpu);
IADDR pc = CPU_PC_GET (current_cpu);
sim_engine_abort (sd, current_cpu, pc,
"unknown write kind during save for interrupt\n");
}
break;
}
}
