static void
via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa,
int satareg_shift)
{
struct pciide_channel *cp;
struct ata_channel *wdc_cp;
struct wdc_regs *wdr;
pcireg_t interface;
int channel;
interface = PCI_INTERFACE(pa->pa_class);
if (via_sata_chip_map_common(sc, pa) == 0)
return;
if (interface == 0) {
ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
DEBUG_PROBE);
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
}
sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
sc->sc_wdcdev.wdc_maxdrives = 1;
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
wdc_cp = &cp->ata_channel;
wdr = CHAN_TO_WDC_REGS(wdc_cp);
wdr->sata_iot = sc->sc_ba5_st;
wdr->sata_baseioh = sc->sc_ba5_sh;
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << satareg_shift) + 0x0, 4,
&wdr->sata_status) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_status regs\n",
wdc_cp->ch_channel);
continue;
}
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << satareg_shift) + 0x4, 4,
&wdr->sata_error) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_error regs\n",
wdc_cp->ch_channel);
continue;
}
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << satareg_shift) + 0x8, 4,
&wdr->sata_control) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_control regs\n",
wdc_cp->ch_channel);
continue;
}
pciide_mapchan(pa, cp, interface, pciide_pci_intr);
}
}
void
wdc_obio_select(struct ata_channel *chp, int drive)
{
struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac;
struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh,
CONFIG_REG, sc->sc_dmaconf[drive]);
}
void
__wdc_spd_bus_space(struct ata_channel *ch)
{
struct wdc_regs *wdr = CHAN_TO_WDC_REGS(ch);
int i;
wdr->cmd_iot = &_wdc_spd_space;
for (i = 0; i < 8; i++)
wdr->cmd_iohs[i] = SPD_HDD_IO_BASE + i * 2; /* wdc register is 16 bit wide. */
wdc_init_shadow_regs(ch);
wdr->ctl_iot = &_wdc_spd_space;
wdr->ctl_ioh = SPD_HDD_IO_BASE + WDC_SPD_HDD_AUXREG_OFFSET;
wdr->data32iot = wdr->cmd_iot;
wdr->data32ioh = SPD_HDD_IO_BASE;
}
void
pciide_pnpbios_attach(device_t parent, device_t self, void *aux)
{
struct pciide_softc *sc = device_private(self);
struct pnpbiosdev_attach_args *aa = aux;
struct pciide_channel *cp;
struct ata_channel *wdc_cp;
struct wdc_regs *wdr;
bus_space_tag_t compat_iot;
bus_space_handle_t cmd_baseioh, ctl_ioh;
int i, drive, size;
uint8_t idedma_ctl;
sc->sc_wdcdev.sc_atac.atac_dev = self;
aprint_naive(": disk controller\n");
aprint_normal("\n");
pnpbios_print_devres(self, aa);
aprint_normal_dev(self, "Toshiba Extended IDE Controller\n");
if (pnpbios_io_map(aa->pbt, aa->resc, 2, &sc->sc_dma_iot,
&sc->sc_dma_ioh) != 0) {
aprint_error_dev(self, "unable to map DMA registers\n");
return;
}
if (pnpbios_io_map(aa->pbt, aa->resc, 0, &compat_iot,
&cmd_baseioh) != 0) {
aprint_error_dev(self, "unable to map command registers\n");
return;
}
if (pnpbios_io_map(aa->pbt, aa->resc, 1, &compat_iot,
&ctl_ioh) != 0) {
aprint_error_dev(self, "unable to map control register\n");
return;
}
sc->sc_dmat = &pci_bus_dma_tag;
cp = &sc->pciide_channels[0];
sc->wdc_chanarray[0] = &cp->ata_channel;
cp->ata_channel.ch_channel = 0;
cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
cp->ata_channel.ch_queue = malloc(sizeof(struct ata_queue),
M_DEVBUF, M_NOWAIT);
cp->ata_channel.ch_ndrive = 2;
if (cp->ata_channel.ch_queue == NULL) {
aprint_error_dev(self, "unable to allocate memory for command "
"queue\n");
return;
}
sc->sc_dma_ok = 1;
for (i = 0; i < IDEDMA_NREGS; i++) {
size = 4;
if (size > (IDEDMA_SCH_OFFSET - i))
size = IDEDMA_SCH_OFFSET - i;
if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh,
i, size, &cp->dma_iohs[i]) != 0) {
aprint_error_dev(self, "can't subregion offset %d "
"size %lu", i, (u_long)size);
return;
}
}
sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX;
sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN;
sc->sc_wdcdev.dma_arg = sc;
sc->sc_wdcdev.dma_init = pciide_dma_init;
sc->sc_wdcdev.dma_start = pciide_dma_start;
sc->sc_wdcdev.dma_finish = pciide_dma_finish;
sc->sc_wdcdev.irqack = pciide_irqack;
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; /* XXX */
sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; /* XXX */
wdc_allocate_regs(&sc->sc_wdcdev);
wdc_cp = &cp->ata_channel;
wdr = CHAN_TO_WDC_REGS(wdc_cp);
wdr->cmd_iot = compat_iot;
wdr->cmd_baseioh = cmd_baseioh;
for (i = 0; i < WDC_NREG; i++) {
if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i,
i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
aprint_error_dev(self, "unable to subregion "
"control register\n");
return;
}
}
wdc_init_shadow_regs(wdc_cp);
wdr->ctl_iot = wdr->data32iot = compat_iot;
wdr->ctl_ioh = wdr->data32ioh = ctl_ioh;
cp->compat = 1;
cp->ih = pnpbios_intr_establish(aa->pbt, aa->resc, 0, IPL_BIO,
pciide_compat_intr, cp);
wdcattach(wdc_cp);
idedma_ctl = 0;
for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) {
/*
* we have not probed the drives yet,
* allocate ressources for all of them.
*/
if (pciide_dma_table_setup(sc, 0, drive) != 0) {
/* Abort DMA setup */
aprint_error(
"%s:%d:%d: can't allocate DMA maps, "
"using PIO transfers\n",
device_xname(self), 0, drive);
sc->sc_dma_ok = 0;
sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
sc->sc_wdcdev.irqack = NULL;
idedma_ctl = 0;
break;
}
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
}
if (idedma_ctl != 0) {
/* Add software bits in status register */
bus_space_write_1(sc->sc_dma_iot,
cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl);
}
}
static void
via_sata_chip_map_new(struct pciide_softc *sc,
const struct pci_attach_args *pa)
{
struct pciide_channel *cp;
struct ata_channel *wdc_cp;
struct wdc_regs *wdr;
int channel;
pci_intr_handle_t intrhandle;
const char *intrstr;
int i;
if (pciide_chipen(sc, pa) == 0)
return;
sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE;
if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0,
&sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map SATA regs\n");
}
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
via_vt6421_mapreg_dma(sc, pa);
aprint_verbose("\n");
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
sc->sc_wdcdev.irqack = pciide_irqack;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
}
sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = 3;
sc->sc_wdcdev.wdc_maxdrives = 2;
wdc_allocate_regs(&sc->sc_wdcdev);
if (pci_intr_map(pa, &intrhandle) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map native-PCI interrupt\n");
return;
}
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
intrhandle, IPL_BIO, pciide_pci_intr, sc);
if (sc->sc_pci_ih == NULL) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't establish native-PCI interrupt");
if (intrstr != NULL)
aprint_error(" at %s", intrstr);
aprint_error("\n");
return;
}
aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"using %s for native-PCI interrupt\n",
intrstr ? intrstr : "unknown interrupt");
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (via_vt6421_chansetup(sc, channel) == 0)
continue;
wdc_cp = &cp->ata_channel;
wdr = CHAN_TO_WDC_REGS(wdc_cp);
wdr->sata_iot = sc->sc_ba5_st;
wdr->sata_baseioh = sc->sc_ba5_sh;
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << 6) + 0x0, 4,
&wdr->sata_status) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_status regs\n",
wdc_cp->ch_channel);
continue;
}
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << 6) + 0x4, 4,
&wdr->sata_error) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_error regs\n",
wdc_cp->ch_channel);
continue;
}
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << 6) + 0x8, 4,
&wdr->sata_control) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_control regs\n",
wdc_cp->ch_channel);
continue;
}
if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel),
PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh,
NULL, &wdr->cmd_ios) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map %s channel regs\n", cp->name);
}
wdr->ctl_iot = wdr->cmd_iot;
for (i = 0; i < WDC_NREG; i++) {
if (bus_space_subregion(wdr->cmd_iot,
wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
&wdr->cmd_iohs[i]) != 0) {
aprint_error_dev(
sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't subregion %s "
"channel cmd regs\n", cp->name);
return;
}
}
if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d ctl regs\n", channel);
return;
}
wdc_init_shadow_regs(wdc_cp);
wdr->data32iot = wdr->cmd_iot;
wdr->data32ioh = wdr->cmd_iohs[wd_data];
wdcattach(wdc_cp);
}
}
void
wdc_buddha_attach(device_t parent, device_t self, void *aux)
{
struct wdc_buddha_softc *sc;
struct zbus_args *zap;
int nchannels;
int ch;
sc = device_private(self);
sc->sc_wdcdev.sc_atac.atac_dev = self;
zap = aux;
sc->ba = zap->va;
sc->sc_iot.base = (bus_addr_t)sc->ba;
sc->sc_iot.absm = &amiga_bus_stride_4swap;
nchannels = 2;
if (zap->prodid == 42) {
aprint_normal(": Catweasel Z2\n");
nchannels = 3;
} else if (zap->serno == 0)
aprint_normal(": Buddha\n");
else
aprint_normal(": Buddha Flash\n");
/* XXX pio mode setting not implemented yet. */
sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = nchannels;
wdc_allocate_regs(&sc->sc_wdcdev);
for (ch = 0; ch < nchannels; ch++) {
struct ata_channel *cp;
struct wdc_regs *wdr;
int i;
cp = &sc->channels[ch];
sc->wdc_chanarray[ch] = cp;
cp->ch_channel = ch;
cp->ch_atac = &sc->sc_wdcdev.sc_atac;
cp->ch_queue =
malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
if (cp->ch_queue == NULL) {
aprint_error_dev(self,
"can't allocate memory for command queue\n");
return;
}
cp->ch_ndrive = 2;
/*
* XXX According to the Buddha docs, we should use a method
* array that adds 0x40 to the address for byte accesses, to
* get the slow timing for command accesses, and the 0x00
* offset for the word (fast) accesses. This will be
* reconsidered when implementing setting the timing.
*
* XXX We also could consider to abuse the 32bit capability, or
* 32bit accesses to the words (which will read in two words)
* for better performance.
* -is
*/
wdr = CHAN_TO_WDC_REGS(cp);
wdr->cmd_iot = &sc->sc_iot;
if (bus_space_map(wdr->cmd_iot, 0x210+ch*0x80, 8, 0,
&wdr->cmd_baseioh)) {
aprint_error_dev(self, "couldn't map cmd registers\n");
return;
}
wdr->ctl_iot = &sc->sc_iot;
if (bus_space_map(wdr->ctl_iot, 0x250+ch*0x80, 2, 0,
&wdr->ctl_ioh)) {
bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 8);
aprint_error_dev(self, "couldn't map ctl registers\n");
return;
}
for (i = 0; i < WDC_NREG; i++) {
if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
i, i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
aprint_error_dev(self,
"couldn't subregion cmd regs\n");
return;
}
}
wdc_init_shadow_regs(cp);
wdcattach(cp);
}
sc->sc_isr.isr_intr = wdc_buddha_intr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_ipl = 2;
add_isr (&sc->sc_isr);
sc->ba[0xfc0] = 0; /* enable interrupts */
}
static void
artisea_mapregs(struct pci_attach_args *pa, struct pciide_channel *cp,
bus_size_t *cmdsizep, bus_size_t *ctlsizep,
int (*pci_intr)(void *))
{
struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
struct ata_channel *wdc_cp = &cp->ata_channel;
struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
const char *intrstr;
pci_intr_handle_t intrhandle;
int i;
cp->compat = 0;
if (sc->sc_pci_ih == NULL) {
if (pci_intr_map(pa, &intrhandle) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map native-PCI interrupt\n");
goto bad;
}
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
intrhandle, IPL_BIO, pci_intr, sc);
if (sc->sc_pci_ih != NULL) {
aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"using %s for native-PCI interrupt\n",
intrstr ? intrstr : "unknown interrupt");
} else {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't establish native-PCI interrupt");
if (intrstr != NULL)
aprint_normal(" at %s", intrstr);
aprint_normal("\n");
goto bad;
}
}
cp->ih = sc->sc_pci_ih;
wdr->cmd_iot = sc->sc_ba5_st;
if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh,
ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200,
&wdr->cmd_baseioh) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map %s channel cmd regs\n", cp->name);
goto bad;
}
wdr->ctl_iot = sc->sc_ba5_st;
if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map %s channel ctl regs\n", cp->name);
goto bad;
}
wdr->ctl_ioh = cp->ctl_baseioh;
for (i = 0; i < WDC_NREG + 2; i++) {
if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size,
&wdr->cmd_iohs[i]) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't subregion %s channel cmd regs\n",
cp->name);
goto bad;
}
}
wdr->data32iot = wdr->cmd_iot;
wdr->data32ioh = wdr->cmd_iohs[0];
wdr->sata_iot = wdr->cmd_iot;
wdr->sata_baseioh = wdr->cmd_baseioh;
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR, 1,
&wdr->sata_status) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_status regs\n",
wdc_cp->ch_channel);
goto bad;
}
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSER, 1,
&wdr->sata_error) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_error regs\n",
wdc_cp->ch_channel);
goto bad;
}
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 1,
&wdr->sata_control) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_control regs\n",
wdc_cp->ch_channel);
goto bad;
}
wdcattach(wdc_cp);
return;
bad:
wdc_cp->ch_flags |= ATACH_DISABLED;
return;
}
