int
sflash_write(si_t *sih, chipcregs_t *cc, uint offset, uint length, const uchar *buffer)
{
struct sflash *sfl;
uint off = offset, len = length;
const uint8 *buf = buffer;
uint8 data;
int ret = 0, ntry = 0;
bool is4712b0;
uint32 page, byte, mask;
osl_t *osh;
ASSERT(sih);
osh = si_osh(sih);
if (!len)
return 0;
sfl = &sflash;
if ((off + len) > sfl->size)
return -22;
switch (sfl->type) {
case SFLASH_ST:
is4712b0 = (CHIPID(sih->chip) == BCM4712_CHIP_ID) && (CHIPREV(sih->chiprev) == 3);
/* Enable writes */
retry: sflash_cmd(osh, cc, SFLASH_ST_WREN);
off = offset;
len = length;
buf = buffer;
ntry++;
if (is4712b0) {
mask = 1 << 14;
W_REG(osh, &cc->flashaddress, off);
data = GET_BYTE(buf);
buf++;
W_REG(osh, &cc->flashdata, data);
/* Set chip select */
OR_REG(osh, &cc->gpioout, mask);
/* Issue a page program with the first byte */
sflash_cmd(osh, cc, SFLASH_ST_PP);
ret = 1;
off++;
len--;
while (len > 0) {
if ((off & 255) == 0) {
/* Page boundary, drop cs and return */
AND_REG(osh, &cc->gpioout, ~mask);
OSL_DELAY(1);
if (!sflash_poll(sih, cc, off)) {
/* Flash rejected command */
if (ntry <= ST_RETRIES)
goto retry;
else
return -11;
}
return ret;
} else {
/* Write single byte */
data = GET_BYTE(buf);
buf++;
sflash_cmd(osh, cc, data);
}
ret++;
off++;
len--;
}
/* All done, drop cs */
AND_REG(osh, &cc->gpioout, ~mask);
OSL_DELAY(1);
if (!sflash_poll(sih, cc, off)) {
/* Flash rejected command */
if (ntry <= ST_RETRIES)
goto retry;
else
return -12;
}
} else if (sih->ccrev >= 20) {
W_REG(osh, &cc->flashaddress, off);
data = GET_BYTE(buf);
buf++;
W_REG(osh, &cc->flashdata, data);
/* Issue a page program with CSA bit set */
sflash_cmd(osh, cc, SFLASH_ST_CSA | SFLASH_ST_PP);
ret = 1;
off++;
len--;
while (len > 0) {
if ((off & 255) == 0) {
/* Page boundary, poll droping cs and return */
W_REG(NULL, &cc->flashcontrol, 0);
OSL_DELAY(1);
if (sflash_poll(sih, cc, off) == 0) {
/* Flash rejected command */
SFL_MSG(("sflash: pp rejected, ntry: %d,"
" off: %d/%d, len: %d/%d, ret:"
"%d\n", ntry, off, offset, len,
length, ret));
if (ntry <= ST_RETRIES)
goto retry;
else
return -11;
}
return ret;
} else {
/* Write single byte */
data = GET_BYTE(buf);
buf++;
sflash_cmd(osh, cc, SFLASH_ST_CSA | data);
}
ret++;
off++;
len--;
}
/* All done, drop cs & poll */
W_REG(NULL, &cc->flashcontrol, 0);
OSL_DELAY(1);
if (sflash_poll(sih, cc, off) == 0) {
/* Flash rejected command */
SFL_MSG(("sflash: pp rejected, ntry: %d, off: %d/%d,"
" len: %d/%d, ret: %d\n",
ntry, off, offset, len, length, ret));
if (ntry <= ST_RETRIES)
goto retry;
else
return -12;
}
} else {
ret = 1;
W_REG(osh, &cc->flashaddress, off);
data = GET_BYTE(buf);
buf++;
W_REG(osh, &cc->flashdata, data);
/* Page program */
sflash_cmd(osh, cc, SFLASH_ST_PP);
}
break;
case SFLASH_AT:
mask = sfl->blocksize - 1;
page = (off & ~mask) << 1;
byte = off & mask;
/* Read main memory page into buffer 1 */
if (byte || (len < sfl->blocksize)) {
W_REG(osh, &cc->flashaddress, page);
sflash_cmd(osh, cc, SFLASH_AT_BUF1_LOAD);
/* 250 us for AT45DB321B */
SPINWAIT(sflash_poll(sih, cc, off), 1000);
ASSERT(!sflash_poll(sih, cc, off));
}
/* Write into buffer 1 */
for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
W_REG(osh, &cc->flashaddress, byte++);
W_REG(osh, &cc->flashdata, *buf++);
sflash_cmd(osh, cc, SFLASH_AT_BUF1_WRITE);
}
/* Write buffer 1 into main memory page */
W_REG(osh, &cc->flashaddress, page);
sflash_cmd(osh, cc, SFLASH_AT_BUF1_PROGRAM);
break;
}
return ret;
}
/**
* Balance between stable SDIO operation and power consumption is achieved using this function.
* Note that each drive strength table is for a specific VDDIO of the SDIO pads, ideally this
* function should read the VDDIO itself to select the correct table. For now it has been solved
* with the 'BCM_SDIO_VDDIO' preprocessor constant.
*
* 'drivestrength': desired pad drive strength in mA. Drive strength of 0 requests tri-state (if
* hardware supports this), if no hw support drive strength is not programmed.
*/
void
si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength)
{
sdiod_drive_str_t *str_tab = NULL;
uint32 str_mask = 0; /* only alter desired bits in PMU chipcontrol 1 register */
uint32 str_shift = 0;
uint32 str_ovr_pmuctl = PMU_CHIPCTL0; /* PMU chipcontrol register containing override bit */
uint32 str_ovr_pmuval = 0; /* position of bit within this register */
pmuregs_t *pmu;
uint origidx;
if (!(sih->cccaps & CC_CAP_PMU)) {
return;
}
/* Remember original core before switch to chipc/pmu */
origidx = si_coreidx(sih);
if (AOB_ENAB(sih)) {
pmu = si_setcore(sih, PMU_CORE_ID, 0);
} else {
pmu = si_setcoreidx(sih, SI_CC_IDX);
}
ASSERT(pmu != NULL);
switch (SDIOD_DRVSTR_KEY(CHIPID(sih->chip), sih->pmurev)) {
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab1;
str_mask = 0x30000000;
str_shift = 28;
break;
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
case SDIOD_DRVSTR_KEY(BCM4315_CHIP_ID, 4):
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab2;
str_mask = 0x00003800;
str_shift = 11;
break;
case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 11):
if (sih->pmurev == 8) {
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab3;
}
else if (sih->pmurev == 11) {
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab4_1v8;
}
str_mask = 0x00003800;
str_shift = 11;
break;
case SDIOD_DRVSTR_KEY(BCM4330_CHIP_ID, 12):
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab4_1v8;
str_mask = 0x00003800;
str_shift = 11;
break;
case SDIOD_DRVSTR_KEY(BCM43362_CHIP_ID, 13):
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab5_1v8;
str_mask = 0x00003800;
str_shift = 11;
break;
case SDIOD_DRVSTR_KEY(BCM4334_CHIP_ID, 17):
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab6_1v8;
str_mask = 0x00001800;
str_shift = 11;
break;
case SDIOD_DRVSTR_KEY(BCM43143_CHIP_ID, 17):
#if !defined(BCM_SDIO_VDDIO) || BCM_SDIO_VDDIO == 33
if (drivestrength >= ARRAYLAST(sdiod_drive_strength_tab7_3v3)->strength) {
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab7_3v3;
}
#else
if (drivestrength >= ARRAYLAST(sdiod_drive_strength_tab7_1v8)->strength) {
str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab7_1v8;
}
#endif /* BCM_SDIO_VDDIO */
str_mask = 0x00000007;
str_ovr_pmuval = PMU43143_CC0_SDIO_DRSTR_OVR;
break;
default:
PMU_MSG(("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
bcm_chipname(
CHIPID(sih->chip), chn, 8), CHIPREV(sih->chiprev), sih->pmurev));
break;
}
if (str_tab != NULL) {
uint32 cc_data_temp;
int i;
/* Pick the lowest available drive strength equal or greater than the
* requested strength. Drive strength of 0 requests tri-state.
*/
for (i = 0; drivestrength < str_tab[i].strength; i++)
;
if (i > 0 && drivestrength > str_tab[i].strength)
i--;
W_REG(osh, &pmu->chipcontrol_addr, PMU_CHIPCTL1);
cc_data_temp = R_REG(osh, &pmu->chipcontrol_data);
cc_data_temp &= ~str_mask;
cc_data_temp |= str_tab[i].sel << str_shift;
W_REG(osh, &pmu->chipcontrol_data, cc_data_temp);
if (str_ovr_pmuval) { /* enables the selected drive strength */
W_REG(osh, &pmu->chipcontrol_addr, str_ovr_pmuctl);
OR_REG(osh, &pmu->chipcontrol_data, str_ovr_pmuval);
}
PMU_MSG(("SDIO: %dmA drive strength requested; set to %dmA\n",
drivestrength, str_tab[i].strength));
}
/* Return to original core */
si_setcoreidx(sih, origidx);
} /* si_sdiod_drive_strength_init */
