void __init prom_init(void)
{
int argc = fw_arg0;
u32 *argv = (u32 *)CKSEG0ADDR(fw_arg1);
int i;
char console_string[40];
print_board_type();
kerSysEarlyFlashInit();
prom_init_cmdline();
strcat(arcs_cmdline, " ");
for (i = 1; i < argc; i++) {
strcat(arcs_cmdline, (char *)CKSEG0ADDR(argv[i]));
if (i < (argc - 1))
strcat(arcs_cmdline, " ");
}
if(!strstr(arcs_cmdline, "console=ttyS"))
{
sprintf(console_string, " console=ttyS0,%d%c%c%c", 115200, 'n', '8', '\0');
strcat(arcs_cmdline, console_string);
prom_printf("Config serial console:%s\n", console_string);
}
retrieve_boot_loader_parameters();
}
void __init prom_init(void)
{
int argc = fw_arg0;
u32 *argv = (u32 *)CKSEG0ADDR(fw_arg1);
int i;
sni_mem_init();
/* copy prom cmdline parameters to kernel cmdline */
for (i = 1; i < argc; i++) {
strcat(arcs_cmdline, (char *)CKSEG0ADDR(argv[i]));
if (i < (argc - 1))
strcat(arcs_cmdline, " ");
}
}
void amon_cpu_start(int cpu,
unsigned long pc, unsigned long sp,
unsigned long gp, unsigned long a0)
{
volatile struct cpulaunch *launch =
(struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
if (!amon_cpu_avail(cpu))
return;
if (cpu == smp_processor_id()) {
pr_debug("launch: I am cpu%d!\n", cpu);
return;
}
launch += cpu;
pr_debug("launch: starting cpu%d\n", cpu);
launch->pc = pc;
launch->gp = gp;
launch->sp = sp;
launch->a0 = a0;
/* Make sure target sees parameters before the go bit */
smp_mb();
launch->flags |= LAUNCH_FGO;
while ((launch->flags & LAUNCH_FGONE) == 0)
;
pr_debug("launch: cpu%d gone!\n", cpu);
}
/*
* Use the REX prom calls to get hold of the memory bitmap, and thence
* determine memory size.
*/
static inline void rex_setup_memory_region(void)
{
int i, bitmap_size;
unsigned long mem_start = 0, mem_size = 0;
memmap *bm;
/* some free 64k */
bm = (memmap *)CKSEG0ADDR(0x28000);
bitmap_size = rex_getbitmap(bm);
for (i = 0; i < bitmap_size; i++) {
/* FIXME: very simplistically only add full sets of pages */
if (bm->bitmap[i] == 0xff)
mem_size += (8 * bm->pagesize);
else if (!mem_size)
mem_start += (8 * bm->pagesize);
else {
add_memory_region(mem_start, mem_size, BOOT_MEM_RAM);
mem_start += mem_size + (8 * bm->pagesize);
mem_size = 0;
}
}
if (mem_size)
add_memory_region(mem_start, mem_size, BOOT_MEM_RAM);
}
int checkboard(void)
{
struct ps2_bootinfo *info = (void *) CKSEG0ADDR(PS2_BOOTINFO_OLDADDR);
uint32_t size;
volatile uint32_t *sbios_magic;
int sbversion = 0;
struct ps2_bootinfo bootinfo;
puts("Board: Sony Playstation 2 MIPS r5900\n");
memset(&bootinfo, 0, sizeof(bootinfo));
size = info->size;
if (size > sizeof(bootinfo)) {
size = sizeof(bootinfo);
}
memcpy(&bootinfo, info, size);
sbios_magic = (uint32_t *) SBIOS_MAGIC;
if (*sbios_magic == SBIOS_MAGICVAL) {
gd->arch._sbios = *(int (**)(int, void *))(SBIOS_BASE);
}
else
gd->arch._sbios = NULL;
sbversion = sbios(SB_GETVER, NULL);
printf("SBIOS Version 0x%08x\n", sbversion);
driver_init();
return 0;
}
int amon_cpu_start(int cpu,
unsigned long pc, unsigned long sp,
unsigned long gp, unsigned long a0)
{
volatile struct cpulaunch *launch =
(struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
if (!amon_cpu_avail(cpu))
return -1;
if (cpu == smp_processor_id()) {
pr_debug("launch: I am cpu%d!\n", cpu);
return -1;
}
launch += cpu;
pr_debug("launch: starting cpu%d\n", cpu);
launch->pc = pc;
launch->gp = gp;
launch->sp = sp;
launch->a0 = a0;
smp_wmb(); /* Target must see parameters before go */
launch->flags |= LAUNCH_FGO;
smp_wmb(); /* Target must see go before we poll */
while ((launch->flags & LAUNCH_FGONE) == 0)
;
smp_rmb(); /* Target will be updating flags soon */
pr_debug("launch: cpu%d gone!\n", cpu);
return 0;
}
void __init prom_init(void)
{
#if 0
int argc = fw_arg0;
u32 *argv = (u32 *)CKSEG0ADDR(fw_arg1);
int i;
kerSysEarlyFlashInit();
// too early in bootup sequence to acquire spinlock, not needed anyways
// only the kernel is running at this point
kerSysNvRamGetBoardIdLocked(promBoardIdStr);
printk( "%s prom init\n", promBoardIdStr );
#if defined(CONFIG_BCM_KF_DSP) && defined(CONFIG_BCM_BCMDSP_MODULE)
main_tp_num = ((read_c0_diag3() & CP0_CMT_TPID) == CP0_CMT_TPID) ? 1 : 0;
printk("Linux TP ID = %u \n", (unsigned int)main_tp_num);
#endif
PERF->IrqControl[0].IrqMask=0;
arcs_cmdline[0] = '\0';
create_cmdline(arcs_cmdline);
strcat(arcs_cmdline, " ");
for (i = 1; i < argc; i++) {
strcat(arcs_cmdline, (char *)CKSEG0ADDR(argv[i]));
if (i < (argc - 1))
strcat(arcs_cmdline, " ");
}
/* Count register increments every other clock */
mips_hpt_frequency = calculateCpuSpeed() / 2;
retrieve_boot_loader_parameters();
#endif
}
phys_size_t initdram(int board_type)
{
/* The only supported number of SDRAM banks is 4.
*/
#define CFG_NB 4
ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0;
ulong cfgdw = *INCA_IP_SDRAM_MC_CFGDW;
int cols = cfgpb0 & 0xF;
int rows = (cfgpb0 & 0xF0) >> 4;
int dw = cfgdw & 0xF;
ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
void (* sdram_init) (ulong);
sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
sdram_init(0x10000);
return size;
}
int amon_cpu_avail(int cpu)
{
struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
if (cpu < 0 || cpu >= NCPULAUNCH) {
pr_debug("avail: cpu%d is out of range\n", cpu);
return 0;
}
launch += cpu;
if (!(launch->flags & LAUNCH_FREADY)) {
pr_debug("avail: cpu%d is not ready\n", cpu);
return 0;
}
if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
return 0;
}
return 1;
}
/* Prepare DMA to start data transfer from the MMC card */
static void jz_mmc_tx_setup_data(struct jz_mmc_host *host,
struct mmc_data *data)
{
unsigned int nob = data->blocks;
int channeltx = txdmachan;
int i;
u32 size;
if (data->flags & MMC_DATA_STREAM)
nob = 0xffff;
REG_MSC_NOB = nob;
REG_MSC_BLKLEN = data->blksz;
size = nob * data->blksz;
if (data->flags & MMC_DATA_READ) {
host->dma.dir = DMA_FROM_DEVICE;
} else {
host->dma.dir = DMA_TO_DEVICE;
}
host->dma.len =
dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
host->dma.dir);
for (i = 0; i < host->dma.len; i++) {
host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
host->sg_cpu[i].dcmd = sg_dma_len(&data->sg[i]);
dma_cache_wback_inv((unsigned long)
CKSEG0ADDR(sg_dma_address(data->sg)) +
data->sg->offset,
host->sg_cpu[i].dcmd);
jz_mmc_start_dma(channeltx, host->sg_cpu[i].dtadr,
host->sg_cpu[i].dcmd, DMA_MODE_WRITE);
}
}
/**
* kvm_mips_trans_replace() - Replace trapping instruction in guest memory.
* @vcpu: Virtual CPU.
* @opc: PC of instruction to replace.
* @replace: Instruction to write
*/
static int kvm_mips_trans_replace(struct kvm_vcpu *vcpu, u32 *opc,
union mips_instruction replace)
{
unsigned long kseg0_opc, flags;
if (KVM_GUEST_KSEGX(opc) == KVM_GUEST_KSEG0) {
kseg0_opc =
CKSEG0ADDR(kvm_mips_translate_guest_kseg0_to_hpa
(vcpu, (unsigned long) opc));
memcpy((void *)kseg0_opc, (void *)&replace, sizeof(u32));
local_flush_icache_range(kseg0_opc, kseg0_opc + 32);
} else if (KVM_GUEST_KSEGX((unsigned long) opc) == KVM_GUEST_KSEG23) {
local_irq_save(flags);
memcpy((void *)opc, (void *)&replace, sizeof(u32));
local_flush_icache_range((unsigned long)opc,
(unsigned long)opc + 32);
local_irq_restore(flags);
} else {
kvm_err("%s: Invalid address: %p\n", __func__, opc);
return -EFAULT;
}
return 0;
}
void ddr_tap_tuning(void)
{
void __iomem *regs;
u32 *addr_k0, *addr_k1, *addr;
u32 val, tap, upper, lower;
int i, j, dir, err, done;
regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
MAP_NOCACHE);
/* Init memory pattern */
addr = (void *)CKSEG0ADDR(0x2000);
for (i = 0; i < 256; i++) {
val = 0;
for (j = 0; j < 8; j++) {
if (i & (1 << j)) {
if (j % 2)
val |= 0xffff0000;
else
val |= 0x0000ffff;
}
if (j % 2) {
*addr++ = val;
val = 0;
}
}
}
err = 0;
done = 0;
dir = 1;
tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
val = tap;
upper = tap;
lower = tap;
while (!done) {
err = 0;
/* Update new DDR tap value */
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
/* Compare DDR with cache */
for (i = 0; i < 2; i++) {
addr_k1 = (void *)CKSEG1ADDR(0x2000);
addr_k0 = (void *)CKSEG0ADDR(0x2000);
addr = (void *)CKSEG0ADDR(0x3000);
while (addr_k0 < addr) {
if (*addr_k1++ != *addr_k0++) {
err = 1;
break;
}
}
if (err)
break;
}
if (err) {
/* Save upper/lower threshold if error */
if (dir) {
dir = 0;
val--;
upper = val;
val = tap;
} else {
val++;
lower = val;
done = 1;
}
} else {
/* Try the next value until limitation */
if (dir) {
if (val < 0x20) {
val++;
} else {
dir = 0;
upper = val;
val = tap;
}
} else {
if (!val) {
lower = val;
done = 1;
} else {
val--;
}
}
}
}
/* compute an intermediate value and write back */
val = (upper + lower) / 2;
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
val++;
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
}
static int pic32_flash_probe(struct udevice *dev)
{
void *blob = (void *)gd->fdt_blob;
int node = dev_of_offset(dev);
const char *list, *end;
const fdt32_t *cell;
unsigned long addr, size;
int parent, addrc, sizec;
flash_info_t *info;
int len, idx;
/*
* decode regs. there are multiple reg tuples, and they need to
* match with reg-names.
*/
parent = fdt_parent_offset(blob, node);
of_bus_default_count_cells(blob, parent, &addrc, &sizec);
list = fdt_getprop(blob, node, "reg-names", &len);
if (!list)
return -ENOENT;
end = list + len;
cell = fdt_getprop(blob, node, "reg", &len);
if (!cell)
return -ENOENT;
for (idx = 0, info = &flash_info[0]; list < end;) {
addr = fdt_translate_address((void *)blob, node, cell + idx);
size = fdt_addr_to_cpu(cell[idx + addrc]);
len = strlen(list);
if (!strncmp(list, "nvm", len)) {
/* NVM controller */
nvm_regs_p = ioremap(addr, size);
} else if (!strncmp(list, "bank", 4)) {
/* Flash bank: use kseg0 cached address */
pic32_flash_bank_init(info, CKSEG0ADDR(addr), size);
info++;
}
idx += addrc + sizec;
list += len + 1;
}
/* disable flash write/erase operations */
writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
return 0;
}
