// setup hardware timer timerNum
// timerCallback: if not-NULL, will be called on any timer interrupt. Default is Match0
// For convenience various default values are setup: a default reload/Match0 period of
// 10us is set, this can be changed by setHwTimerInterval.
void setupHwTimer (uint16_t timerNum, tHwTimerCallback timerCallback)
{
TIM_TIMERCFG_Type TIM_ConfigStruct;
TIM_MATCHCFG_Type TIM_MatchConfigStruct ;
// Prescale in absolute value
TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_TICKVAL;
TIM_ConfigStruct.PrescaleValue = 1;
TIM_Init (pTimerRegs[timerNum], TIM_TIMER_MODE, &TIM_ConfigStruct);
/* Configure Timer to have the same clock as CPU: 100MHz */
CLKPWR_SetPCLKDiv (TimerConfig[timerNum].ClkPwr_PClkSel, CLKPWR_PCLKSEL_CCLK_DIV_1);
// use channel 0, MR0
TIM_MatchConfigStruct.MatchChannel = 0;
// Enable interrupt when MR0 matches the value in TC register
TIM_MatchConfigStruct.IntOnMatch = 1;
//Enable reset on MR0: TIMER will reset if MR0 matches it
TIM_MatchConfigStruct.ResetOnMatch = 1;
//Do not stop on MR0 if MR0 matches it
TIM_MatchConfigStruct.StopOnMatch = 0;
//Do not toggle MR0.0 pin if MR0 matches it
TIM_MatchConfigStruct.ExtMatchOutputType = TIM_EXTMATCH_NOTHING;
// Set Match value, count value of 100000000 (100000000 * 10ns = 100000000ns = 1s --> 1 Hz)
TIM_MatchConfigStruct.MatchValue = 1000;
TIM_ConfigMatch (pTimerRegs[timerNum], &TIM_MatchConfigStruct);
/* Set to have highest priority = 0 */
NVIC_SetPriority(TimerConfig[timerNum].TimerIrq, 0);
// store the callback address for later use
HwTimer[timerNum].timerCallback = timerCallback;
}
/*********************************************************************//**
* @brief Initializes the QEI peripheral according to the specified
* parameters in the QEI_ConfigStruct.
* @param[in] QEIx QEI peripheral, should be LPC_QEI
* @param[in] QEI_ConfigStruct Pointer to a QEI_CFG_Type structure
* that contains the configuration information for the
* specified QEI peripheral
* @return None
**********************************************************************/
void QEI_Init(LPC_QEI_TypeDef *QEIx, QEI_CFG_Type *QEI_ConfigStruct)
{
CHECK_PARAM(PARAM_QEIx(QEIx));
CHECK_PARAM(PARAM_QEI_DIRINV(QEI_ConfigStruct->DirectionInvert));
CHECK_PARAM(PARAM_QEI_SIGNALMODE(QEI_ConfigStruct->SignalMode));
CHECK_PARAM(PARAM_QEI_CAPMODE(QEI_ConfigStruct->CaptureMode));
CHECK_PARAM(PARAM_QEI_INVINX(QEI_ConfigStruct->InvertIndex));
/* Set up clock and power for QEI module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCQEI, ENABLE);
/* As default, peripheral clock for QEI module
* is set to FCCLK / 2 */
CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_QEI, CLKPWR_PCLKSEL_CCLK_DIV_1);
// Reset all remaining value in QEI peripheral
QEIx->QEICON = QEI_CON_RESP | QEI_CON_RESV | QEI_CON_RESI;
QEIx->QEIMAXPOS = 0x00;
QEIx->CMPOS0 = 0x00;
QEIx->CMPOS1 = 0x00;
QEIx->CMPOS2 = 0x00;
QEIx->INXCMP = 0x00;
QEIx->QEILOAD = 0x00;
QEIx->VELCOMP = 0x00;
QEIx->FILTER = 0x00;
// Disable all Interrupt
QEIx->QEIIEC = QEI_IECLR_BITMASK;
// Clear all Interrupt pending
QEIx->QEICLR = QEI_INTCLR_BITMASK;
// Set QEI configuration value corresponding to its setting up value
QEIx->QEICONF = ((QEI_CFGOPT_Type *)QEI_ConfigStruct)->ulQEIConfig;
}
void get_mac_addr(uint8_t *mac_buf) {
PINSEL_CFG_Type PinCfg;
I2C_M_SETUP_Type transferMCfg;
uint8_t eeprom_addr = EEPROM_ADDR;
/* Configure I2C0 */
PinCfg.OpenDrain = PINSEL_PINMODE_OPENDRAIN;
PinCfg.Pinmode = PINSEL_PINMODE_TRISTATE;
PinCfg.Funcnum = 1;
PinCfg.Pinnum = 27;
PinCfg.Portnum = 0;
PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 28;
PINSEL_ConfigPin(&PinCfg);
// Initialize Slave I2C peripheral
/* Set up clock and power for I2C0 module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C0, ENABLE);
/* As default, peripheral clock for I2C0 module
* is set to FCCLK / 2 */
CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_I2C0, CLKPWR_PCLKSEL_CCLK_DIV_2);
transferMCfg.sl_addr7bit = I2CDEV_S_ADDR;
transferMCfg.tx_data = &eeprom_addr;
transferMCfg.tx_length = 1;
transferMCfg.rx_data = mac_buf;
transferMCfg.rx_length = MAC_ADDR_SIZE;
transferMCfg.retransmissions_max = 3;
I2C_MasterTransferData(LPC_I2C0, &transferMCfg, I2C_TRANSFER_POLLING);
/** deinitialize I2C0 */
LPC_I2C0->I2CONCLR = I2C_I2CONCLR_I2ENC;
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C0, DISABLE);
}
/*********************************************************************//**
* @brief Initializes the PWMx peripheral corresponding to the specified
* parameters in the PWM_ConfigStruct.
* @param[in] PWMx PWM peripheral, should be LPC_PWM1
* @param[in] PWMTimerCounterMode Timer or Counter mode, should be:
* - PWM_MODE_TIMER: Counter of PWM peripheral is in Timer mode
* - PWM_MODE_COUNTER: Counter of PWM peripheral is in Counter mode
* @param[in] PWM_ConfigStruct Pointer to structure (PWM_TIMERCFG_Type or
* PWM_COUNTERCFG_Type) which will be initialized.
* @return None
* Note: PWM_ConfigStruct pointer will be assigned to corresponding structure
* (PWM_TIMERCFG_Type or PWM_COUNTERCFG_Type) due to PWMTimerCounterMode.
**********************************************************************/
void PWM_Init(LPC_PWM_TypeDef *PWMx, uint32_t PWMTimerCounterMode, void *PWM_ConfigStruct)
{
PWM_TIMERCFG_Type *pTimeCfg;
PWM_COUNTERCFG_Type *pCounterCfg;
uint64_t clkdlycnt;
CHECK_PARAM(PARAM_PWMx(PWMx));
CHECK_PARAM(PARAM_PWM_TC_MODE(PWMTimerCounterMode));
pTimeCfg = (PWM_TIMERCFG_Type *)PWM_ConfigStruct;
pCounterCfg = (PWM_COUNTERCFG_Type *)PWM_ConfigStruct;
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCPWM1, ENABLE);
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_PWM1, CLKPWR_PCLKSEL_CCLK_DIV_4);
// Get peripheral clock of PWM1
clkdlycnt = (uint64_t) CLKPWR_GetPCLK (CLKPWR_PCLKSEL_PWM1);
// Clear all interrupts pending
PWMx->IR = 0xFF & PWM_IR_BITMASK;
PWMx->TCR = 0x00;
PWMx->CTCR = 0x00;
PWMx->MCR = 0x00;
PWMx->CCR = 0x00;
PWMx->PCR = 0x00;
PWMx->LER = 0x00;
if (PWMTimerCounterMode == PWM_MODE_TIMER)
{
CHECK_PARAM(PARAM_PWM_TIMER_PRESCALE(pTimeCfg->PrescaleOption));
/* Absolute prescale value */
if (pTimeCfg->PrescaleOption == PWM_TIMER_PRESCALE_TICKVAL)
{
PWMx->PR = pTimeCfg->PrescaleValue - 1;
}
/* uSecond prescale value */
else
{
clkdlycnt = (clkdlycnt * pTimeCfg->PrescaleValue) / 1000000;
PWMx->PR = ((uint32_t) clkdlycnt) - 1;
}
}
else if (PWMTimerCounterMode == PWM_MODE_COUNTER)
{
CHECK_PARAM(PARAM_PWM_COUNTER_INPUTSEL(pCounterCfg->CountInputSelect));
CHECK_PARAM(PARAM_PWM_COUNTER_EDGE(pCounterCfg->CounterOption));
PWMx->CTCR |= (PWM_CTCR_MODE((uint32_t)pCounterCfg->CounterOption)) \
| (PWM_CTCR_SELECT_INPUT((uint32_t)pCounterCfg->CountInputSelect));
}
}
/********************************************************************//**
* @brief Initializes the I2Cx peripheral with specified parameter.
* @param[in] I2Cx I2C peripheral selected, should be I2C0, I2C1 or I2C2
* @param[in] clockrate Target clock rate value to initialized I2C
* peripheral
* @return None
*********************************************************************/
void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate)
{
//CHECK_PARAM(PARAM_I2Cx(I2Cx));
if (I2Cx==LPC_I2C0)
{
/* Set up clock and power for I2C0 module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C0, ENABLE);
/* As default, peripheral clock for I2C0 module
* is set to FCCLK / 2 */
CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_I2C0, CLKPWR_PCLKSEL_CCLK_DIV_2);
}
else if (I2Cx==LPC_I2C1)
{
/* Set up clock and power for I2C1 module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C1, ENABLE);
/* As default, peripheral clock for I2C1 module
* is set to FCCLK / 2 */
CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_I2C1, CLKPWR_PCLKSEL_CCLK_DIV_2);
}
else if (I2Cx==LPC_I2C2)
{
/* Set up clock and power for I2C2 module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C2, ENABLE);
/* As default, peripheral clock for I2C2 module
* is set to FCCLK / 2 */
CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_I2C2, CLKPWR_PCLKSEL_CCLK_DIV_2);
}
else {
// Up-Support this device
return;
}
/* Set clock rate */
I2C_SetClock(I2Cx, clockrate);
/* Set I2C operation to default */
I2Cx->I2CONCLR = (I2C_I2CONCLR_AAC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_I2ENC);
}
/*********************************************************************//**
* @brief Initial for Watchdog function
* Clock source = RTC ,
* @param[in] ClkSrc Select clock source, should be:
* - WDT_CLKSRC_IRC: Clock source from Internal RC oscillator
* - WDT_CLKSRC_PCLK: Selects the APB peripheral clock (PCLK)
* - WDT_CLKSRC_RTC: Selects the RTC oscillator
* @param[in] WDTMode WDT mode, should be:
* - WDT_MODE_INT_ONLY: Use WDT to generate interrupt only
* - WDT_MODE_RESET: Use WDT to generate interrupt and reset MCU
* @return None
**********************************************************************/
void WDT_Init (WDT_CLK_OPT ClkSrc, WDT_MODE_OPT WDTMode)
{
CHECK_PARAM(PARAM_WDT_CLK_OPT(ClkSrc));
CHECK_PARAM(PARAM_WDT_MODE_OPT(WDTMode));
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_WDT, CLKPWR_PCLKSEL_CCLK_DIV_4);
//Set clock source
LPC_WDT->WDCLKSEL &= ~WDT_WDCLKSEL_MASK;
LPC_WDT->WDCLKSEL |= ClkSrc;
//Set WDT mode
if (WDTMode == WDT_MODE_RESET){
LPC_WDT->WDMOD |= WDT_WDMOD(WDTMode);
}
}
/* dac_init
*
* Initialize the DAC. This must be called once after reset.
*/
void COLD dac_init() {
/* Turn on the PWM and timer peripherals. */
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCPWM1, ENABLE);
CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_PWM1, CLKPWR_PCLKSEL_CCLK_DIV_4);
/* Set up the SSP to communicate with the DAC, and initialize to 0 */
hw_dac_init();
/* ... and LDAC on the PWM peripheral */
LPC_PINCON->PINSEL4 |= (1 << 8);
/* Get the pin set up to produce a low LDAC puslse */
LPC_GPIO2->FIODIR |= (1 << 4);
LPC_GPIO2->FIOCLR = (1 << 4);
/* The PWM peripheral is used to generate LDAC pulses. Set it up,
* but hold it in reset until go time. */
LPC_PWM1->TCR = PWM_TCR_COUNTER_RESET | PWM_TCR_COUNTER_ENABLE;
/* Reset on match channel 0 */
LPC_PWM1->MCR = PWM_MCR_RESET_ON_MATCH(0) | PWM_MCR_INT_ON_MATCH(0);
/* Enable single-edge PWM on channel 5 */
LPC_PWM1->PCR = PWM_PCR_PWMENAn(5);
/* The match registers themselves will be set by dac_start(). */
/* Enable the write-to-DAC interrupt with the highest priority. */
NVIC_SetPriority(PWM1_IRQn, 0);
NVIC_EnableIRQ(PWM1_IRQn);
dac_control.state = DAC_IDLE;
dac_control.irq_do = IRQ_DO_PANIC;
dac_control.count = 0;
dac_current_pps = 0;
dac_control.color_control.word = 0;
delay_line_reset();
dac_control.red_gain = COORD_MAX;
dac_control.green_gain = COORD_MAX;
dac_control.blue_gain = COORD_MAX;
if (hw_dac_16bit) {
memcpy(PWM1_IRQHandler, goto_dac16_handle_irq, goto_dac16_handle_irq_end - goto_dac16_handle_irq);
}
}
/********************************************************************//**
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the UART_ConfigStruct.
* @param[in] SPIx SPI peripheral selected, should be SPI
* @param[in] SPI_ConfigStruct Pointer to a SPI_CFG_Type structure
* that contains the configuration information for the
* specified SPI peripheral.
* @return None
*********************************************************************/
void SPI_Init(SPI_TypeDef *SPIx, SPI_CFG_Type *SPI_ConfigStruct)
{
SPI_PinCFG_Type defaultSPIPinCfg;
uint32_t tmp;
CHECK_PARAM(PARAM_SPIx(SPIx));
if(SPIx == SPI)
{
/* Set up clock and power for UART module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSPI, ENABLE);
/* As default, peripheral clock for UART0 module
* is set to FCCLK / 2 */
CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_SPI, CLKPWR_PCLKSEL_CCLK_DIV_2);
// Set UART0 function pin as default
defaultSPIPinCfg.SCK_Pin = SPI_SCK_P0_15;
defaultSPIPinCfg.SSEL_Pin = SPI_SSEL_P0_16;
defaultSPIPinCfg.MISO_Pin = SPI_MISO_P0_17;
defaultSPIPinCfg.MOSI_Pin = SPI_MOSI_P0_18;
SPI_PinConfig(SPIx, &defaultSPIPinCfg, SPI_ConfigStruct->Mode);
}
// Configure SPI, interrupt is disable as default
tmp = ((SPI_ConfigStruct->CPHA) | (SPI_ConfigStruct->CPOL) \
| (SPI_ConfigStruct->DataOrder) | (SPI_ConfigStruct->Databit) \
| (SPI_ConfigStruct->Mode) | SPI_SPCR_BIT_EN) & SPI_SPCR_BITMASK;
// write back to SPI control register
SPIx->SPCR = tmp;
// Set clock rate for SPI peripheral
SPI_SetClock(SPIx, SPI_ConfigStruct->ClockRate);
// If interrupt flag is set, Write '1' to Clear interrupt flag
if (SPIx->SPINT & SPI_SPINT_INTFLAG)
{
SPIx->SPINT = SPI_SPINT_INTFLAG;
}
}
/********************************************************************//**
* @brief Set WDT time out value and WDT mode
* @param[in] clk_source select Clock source for WDT device
* @param[in] timeout value of time-out for WDT (us)
* @return None
*********************************************************************/
static uint8_t WDT_SetTimeOut (uint8_t clk_source, uint32_t timeout)
{
uint32_t pclk_wdt = 0;
uint32_t tempval = 0;
switch ((WDT_CLK_OPT) clk_source)
{
case WDT_CLKSRC_IRC:
pclk_wdt = 4000000;
// Calculate TC in WDT
tempval = (((pclk_wdt) / WDT_US_INDEX) * (timeout / 4));
// Check if it valid
if ((tempval >= WDT_TIMEOUT_MIN) && (tempval <= WDT_TIMEOUT_MAX))
{
LPC_WDT->WDTC = tempval;
return SUCCESS;
}
break;
case WDT_CLKSRC_PCLK:
// Get WDT clock with CCLK divider = 4
pclk_wdt = SystemCoreClock / 4;
// Calculate TC in WDT
tempval = (((pclk_wdt) / WDT_US_INDEX) * (timeout / 4));
if ((tempval >= WDT_TIMEOUT_MIN) && (tempval <= WDT_TIMEOUT_MAX))
{
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_WDT, CLKPWR_PCLKSEL_CCLK_DIV_4);
LPC_WDT->WDTC = (uint32_t) tempval;
return SUCCESS;
}
// Get WDT clock with CCLK divider = 2
pclk_wdt = SystemCoreClock / 2;
// Calculate TC in WDT
tempval = (((pclk_wdt) / WDT_US_INDEX) * (timeout / 4));
if ((tempval >= WDT_TIMEOUT_MIN) && (tempval <= WDT_TIMEOUT_MAX))
{
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_WDT, CLKPWR_PCLKSEL_CCLK_DIV_2);
LPC_WDT->WDTC = (uint32_t) tempval;
return SUCCESS;
}
// Get WDT clock with CCLK divider = 1
pclk_wdt = SystemCoreClock;
// Calculate TC in WDT
tempval = (((pclk_wdt) / WDT_US_INDEX) * (timeout / 4));
if ((tempval >= WDT_TIMEOUT_MIN) && (tempval <= WDT_TIMEOUT_MAX))
{
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_WDT, CLKPWR_PCLKSEL_CCLK_DIV_1);
LPC_WDT->WDTC = (uint32_t) tempval;
return SUCCESS;
}
break ;
case WDT_CLKSRC_RTC:
pclk_wdt = 32768;
// Calculate TC in WDT
tempval = (((pclk_wdt) / WDT_US_INDEX) * (timeout / 4));
// Check if it valid
if ((tempval >= WDT_TIMEOUT_MIN) && (tempval <= WDT_TIMEOUT_MAX))
{
LPC_WDT->WDTC = (uint32_t) tempval;
return SUCCESS;
}
break;
// Error parameter
default:
break;
}
return ERROR;
}
/*********************************************************************//**
* @brief Initial Timer/Counter device
* Set Clock frequency for Timer
* Set initial configuration for Timer
* @param[in] TIMx Timer selection, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @param[in] TimerCounterMode Timer counter mode, should be:
* - TIM_TIMER_MODE: Timer mode
* - TIM_COUNTER_RISING_MODE: Counter rising mode
* - TIM_COUNTER_FALLING_MODE: Counter falling mode
* - TIM_COUNTER_ANY_MODE:Counter on both edges
* @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type
* that contains the configuration information for the
* specified Timer peripheral.
* @return None
**********************************************************************/
void TIM_Init(LPC_TIM_TypeDef *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct)
{
TIM_TIMERCFG_Type *pTimeCfg;
TIM_COUNTERCFG_Type *pCounterCfg;
CHECK_PARAM(PARAM_TIMx(TIMx));
CHECK_PARAM(PARAM_TIM_MODE_OPT(TimerCounterMode));
//set power
if (TIMx== LPC_TIM0)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM0, ENABLE);
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER0, CLKPWR_PCLKSEL_CCLK_DIV_4);
}
else if (TIMx== LPC_TIM1)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM1, ENABLE);
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER1, CLKPWR_PCLKSEL_CCLK_DIV_4);
}
else if (TIMx== LPC_TIM2)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, ENABLE);
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER2, CLKPWR_PCLKSEL_CCLK_DIV_4);
}
else if (TIMx== LPC_TIM3)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM3, ENABLE);
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER3, CLKPWR_PCLKSEL_CCLK_DIV_4);
}
TIMx->CTCR &= ~TIM_CTCR_MODE_MASK;
TIMx->CTCR |= TimerCounterMode;
TIMx->TC =0;
TIMx->PC =0;
TIMx->PR =0;
TIMx->TCR |= (1<<1); //Reset Counter
TIMx->TCR &= ~(1<<1); //release reset
if (TimerCounterMode == TIM_TIMER_MODE )
{
pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct;
if (pTimeCfg->PrescaleOption == TIM_PRESCALE_TICKVAL)
{
TIMx->PR = pTimeCfg->PrescaleValue -1 ;
}
else
{
TIMx->PR = converUSecToVal (converPtrToTimeNum(TIMx),pTimeCfg->PrescaleValue)-1;
}
}
else
{
pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct;
TIMx->CTCR &= ~TIM_CTCR_INPUT_MASK;
if (pCounterCfg->CountInputSelect == TIM_COUNTER_INCAP1)
TIMx->CCR |= _BIT(2);
}
// Clear interrupt pending
TIMx->IR = 0xFFFFFFFF;
}
void spi_init(){
#ifdef SPI_ENABLED
/*Power: In the PCONP register (Table 46), set bit PCSPI.*/
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCSPI,ENABLE);
/*Clock: In the PCLKSEL0 register (Table 40), set bit PCLK_SPI. In master mode, the
clock must be an even number greater than or equal to 8 (see Section 17.7.4).*/
CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_SPI,CLKPWR_PCLKSEL_CCLK_DIV_4);//default clock
// LPC_SC->PCLKSEL0 |= (1<<16)|(1<<17);//cclk/8
/* SPCCR clock prescale register, master mode min value 8*/
LPC_SPI->SPCCR = 0x8;
/*Pins: The SPI pins are configured using both PINSEL0 (Table 79) and PINSEL1
(Table 80), as well as the PINMODE (Section 8.4) register. PINSEL0[31:30] is used to
configure the SPI CLK pin. PINSEL1[1:0], PINSEL1[3:2] and PINSEL1[5:4] are used
to configure the pins SSEL, MISO and MOSI, respectively.*/
// configure pins
LPC_PINCON->PINSEL1 |= (3<<30); // [P0.15] SCK0
LPC_PINCON->PINSEL1 |= (1<<2 )|(1<<3 ); // [P0.17] MISO0
LPC_PINCON->PINSEL1 |= (1<<4 )|(1<<5 ); // [P0.18] MOSI0
LPC_PINCON->PINSEL0 &= ~(3)<<12; // [P0.6] CS as GPIO
LPC_GPIO0->FIODIR |= PIN_MASK_CS;
LPC_GPIO0->FIOSET |= PIN_MASK_CS; // - set high
//LPC_GPIO2->FIODIR |= PIN_MASK_CS; // [P2.2] CS - set as output [P0.6] SSEL1 - set as output
//LPC_GPIO2->FIOSET |= PIN_MASK_CS; // - set high
//the radio wants MSB, Master mode,CPOL=0 and CPHA=0
LPC_SPI->SPCR|=SPI_MST;// master mode
LPC_SPI->SPCR&=~SPI_LSB; // MSB first,
LPC_SPI->SPCR&=~SPI_CPOL; //clock polarity high
LPC_SPI->SPCR&=~SPI_CPHA; //clock phase to 0
/* 0b111000XX
* ||||||||__ Reserved
* |||||||___ Reserved
* ||||||____ BitEnable --> 0 if 8 bits per transfer. 1 if bits 8:11 specify the amount of bits per transfer (8-16)
* |||||_____ CPHA --> clock phase control. 0-first clock edge of SCK, 1-2nd clock edge
* ||||______ CPOL --> clock polarity - 0 SCK is active.
* |||_______ MSTR --> 0 slave, 1 master
* ||________ LSBF --> least significant bit first.0 is LSBF, 1 is MSBF.
* |_________ SPIE --> Interrupt enable. 1 if active.
* (bits 8-11) When bit 2 of this register is 1, this field controls the number of bits per transfer (8-16. pag 407)
*
*/
NVIC_EnableIRQ(SPI_IRQn);
#ifdef SPI_IN_INTERRUPT_MODE
LPC_SPI->SPCR|=SPI_IE; //enable interrupt if interrupt mode on.
#endif
#endif
#ifdef SSP_ENABLED
ssp_spi_init();
#endif
}
/*********************************************************************//**
* @brief Initial Timer/Counter device
* Set Clock frequency for ADC
* Set initial configuration for ADC
* @param[in] TIMx Timer selection, should be TIM0, TIM1, TIM2, TIM3
* @param[in] TimerCounterMode TIM_MODE_OPT
* @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type
* that contains the configuration information for the
* specified Timer peripheral.
* @return None
**********************************************************************/
void TIM_Init(TIM_TypeDef *TIMx, uint8_t TimerCounterMode, void *TIM_ConfigStruct)
{
TIM_TIMERCFG_Type *pTimeCfg;
TIM_COUNTERCFG_Type *pCounterCfg;
CHECK_PARAM(PARAM_TIMx(TIMx));
CHECK_PARAM(PARAM_TIM_MODE_OPT(TimerCounterMode));
uint32_t timer = TIM_ConverPtrToTimeNum(TIMx) ;
//set power
if (TIMx== TIM0)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM0, ENABLE);
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER0, CLKPWR_PCLKSEL_CCLK_DIV_4);
}
else if (TIMx== TIM1)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM1, ENABLE);
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER1, CLKPWR_PCLKSEL_CCLK_DIV_4);
}
else if (TIMx== TIM2)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, ENABLE);
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER2, CLKPWR_PCLKSEL_CCLK_DIV_4);
}
else if (TIMx== TIM3)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM3, ENABLE);
CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER3, CLKPWR_PCLKSEL_CCLK_DIV_4);
}
TIMx->CCR &= ~TIM_CTCR_MODE_MASK;
TIMx->CCR |= TIM_TIMER_MODE;
TIMx->TC =0;
TIMx->PC =0;
TIMx->PR =0;
if (TimerCounterMode == TIM_TIMER_MODE )
{
pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct;
if (pTimeCfg->PrescaleOption == TIM_PRESCALE_TICKVAL)
{
TIMx->PR = pTimeCfg->PrescaleValue -1 ;
}
else
{
TIMx->PR = TIM_ConverUSecToVal (TIM_ConverPtrToTimeNum(TIMx),pTimeCfg->PrescaleValue)-1;
}
}
else
{
pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct;
TIMx->CCR &= ~TIM_CTCR_INPUT_MASK;
if (pCounterCfg->CountInputSelect == TIM_COUNTER_INCAP1)
TIMx->CCR |= _BIT(2);
//set pin function
PINSEL_ConfigPin((PINSEL_CFG_Type *)&timer_caption_pin[2*timer + pCounterCfg->CountInputSelect]);
}
// Clear interrupt pending
TIMx->IR = 0xFFFFFFFF;
}
