/**
* @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
* @param spi is the base address of SPI module.
* @return Actual SPI bus clock frequency.
*/
uint32_t SPI_GetBusClock(SPI_T *spi)
{
uint32_t u32Div;
uint32_t u32ClkSrc;
/* Get DIVIDER setting */
u32Div = (spi->DIVIDER & SPI_DIVIDER_DIVIDER_Msk) >> SPI_DIVIDER_DIVIDER_Pos;
/* Check clock source of SPI */
if(spi == SPI0)
{
if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0_S_Msk) == CLK_CLKSEL1_SPI0_S_HCLK)
u32ClkSrc = CLK_GetHCLKFreq();
else
u32ClkSrc = CLK_GetPLLClockFreq();
}
else
{
if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1_S_Msk) == CLK_CLKSEL1_SPI1_S_HCLK)
u32ClkSrc = CLK_GetHCLKFreq();
else
u32ClkSrc = CLK_GetPLLClockFreq();
}
if(spi->CNTRL2 & SPI_CNTRL2_BCn_Msk) /* BCn = 1: f_spi = f_spi_clk_src / (DIVIDER + 1) */
{
/* Return SPI bus clock rate */
return (u32ClkSrc / (u32Div + 1));
}
else /* BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */
{
/* Return SPI bus clock rate */
return (u32ClkSrc / ((u32Div + 1) * 2));
}
}
/**
* @brief This function make SPI module be ready to transfer.
* By default, the SPI transfer sequence is MSB first and
* the automatic slave select function is disabled. In
* Slave mode, the u32BusClock must be NULL and the SPI clock
* divider setting will be 0.
* @param spi is the base address of SPI module.
* @param u32MasterSlave decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER)
* @param u32SPIMode decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_03)
* @param u32DataWidth decides the data width of a SPI transaction.
* @param u32BusClock is the expected frequency of SPI bus clock in Hz.
* @return Actual frequency of SPI peripheral clock.
*/
uint32_t SPI_Open(SPI_T *spi,
uint32_t u32MasterSlave,
uint32_t u32SPIMode,
uint32_t u32DataWidth,
uint32_t u32BusClock)
{
uint32_t u32Pclk, u32Div;
// assert if is as slave but bus clock isn't equal 0
//
if(u32DataWidth == 32)
u32DataWidth = 0;
spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_TX_BIT_LEN_Pos) | (u32SPIMode);
u32Pclk = CLK_GetHCLKFreq();
u32Div = 0xffff;
if(u32BusClock !=0 ) {
u32Div = (((u32Pclk / u32BusClock) + 1) >> 1) - 1;
if(u32Div > 0xFFFF)
u32Div = 0xFFFF;
spi->CLKDIV = (spi->CLKDIV & ~0xffff) | u32Div;
} else
/**
* @brief Enable I2C function and set clock divider. I2C clock = PCLK / (4x(divider+1)).
* @param I2cPort: I2C port handler
* u32BusClock: I2C bus clock frequency (Hz)
* @retval None.
*/
void DrvI2C_Init(I2C_T *I2cPort, uint32_t u32BusClock, uint8_t EnableInt)
{
uint32_t divider;
divider = (uint32_t) (((CLK_GetHCLKFreq()*10)/(u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
if((uint32_t)I2cPort == I2C1_BASE)
{
SYS_RESET_IP2(SYS_RST_I2C1); //中:复位I2C模块//en:Reset I2C IP module
APBCLK_ENABLE(CLK_I2C1); //中:使能I2C时钟//en:Enable I2C0 clock
}
else
{
SYS_RESET_IP2(SYS_RST_I2C0); //中:复位I2C模块//en:Reset I2C IP module
APBCLK_ENABLE(CLK_I2C0); //中:使能I2C时钟//en:Enable I2C0 clock
}
I2C_SET_DIVIDER(I2cPort, divider);
if(EnableInt)
{
I2C_ENABLE_I2C_INT(I2cPort);
if((uint32_t)I2cPort == I2C0_BASE)
NVIC_EnableIRQ(I2C0_IRQn);
else if((uint32_t)I2cPort == I2C1_BASE)
NVIC_EnableIRQ(I2C1_IRQn);
}
I2C_ENABLE_I2C(I2cPort);
}
/**
* @brief Get I2C bit rate.
* @param I2cPort: I2C port handler
* @retval I2C Bus Clock Frequency
*/
uint32_t DrvI2C_GetClockFreq(I2C_T *I2cPort)
{
uint32_t divider;
divider = I2cPort->I2CLK;
return ( CLK_GetHCLKFreq() / ((divider+1)<<2) );
}
/**
* @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
* @param spi is the base address of SPI module.
* @return Actual SPI bus clock frequency.
*/
uint32_t SPI_GetBusClock(SPI_T *spi)
{
uint32_t u32Div;
uint32_t u32ApbClock;
u32ApbClock = CLK_GetHCLKFreq();
u32Div = spi->CLKDIV & 0xff;
return (u32ApbClock / (u32Div + 1));
}
void initialize()
{
IO::pinMode(MUX_ADR0_PIN, OUTPUT);
IO::pinMode(MUX_ADR1_PIN, OUTPUT);
IO::pinMode(MUX_ADR2_PIN, OUTPUT);
IO::pinMode(V_IN_PIN, ANALOG_INPUT);
IO::pinMode(OUTPUT_VOLTAGE_MINUS_PIN, ANALOG_INPUT);
IO::pinMode(SMPS_CURRENT_PIN, ANALOG_INPUT);
IO::pinMode(OUTPUT_VOLTAGE_PLUS_PIN, ANALOG_INPUT);
IO::pinMode(DISCHARGE_CURRENT_PIN, ANALOG_INPUT);
IO::pinMode(MUX0_Z_D_PIN, ANALOG_INPUT_DISCHARGE);
IO::digitalWrite(MUX0_Z_D_PIN, 0);
//initialize internal temperature sensor
SYS->TEMPCR |= 1;
//initialize TIMER 1 (mux ADC capacitor discharge)
CLK_EnableModuleClock(TMR1_MODULE);
CLK_SetModuleClock(TMR1_MODULE,CLK_CLKSEL1_TMR1_S_HCLK,CLK_CLKDIV_UART(1));
//TODO: 50kHz ??
TIMER_Open(TIMER1, TIMER_ONESHOT_MODE, 1000000 / ADC_CAPACITOR_DISCHARGE_DELAY_US);
TIMER_EnableInt(TIMER1);
NVIC_EnableIRQ(TMR1_IRQn);
NVIC_SetPriority(TMR1_IRQn, ADC_C_DISCHARGE_IRQ_PRIORITY);
//initialize ADC
//init clock
CLK_EnableModuleClock(ADC_MODULE);
CLK_SetModuleClock(ADC_MODULE, CLK_CLKSEL1_ADC_S_HCLK, CLK_CLKDIV_ADC(CLK_GetHCLKFreq()/ADC_CLOCK_FREQUENCY));
//__HXT/ADC_CLOCK_FREQUENCY));
/* Set the ADC operation mode as burst, input mode as single-end and enable the analog input channel 2 */
ADC_Open(ADC, ADC_ADCR_DIFFEN_SINGLE_END, ADC_ADCR_ADMD_BURST, 0x1 << 2);
ADC_SET_DMOF(ADC, ADC_ADCR_DMOF_UNSIGNED_OUTPUT);
/* Power on ADC module */
ADC_POWER_ON(ADC);
/* clear the A/D interrupt flag for safe */
ADC_CLR_INT_FLAG(ADC, ADC_ADF_INT);
/* Enable the ADC interrupt */
ADC_EnableInt(ADC, ADC_ADF_INT);
NVIC_EnableIRQ(ADC_IRQn);
NVIC_SetPriority(ADC_IRQn, ADC_IRQ_PRIORITY);
current_input_ = 0;
startConversion();
}
/**
* @brief Set the SPI bus clock. Only available in Master mode.
* @param spi is the base address of SPI module.
* @param u32BusClock is the expected frequency of SPI bus clock.
* @return Actual frequency of SPI peripheral clock.
*/
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
{
uint32_t u32Pclk = CLK_GetHCLKFreq();
uint32_t u32Div = 0xffff;
if(u32BusClock !=0 ) {
u32Div = ((u32Pclk / u32BusClock) + 1) - 1;
if(u32Div > 0xFFFF)
u32Div = 0xFFFF;
spi->CLKDIV = (spi->CLKDIV & ~0xffff) | u32Div;
} else
spi->CLKDIV = 0;
return ( u32Pclk / (u32Div+1) );
}
/**
* @brief This function make SPI module be ready to transfer.
* By default, the SPI transfer sequence is MSB first and
* the automatic slave select function is disabled. In
* Slave mode, the u32BusClock must be NULL and the SPI clock
* divider setting will be 0.
* @param spi is the base address of SPI module.
* @param u32MasterSlave decides the SPI module is operating in master mode or in slave mode. Valid values are:
* - \ref SPI_SLAVE
* - \ref SPI_MASTER
* @param u32SPIMode decides the transfer timing. Valid values are:
* - \ref SPI_MODE_0
* - \ref SPI_MODE_1
* - \ref SPI_MODE_2
* - \ref SPI_MODE_3
* @param u32DataWidth decides the data width of a SPI transaction.
* @param u32BusClock is the expected frequency of SPI bus clock in Hz.
* @return Actual frequency of SPI peripheral clock.
*/
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
{
uint32_t u32Pclk, u32Div;
if(u32DataWidth == 32)
u32DataWidth = 0;
spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode);
u32Pclk = CLK_GetHCLKFreq();
u32Div = 0xffff;
if(u32BusClock !=0 ) {
u32Div = ((u32Pclk / u32BusClock) + 1) - 1;
if(u32Div > 0xFFFF)
u32Div = 0xFFFF;
spi->CLKDIV = (spi->CLKDIV & ~0xffff) | u32Div;
} else
spi->CLKDIV = 0;
return ( u32Pclk / (u32Div+1) );
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
unsigned int u32ByteCount;
unsigned int u32PageNumber;
unsigned int u32ProgramFlashAddress = 0;
unsigned int u32VerifyFlashAddress = 0;
unsigned int MidDid;
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
printf("Hello World.\n");
printf("PLL Clock = %d Hz\n", CLK_GetPLLClockFreq());
printf("Core Clock = %d Hz\n\n", CLK_GetHCLKFreq());
printf("+-------------------------------------------------------+\n");
printf("| M451 Series SPI_Flash Sample Code |\n");
printf("+-------------------------------------------------------+\n");
/* Open 7-Seg */
Open_Seven_Segment();
/* Open SPI for Serial Flash */
Open_SPI_Flash();
/* Read MID & DID */
MidDid = SpiFlash_ReadMidDid();
printf("\nMID and DID = %x", MidDid);
/* Erase SPI Flash */
SpiFlash_ChipErase();
printf("\nFlash Erasing... ");
/* Wait ready */
SpiFlash_WaitReady();
printf("Done!");
/* Fill the Source Data and clear Destination Data Buffer */
for(u32ByteCount = 0; u32ByteCount < 256; u32ByteCount++)
{
SrcArray[u32ByteCount] = u32ByteCount;
DestArray[u32ByteCount] = 0;
}
u32ProgramFlashAddress = 0;
u32VerifyFlashAddress = 0;
for(u32PageNumber = 0; u32PageNumber < TEST_NUMBER; u32PageNumber++)
{
printf("\n\nTest Page Number = %d", u32PageNumber);
Show_Seven_Segment(u32PageNumber, 1);
CLK_SysTickDelay(200000);
/*=== Program SPI Flash ===*/
printf("\n Flash Programming... ");
/* Page Program */
SpiFlash_PageProgram(SrcArray, u32ProgramFlashAddress, 256);
SpiFlash_WaitReady();
u32ProgramFlashAddress += 0x100;
printf("Done!");
/*=== Read Back and Compare Data ===*/
printf("\n Flash Verifying... ");
/* Page Read */
SpiFlash_ReadData(DestArray, u32VerifyFlashAddress, 256);
u32VerifyFlashAddress += 0x100;
for(u32ByteCount = 0; u32ByteCount < 256; u32ByteCount++)
{
if(DestArray[u32ByteCount] != u32ByteCount)
{
/* Error */
printf("SPI Flash R/W Fail!");
while(1);
}
}
/* Clear Destination Data Buffer */
for(u32ByteCount = 0; u32ByteCount < 256; u32ByteCount++)
DestArray[u32ByteCount] = 0;
printf("Done!");
}
printf("\n\nSPI Flash Test Ok!");
printf("\n\n");
while(1);
}
/**
* @brief This function make SPI module be ready to transfer.
* By default, the SPI transfer sequence is MSB first and
* the automatic slave select function is disabled. In
* Slave mode, the u32BusClock must be NULL and the SPI clock
* divider setting will be 0.
* @param spi is the base address of SPI module.
* @param u32MasterSlave decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER)
* @param u32SPIMode decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_03)
* @param u32DataWidth decides the data width of a SPI transaction.
* @param u32BusClock is the expected frequency of SPI bus clock in Hz.
* @return Actual frequency of SPI peripheral clock.
* @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
* @note In slave mode, the SPI peripheral clock rate will be set to equal to system clock rate.
* @note If u32BusClock is equal to system clock rate, DIV_ONE will be set to 1.
* So that byte reorder function, byte suspend function and variable clock function must be disabled.
* @note if u32BusClock is larger than system clock rate, the SPI peripheral clock rate will be set to equal to system clock rate.
*/
uint32_t SPI_Open(SPI_T *spi,
uint32_t u32MasterSlave,
uint32_t u32SPIMode,
uint32_t u32DataWidth,
uint32_t u32BusClock)
{
uint32_t u32ClkSrc = 0, u32Div;
if(u32DataWidth == 32)
u32DataWidth = 0;
/* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
spi->CNTRL = u32MasterSlave | (u32DataWidth << SPI_CNTRL_TX_BIT_LEN_Pos) | (u32SPIMode);
/* Set BCn = 1: f_spi = f_spi_clk_src / (DIVIDER + 1) */
spi->CNTRL2 |= SPI_CNTRL2_BCn_Msk;
if(u32MasterSlave == SPI_MASTER)
{
/* Default setting: slave select signal is active low; disable automatic slave select function. */
spi->SSR = SPI_SS_ACTIVE_LOW;
/* Check clock source of SPI */
if(spi == SPI0)
{
if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0_S_Msk) == CLK_CLKSEL1_SPI0_S_HCLK)
u32ClkSrc = CLK_GetHCLKFreq();
else
u32ClkSrc = CLK_GetPLLClockFreq();
}
else
{
if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1_S_Msk) == CLK_CLKSEL1_SPI1_S_HCLK)
u32ClkSrc = CLK_GetHCLKFreq();
else
u32ClkSrc = CLK_GetPLLClockFreq();
}
if(u32BusClock >= u32ClkSrc)
{
/* Set DIVIDER = 0 */
spi->DIVIDER = 0;
/* Return master peripheral clock rate */
return u32ClkSrc;
}
else if(u32BusClock == 0)
{
/* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */
spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk);
/* Set DIVIDER to the maximum value 0xFF */
spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (0xFF << SPI_DIVIDER_DIVIDER_Pos);
/* Return master peripheral clock rate */
return (u32ClkSrc / ((0xFF + 1) * 2));
}
else
{
u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
if(u32Div > 0xFF)
{
/* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */
spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk);
u32Div = (((u32ClkSrc * 10) / (u32BusClock * 2) + 5) / 10) - 1; /* Round to the nearest integer */
if(u32Div > 0xFF)
u32Div = 0xFF;
spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos);
/* Return master peripheral clock rate */
return (u32ClkSrc / ((u32Div + 1) * 2));
}
else
{
spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos);
/* Return master peripheral clock rate */
return (u32ClkSrc / (u32Div + 1));
}
}
}
else /* For slave mode, force the SPI peripheral clock rate to system clock rate. */
{
/* Default setting: slave select signal is low level active. */
spi->SSR = SPI_SSR_SS_LTRIG_Msk;
/* Select HCLK as the clock source of SPI */
if(spi == SPI0)
CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI0_S_Msk)) | CLK_CLKSEL1_SPI0_S_HCLK;
else
CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_SPI1_S_Msk)) | CLK_CLKSEL1_SPI1_S_HCLK;
/* Set DIVIDER = 0 */
spi->DIVIDER = 0;
/* Return slave peripheral clock rate */
return u32ClkSrc;
}
}
/**
* @brief Set the SPI bus clock. Only available in Master mode.
* @param spi is the base address of SPI module.
* @param u32BusClock is the expected frequency of SPI bus clock in Hz.
* @return Actual frequency of SPI peripheral clock.
* @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
* @note If u32BusClock is larger than system clock rate, the SPI peripheral clock rate will be set to equal to system clock rate.
*/
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
{
uint32_t u32ClkSrc;
uint32_t u32Div;
/* Set BCn = 1: f_spi = f_spi_clk_src / (DIVIDER + 1) */
spi->CNTRL2 |= SPI_CNTRL2_BCn_Msk;
/* Check clock source of SPI */
if(spi == SPI0)
{
if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0_S_Msk) == CLK_CLKSEL1_SPI0_S_HCLK)
u32ClkSrc = CLK_GetHCLKFreq();
else
u32ClkSrc = CLK_GetPLLClockFreq();
}
else
{
if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1_S_Msk) == CLK_CLKSEL1_SPI1_S_HCLK)
u32ClkSrc = CLK_GetHCLKFreq();
else
u32ClkSrc = CLK_GetPLLClockFreq();
}
if(u32BusClock >= u32ClkSrc)
{
/* Set DIVIDER = 0 */
spi->DIVIDER = 0;
/* Return master peripheral clock rate */
return u32ClkSrc;
}
else if(u32BusClock == 0)
{
/* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */
spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk);
/* Set DIVIDER to the maximum value 0xFF */
spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (0xFF << SPI_DIVIDER_DIVIDER_Pos);
/* Return master peripheral clock rate */
return (u32ClkSrc / ((0xFF + 1) * 2));
}
else
{
u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
if(u32Div > 0xFF)
{
/* Set BCn = 0: f_spi = f_spi_clk_src / ((DIVIDER + 1) * 2) */
spi->CNTRL2 &= (~SPI_CNTRL2_BCn_Msk);
u32Div = (((u32ClkSrc * 10) / (u32BusClock * 2) + 5) / 10) - 1; /* Round to the nearest integer */
if(u32Div > 0xFF)
u32Div = 0xFF;
spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos);
/* Return master peripheral clock rate */
return (u32ClkSrc / ((u32Div + 1) * 2));
}
else
{
spi->DIVIDER = (spi->DIVIDER & (~SPI_DIVIDER_DIVIDER_Msk)) | (u32Div << SPI_DIVIDER_DIVIDER_Pos);
/* Return master peripheral clock rate */
return (u32ClkSrc / (u32Div + 1));
}
}
}
/*---------------------------------------------------------------------------------------------------------*/
int main()
{
unsigned int u32ByteCount;
unsigned int u32PageNumber;
unsigned int u32ProgramFlashAddress = 0;
unsigned int u32VerifyFlashAddress = 0;
unsigned int MidDid;
PDMA_T *PDMA_CH1, *PDMA_CH2;
// PDMA Channel 1/2 control registers
PDMA_CH1 = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (CH1-1)));
PDMA_CH2 = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (CH2-1)));
/* Initial system */
SYS_Init();
/* Initial UART1 to 115200-8n1 for print message */
UART1_Init();
printf("Hello World.\n");
printf("PLL Clock = %d Hz\n", CLK_GetPLLClockFreq());
printf("Core Clock = %d Hz\n\n", CLK_GetHCLKFreq());
printf("+-------------------------------------------------------+\n");
printf("| Nano100 Series SPI_Flash Sample Code with PDMA |\n");
printf("+-------------------------------------------------------+\n");
/* Open 7-Seg */
Open_Seven_Segment();
/* Open SPI for Serial Flash */
Open_SPI_Flash();
/* Initial PDMA Channels */
Init_PDMA_CH1_for_SPI0_TX((uint32_t)SrcArray);
Init_PDMA_CH2_for_SPI0_RX((uint32_t)DestArray);
/* Enable PDMA IRQ */
NVIC_EnableIRQ(PDMA_IRQn);
/* Read MID & DID */
MidDid = SpiFlash_w_PDMA_ReadMidDid();
printf("\nMID and DID = %x", MidDid);
/* Erase SPI Flash */
SpiFlash_w_PDMA_ChipErase();
printf("\nFlash Erasing... ");
/* Wait ready */
SpiFlash_w_PDMA_WaitReady();
printf("Done!");
/* Fill the Source Data and clear Destination Data Buffer */
for(u32ByteCount=0; u32ByteCount<256; u32ByteCount++)
{
SrcArray[u32ByteCount] = u32ByteCount;
DestArray[u32ByteCount] = 0;
}
u32ProgramFlashAddress = 0;
u32VerifyFlashAddress = 0;
for(u32PageNumber=0; u32PageNumber<TEST_NUMBER; u32PageNumber++)
{
printf("\n\nTest Page Number = %d", u32PageNumber);
Show_Seven_Segment(u32PageNumber,1);
CLK_SysTickDelay(200000);
/*=== Program SPI Flash ===*/
printf("\n Flash Programming... ");
/* Trigger PDMA specified Channel */
PDMA_CH1->CSR |= (PDMA_CSR_TRIG_EN_Msk | PDMA_CSR_PDMACEN_Msk);
/* Page Program */
SpiFlash_w_PDMA_PageProgram(u32ProgramFlashAddress, 256);
SpiFlash_w_PDMA_WaitReady();
u32ProgramFlashAddress += 0x100;
printf("Done!");
/*=== Read Back and Compare Data ===*/
printf("\n Flash Verifying... ");
/* Trigger PDMA specified Channel */
PDMA_CH2->CSR |= (PDMA_CSR_TRIG_EN_Msk | PDMA_CSR_PDMACEN_Msk);
/* Page Read */
SpiFlash_w_PDMA_ReadData(u32VerifyFlashAddress, 256);
u32VerifyFlashAddress += 0x100;
for(u32ByteCount=0; u32ByteCount<256; u32ByteCount++)
{
if(DestArray[u32ByteCount]!=u32ByteCount)
{
/* Error */
printf("\n\nSPI Flash R/W Fail!");
while(1);
}
}
/* Clear Destination Data Buffer */
for(u32ByteCount=0; u32ByteCount<256; u32ByteCount++)
DestArray[u32ByteCount] = 0;
printf("Done!");
}
printf("\n\nSPI Flash with PDMA Test Ok!");
printf("\n\n");
while(1);
}
