{ &gcc_ce2_ahb_m_clk.c, 0x0142 },
{ &gcc_bimc_kpss_axi_m_clk.c, 0x0155 },
{ &ce3_clk.c, 0x0228 },
{ &gcc_ce3_axi_m_clk.c, 0x0229 },
{ &gcc_ce3_ahb_m_clk.c, 0x022a },
),
.c = {
.dbg_name = "rpm_debug_mux",
.ops = &clk_ops_gen_mux,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(rpm_debug_mux.c),
},
};
static struct clk_lookup msm_clocks_rpm_8994[] = {
CLK_LIST(cxo_clk_src),
CLK_LIST(pnoc_clk),
CLK_LIST(ocmemgx_clk),
CLK_LIST(pnoc_a_clk),
CLK_LIST(bimc_clk),
CLK_LIST(bimc_a_clk),
CLK_LIST(cnoc_clk),
CLK_LIST(cnoc_a_clk),
CLK_LIST(gfx3d_clk_src),
CLK_LIST(ocmemgx_a_clk),
CLK_LIST(snoc_clk),
CLK_LIST(snoc_a_clk),
CLK_LIST(bb_clk1),
CLK_LIST(bb_clk1_ao),
CLK_LIST(bb_clk1_pin),
CLK_LIST(bb_clk1_pin_ao),
static struct div_clk byte_clk_src = {
.ops = &fixed_4div_ops,
.data = {
.min_div = 4,
.max_div = 4,
},
.c = {
.parent = &byte_mux_8916.c,
.dbg_name = "byte_clk_src_8916",
.ops = &byte_clk_src_ops,
CLK_INIT(byte_clk_src.c),
},
};
static struct clk_lookup mdss_dsi_pllcc_8916[] = {
CLK_LIST(pixel_clk_src),
CLK_LIST(byte_clk_src),
};
int dsi_pll_clock_register_lpm(struct platform_device *pdev,
struct mdss_pll_resources *pll_res)
{
int rc;
if (!pdev || !pdev->dev.of_node) {
pr_err("Invalid input parameters\n");
return -EINVAL;
}
if (!pll_res || !pll_res->pll_base) {
pr_err("Invalid PLL resources\n");
static struct div_clk dsi_pll1_byte_clk_src = {
.ops = &fixed_4div_ops,
.data = {
.min_div = 4,
.max_div = 4,
},
.c = {
.parent = &dsi_pll1_byte_mux.c,
.dbg_name = "dsi_pll1_byte_clk_src",
.ops = &byte_clk_src_ops,
CLK_INIT(dsi_pll1_byte_clk_src.c),
},
};
static struct clk_lookup dsi_pll0_cc[] = {
CLK_LIST(dsi_pll0_pixel_clk_src),
CLK_LIST(dsi_pll0_byte_clk_src),
};
static struct clk_lookup dsi_pll1_cc[] = {
CLK_LIST(dsi_pll1_pixel_clk_src),
CLK_LIST(dsi_pll1_byte_clk_src),
};
int dsi_pll_clock_register_hpm(struct platform_device *pdev,
struct mdss_pll_resources *pll_res)
{
int rc;
if (!pdev || !pdev->dev.of_node) {
pr_err("Invalid input parameters\n");
{80000000, 0xBB},
{80060000, 0x77},
{160010000, 0xBB},
{160120000, 0x77},
{772930000, 0xBB},
{HDMI_PLL_TMDS_MAX, 0xFF},
},
.c = {
.dbg_name = "hdmi_20nm_vco_clk",
.ops = &hdmi_20nm_vco_clk_ops,
CLK_INIT(hdmi_20nm_vco_clk.c),
},
};
static struct clk_lookup hdmipllcc_8994[] = {
CLK_LIST(hdmi_20nm_vco_clk),
};
int hdmi_20nm_pll_clock_register(struct platform_device *pdev,
struct mdss_pll_resources *pll_res)
{
int rc = -ENOTSUPP;
if (!pll_res || !pll_res->phy_base || !pll_res->pll_base) {
pr_err("Invalide input parameters\n");
return -EPROBE_DEFER;
}
/* Set client data for vco, mux and div clocks */
hdmi_20nm_vco_clk.priv = pll_res;
* axi clock is for the BIMC AXI interface. The AXI clock is 1/2 of
* the BIMC Clock. measure the gcc_bimc_apss_axi_clk.
*/
{&bimc_clk.c, 0x0155},
),
.c = {
.dbg_name = "rpm_debug_mux",
.ops = &clk_ops_gen_mux,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(rpm_debug_mux.c),
},
};
/* Lookup Table */
static struct clk_lookup msm_clocks_rpm[] = {
CLK_LIST(xo_clk_src),
CLK_LIST(xo_a_clk_src),
CLK_LIST(xo_otg_clk),
CLK_LIST(xo_lpm_clk),
CLK_LIST(xo_pil_mss_clk),
CLK_LIST(xo_pil_pronto_clk),
CLK_LIST(xo_wlan_clk),
CLK_LIST(snoc_msmbus_clk),
CLK_LIST(snoc_msmbus_a_clk),
CLK_LIST(pcnoc_msmbus_clk),
CLK_LIST(pcnoc_msmbus_a_clk),
CLK_LIST(bimc_msmbus_clk),
CLK_LIST(bimc_msmbus_a_clk),
CLK_LIST(bimc_acpu_a_clk),
CLK_LIST(pcnoc_keepalive_a_clk),
{ &pcie_0_phy_ldo.c, 0x02c0 },
{ &pcie_1_phy_ldo.c, 0x02c8 },
{ &gcc_gmac0_axi_clk.c, 0x02e5 },
{ &gcc_gmac1_axi_clk.c, 0x02e6 },
),
.c = {
.dbg_name = "gcc_debug_mux",
.ops = &clk_ops_debug_mux,
.flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
CLK_INIT(gcc_debug_mux.c),
},
};
static struct clk_lookup msm_clocks_lookup[] = {
CLK_LIST(gcc_blsp1_uart4_apps_clk),
CLK_LIST(gcc_blsp1_qup2_i2c_apps_clk),
CLK_LIST(gcc_blsp1_ahb_clk),
CLK_LIST(gcc_sdcc1_ahb_clk),
CLK_LIST(gcc_sdcc1_apps_clk),
CLK_LIST(gcc_prng_ahb_clk),
CLK_LIST(pcie_0_phy_ldo),
CLK_LIST(pcie_1_phy_ldo),
CLK_LIST(gcc_pcie_0_aux_clk),
CLK_LIST(gcc_pcie_0_cfg_ahb_clk),
CLK_LIST(gcc_pcie_0_mstr_axi_clk),
CLK_LIST(gcc_pcie_0_pipe_clk),
CLK_LIST(gcc_pcie_0_slv_axi_clk),
CLK_LIST(gcc_pcie_1_aux_clk),
CLK_LIST(gcc_pcie_1_cfg_ahb_clk),
CLK_LIST(gcc_pcie_1_mstr_axi_clk),
.num_parents = 2,
.parents = (struct clk_src[]) {
{&dsi0pll_byte_clk_src.c, 0},
{&dsi0pll_shadow_byte_clk_src.c, 1},
},
.ops = &mdss_byte_mux_ops,
.c = {
.parent = &dsi0pll_byte_clk_src.c,
.dbg_name = "dsi0pll_byte_clk_mux",
.ops = &clk_ops_gen_mux_dsi,
CLK_INIT(dsi0pll_byte_clk_mux.c),
}
};
static struct clk_lookup dsi0_pllcc_20nm[] = {
CLK_LIST(dsi0pll_pixel_clk_mux),
CLK_LIST(dsi0pll_byte_clk_mux),
CLK_LIST(dsi0pll_pixel_clk_src),
CLK_LIST(dsi0pll_byte_clk_src),
CLK_LIST(dsi0pll_fixed_hr_oclk2_div_clk),
CLK_LIST(dsi0pll_bypass_lp_div_mux),
CLK_LIST(dsi0pll_hr_oclk3_div_clk),
CLK_LIST(dsi0pll_indirect_path_div2_clk),
CLK_LIST(dsi0pll_ndiv_clk),
CLK_LIST(dsi0pll_vco_clk),
CLK_LIST(dsi0pll_shadow_pixel_clk_src),
CLK_LIST(dsi0pll_shadow_byte_clk_src),
CLK_LIST(dsi0pll_shadow_fixed_hr_oclk2_div_clk),
CLK_LIST(dsi0pll_shadow_bypass_lp_div_mux),
CLK_LIST(dsi0pll_shadow_hr_oclk3_div_clk),
CLK_LIST(dsi0pll_shadow_indirect_path_div2_clk),
