void serial_setgpio(void)
{
#if (DEBUG_UART_BASE == UART0_BASE_U_VIRTUAL)
UART0_GPIO_INIT();
CLRREG32(A_CPM_CLKGR,CLKGR_STOP_UART0);
#elif (DEBUG_UART_BASE == UART1_BASE_U_VIRTUAL)
UART1_GPIO_INIT();
CLRREG32(A_CPM_CLKGR,CLKGR_STOP_UART1);
#else
#error There are only two serial port!!!
#endif
}
//------------------------------------------------------------------------------
//
// Function: UpdateVoltageLevels
//
// update voltage levels
//
void UpdateVoltageLevels(pCPU_OPP_Settings opp_setting)
{
OMAP_PRCM_GLOBAL_PRM_REGS* pPrcmGblPRM = OALPAtoUA(OMAP_PRCM_GLOBAL_PRM_REGS_PA);
//---------------------------------
// setup voltage processors
//
// setup i2c for smps communication
OUTREG32(&pPrcmGblPRM->PRM_VC_SMPS_SA, BSP_VC_SMPS_SA_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VC_SMPS_VOL_RA, BSP_VC_SMPS_VOL_RA_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VC_SMPS_CMD_RA, BSP_VC_SMPS_CMD_RA_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VC_CH_CONF, BSP_VC_CH_CONF_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VC_I2C_CFG, BSP_PRM_VC_I2C_CFG_INIT);
// set intial voltage levels
OUTREG32(&pPrcmGblPRM->PRM_VC_CMD_VAL_0, (opp_setting->VDD1Init << 24) | BSP_PRM_VC_CMD_VAL_0_INIT );
OUTREG32(&pPrcmGblPRM->PRM_VC_CMD_VAL_1, (opp_setting->VDD2Init << 24) | BSP_PRM_VC_CMD_VAL_1_INIT);
// set PowerIC error offset, gains, and initial voltage
OUTREG32(&pPrcmGblPRM->PRM_VP1_CONFIG, (opp_setting->VDD1Init << 8) | BSP_PRM_VP1_CONFIG_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VP2_CONFIG, (opp_setting->VDD2Init << 8) | BSP_PRM_VP2_CONFIG_INIT);
// set PowerIC slew range
OUTREG32(&pPrcmGblPRM->PRM_VP1_VSTEPMIN, BSP_PRM_VP1_VSTEPMIN_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VP1_VSTEPMAX, BSP_PRM_VP1_VSTEPMAX_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VP2_VSTEPMIN, BSP_PRM_VP2_VSTEPMIN_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VP2_VSTEPMAX, BSP_PRM_VP2_VSTEPMAX_INIT);
// set PowerIC voltage limits and timeout
OUTREG32(&pPrcmGblPRM->PRM_VP1_VLIMITTO, BSP_PRM_VP1_VLIMITTO_INIT);
OUTREG32(&pPrcmGblPRM->PRM_VP2_VLIMITTO, BSP_PRM_VP2_VLIMITTO_INIT);
// enable voltage processor
SETREG32(&pPrcmGblPRM->PRM_VP1_CONFIG, SMPS_VPENABLE);
SETREG32(&pPrcmGblPRM->PRM_VP2_CONFIG, SMPS_VPENABLE);
// enable timeout
SETREG32(&pPrcmGblPRM->PRM_VP1_CONFIG, SMPS_TIMEOUTEN);
SETREG32(&pPrcmGblPRM->PRM_VP2_CONFIG, SMPS_TIMEOUTEN);
// flush commands to smps
SETREG32(&pPrcmGblPRM->PRM_VP1_CONFIG, SMPS_FORCEUPDATE | SMPS_INITVDD);
SETREG32(&pPrcmGblPRM->PRM_VP2_CONFIG, SMPS_FORCEUPDATE | SMPS_INITVDD);
// allow voltage to settle
OALStall(100);
// disable voltage processor
CLRREG32(&pPrcmGblPRM->PRM_VP1_CONFIG, SMPS_VPENABLE | SMPS_FORCEUPDATE | SMPS_INITVDD | SMPS_TIMEOUTEN);
CLRREG32(&pPrcmGblPRM->PRM_VP2_CONFIG, SMPS_VPENABLE | SMPS_FORCEUPDATE | SMPS_INITVDD | SMPS_TIMEOUTEN);
}
void dma_nowait_cpyinit()
{
CLRREG32(A_CPM_CLKGR, ( 1 << 12 ));
SETREG32(A_DMA_DMAC(DMA_CPY_CHANNEL / 6),DMAC_DMA_EN);
OUTREG32(A_DMA_DCKE(DMA_CPY_CHANNEL / 6),(1 << (DMA_CPY_CHANNEL % 6)));//Open channel clock
CLRREG32(A_DMA_DMAC(DMA_CPY_CHANNEL / 6), (DMAC_HALT | DMAC_ADDR_ERR));//Ensure DMAC.AR = 0,DMAC.HLT = 0
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_AR | DCS_HLT | DCS_TT | DCS_INV); // Ensure DCSn.AR = 0, DCSn.HLT = 0, DCSn.TT = 0, DCSn.INV = 0
OUTREG32(A_DMA_DTC(DMA_CPY_CHANNEL), 0);//DTCn = 0
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE);
SETREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_NDES);
}
////////////////////////////////////////////////////
// 功能: 音频初始化
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
static int intr_handler_record_dma(int arg)
{
unsigned int channle = arg - IRQ_DMA_0;
unsigned int group = arg / HALF_DMA_NUM;
#ifdef KPRINTF_DEF
kprintf("recorde interrupt happend\n");
#endif
CLRREG32(A_DMA_DMAC(group), (DMAC_ADDR_ERR | DMAC_HALT) );
CLRREG32(A_DMA_DCS(channle), (DCS_CTE | DCS_CT | DCS_TT | DCS_AR | DCS_HLT));
AdcSetPcmData(); //读出PCM数据
return INT_DONE;
}
void pwm_set_duty(unsigned int chn, unsigned int percent)
{
unsigned int full_cycles;
static unsigned int old_percent=1;
if (percent == 108)
{
OUTREG16(A_TCU_TESR, TCU_TIMER(chn));
SETREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(chn));
return;
}
if (percent > 100)
{
printf("The percent of PWM should be within 100\n");
return;
}
if (percent == 0)
{
CLRREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(chn));
OUTREG16(A_TCU_TECR, TCU_TIMER(chn));
if(old_percent!=0)
{
__gpio_as_output(4*32+20+chn);
__gpio_clear_pin(4*32+20+chn);
}
old_percent=0;
}
else
{
if(old_percent==0)
{
OUTREG32(A_GPIO_PXFUNS(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXSELC(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXPES(4), 1 << (20 + chn));
}
full_cycles = INREG16(A_TCU_TDFR(chn));
CLRREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
OUTREG16(A_TCU_TDHR(chn), full_cycles - (full_cycles * percent) / 110);
OUTREG16(A_TCU_TCNT(chn), 0x0000);
OUTREG16(A_TCU_TESR, TCU_TIMER(chn));
SETREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
old_percent=percent;
}
}
void dma_copy_nowait(void *tar,void *src,int size)
{
int timeout = 0x1000000;
while ((!(INREG32(A_DMA_DCS(DMA_CPY_CHANNEL)) & DCS_TT)) && (timeout--));
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE);
OUTREG32(A_DMA_DSA(DMA_CPY_CHANNEL), PHYSADDR((unsigned long)src));
OUTREG32(A_DMA_DTA(DMA_CPY_CHANNEL), PHYSADDR((unsigned long)tar));
OUTREG32(A_DMA_DTC(DMA_CPY_CHANNEL), size / 32);
OUTREG32(A_DMA_DRT(DMA_CPY_CHANNEL), DRT_AUTO);
OUTREG32(A_DMA_DCM(DMA_CPY_CHANNEL), (DCM_SAI| DCM_DAI | DCM_SP_32BIT | DCM_DP_32BIT | DCM_TSZ_32BYTE));
CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL),(DCS_TT));
SETREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE | DCS_NDES);
}
void JZ_StartTimerEx(int chn, int frequence, void (*handler)())
{
unsigned int match_counter;
if ( (frequence<((OSC_CLOCK / 4) / 0xffff)+1) || (frequence>(OSC_CLOCK / 400)) )
{
printf("The frequence of timer shoud be in [%d,%d]\n",
(((OSC_CLOCK / 4) / 0xffff)+1),((OSC_CLOCK / 400)));
return ;
}
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_TIMER(chn));
OUTREG16(A_TCU_TCSR(chn), TCU_CLK_EXTAL | TCU_CLK_PRESCALE_CLK4);
match_counter = (OSC_CLOCK / 4) / frequence;
OUTREG16(A_TCU_TDFR(chn), match_counter);
OUTREG16(A_TCU_TDHR(chn), match_counter);
OUTREG16(A_TCU_TCNT(chn), 0x0000);
OUTREG32(A_TCU_TFCR, TCU_INTR_FLAG(chn));
OUTREG32(A_TCU_TMCR, TCU_INTR_FLAG(chn));
request_irq(EIRQ_TCU2_BASE + chn, handler, 0);
OUTREG16(A_TCU_TESR, TCU_TIMER(chn));
enable_irq(EIRQ_TCU2_BASE + chn);
}
////////////////////////////////////////////////////
// 功能: 音频初始化
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
static void jz_audio_reset(void)
{
CLRREG32(AIC_CR, AIC_CR_ERPL | AIC_CR_EREC);
SETREG32(AIC_CR, AIC_CR_FLUSH_FIFO);
OUTREG32(AIC_SR, 0x00000000);
}
//-----------------------------------------------------------------------------
BOOL
NAND_LockBlocks(
HANDLE hNand,
UINT blockStart,
UINT blockEnd,
BOOL bLock
)
{
BOOL rc = FALSE;
NandDevice_t *pDevice = (NandDevice_t*)hNand;
UNREFERENCED_PARAMETER(blockEnd);
UNREFERENCED_PARAMETER(blockStart);
if (pDevice == NULL) goto cleanUp;
if (bLock)
{
CLRREG32(&pDevice->pGpmcRegs->GPMC_CONFIG, GPMC_CONFIG_WRITEPROTECT);
}
else
{
SETREG32(&pDevice->pGpmcRegs->GPMC_CONFIG, GPMC_CONFIG_WRITEPROTECT);
}
rc = TRUE;
cleanUp:
return rc;
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//Note:
// frequence=[(OSC_CLOCK / 4) / 0xffff+1,((OSC_CLOCK / 4) / 100)]
// IF OSC_CLOCK=12,000,000 THEN frequence=[190,120000]
// mode: bit0---InitLevel 0--LowLevel 1--HightLevel
// bit1---ShutDown 0--Gracefull 1--Abrutp
void pwm_init(unsigned int chn, unsigned int frequence, unsigned int mode)
{
unsigned int full_counter;
if ((frequence < ((OSC_CLOCK) / 0xffff) + 1) || (frequence > (OSC_CLOCK/100)))
{
printf("The frequence of pwm shoud be in [%d,%d]\n",
(((OSC_CLOCK) / 0xffff)+1), ((OSC_CLOCK/100)) );
return;
}
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_TIMER(chn));
OUTREG32(A_GPIO_PXFUNS(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXSELC(4), 1 << (20 + chn));
OUTREG32(A_GPIO_PXPES(4), 1 << (20 + chn));
OUTREG16(A_TCU_TCSR(chn), TCU_CLK_EXTAL);
full_counter = (OSC_CLOCK) / frequence;
OUTREG16(A_TCU_TDFR(chn), full_counter);
OUTREG16(A_TCU_TDHR(chn), 0x0000);
OUTREG16(A_TCU_TCNT(chn), 0x0000);
OUTREG32(A_TCU_TMSR, TCU_INTR_FLAG(chn));
SETREG32((A_TCU_TCSR(chn)), (mode & 0x3) << 8);
SETREG32((A_TCU_TCSR(chn)), TCSR_PWM_EN);
}
static void enable_tv_detect(bool tv_enable)
{
// disable ACCDET unit before switch the detect way
OUTREG32(ACCDET_CTRL, ACCDET_DISABLE);
OUTREG32(ACCDET_STATE_SWCTRL, 0);
if(tv_enable)
{
}
else
{
// switch analog switch from tv out to mic
OUTREG32(ACCDET_STATE_SWCTRL, ACCDET_SWCTRL_EN);
// init the accdet MIC detect unit
SETREG32(ACCDET_RSTB, MIC_INIT_BIT);
CLRREG32(ACCDET_RSTB, MIC_INIT_BIT);
}
ACCFIX_DEBUG("[accfix]enable_tv_detect:ACCDET_STATE_SWCTRL =%x\n",
INREG32(ACCDET_STATE_SWCTRL));
// enable ACCDET unit
OUTREG32(ACCDET_CTRL, ACCDET_ENABLE);
}
int efuseWrite(UINT32 group, UINT32* pBuf, UINT32 num)
{
int i;
SETREG32(EFUSEC_CFG, EFUSEC_APB);
SETBITVALUE32(EFUSEC_COUNT, EFUSE_COUNT_MASK, EFUSE_COUNT_CFG);
SETBITVALUE32(EFUSEC_PGM_COUNT, EFUSE_PGM_COUNT_MASK, PGM_COUNT_CFG);
SETREG32(EFUSEC_CFG, EFUSEC_PRE_PG);
if (!TestBitValue(EFUSEC_STATUS, EFUSEC_PRE_PG_FIN, EFUSEC_PRE_PG_FIN))
{
return ERROR;
}
for (i = 0; i < num; i++)
{
SETBITVALUE32(EFUSE_GROUP, EFUSE_GP_MASK, group + i);
OUTREG32(EFUSE_PG_VALUE, *(pBuf + i));
SETREG32(EFUSEC_CFG, EFUSEC_PG_EN);
if (!TestBitValue(EFUSEC_STATUS, EFUSEC_PG_STATUS, EFUSEC_PG_STATUS))
{
return ERROR;
}
}
CLRREG32(EFUSEC_CFG, EFUSEC_PRE_PG);
return OK;
}
void JZ_StartTicker(unsigned int TicksPerSec)
{
unsigned int match_counter;
// 1. Start TCU Clock
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
// 2. Disable TCU.
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_SYSTEM_TIMER_CHN));
// 3. Config Clock
OUTREG16(A_TCU_TCSR(TCU_SYSTEM_TIMER_CHN), TCU_CLK_EXTAL | TCU_CLK_PRESCALE_CLK64);
// 4. Config Counter According to Clock
match_counter = (OSC_CLOCK / 64) / TicksPerSec;
OUTREG16(A_TCU_TDFR(TCU_SYSTEM_TIMER_CHN), match_counter);
OUTREG16(A_TCU_TDHR(TCU_SYSTEM_TIMER_CHN), match_counter);
OUTREG16(A_TCU_TCNT(TCU_SYSTEM_TIMER_CHN), 0x0000);
// 5. Clear TCU Intr Flag and Enable Intr
OUTREG32(A_TCU_TFCR, TCU_INTR_FLAG(TCU_SYSTEM_TIMER_CHN));
OUTREG32(A_TCU_TMCR, TCU_INTR_FLAG(TCU_SYSTEM_TIMER_CHN));
// 6. Enable TCU_SYSTEM_TIMER_CHN TCU
OUTREG16(A_TCU_TESR, TCU_TIMER(TCU_SYSTEM_TIMER_CHN));
// 7. Enable IRQ
enable_irq(IRQ_SYSTEM_TIMER);
}
void
OMAP2420DMAContext::HWStopOutputDMA()
{
OMAP2420_DMA_REGS *pDMAReg;
DWORD i, dwVal;
DEBUGMSG(ZONE_FUNCTION, (L"+OMAP2420DMAContext::HWStopOutputDMA()\r\n"));
pDMAReg = m_pOutDMAReg;
// disable the DMA channel link and wait for writing to finish
CLRREG32(&pDMAReg->DMA4_CLNK_CTRL, DMA_CLNK_CTRL_ENABLE_LINK);
dwVal = INREG32(&pDMAReg->DMA4_CCR);
for (i = 0; (i < DMA_SAFETY_LOOP_NUM) && (dwVal & DMA_CCR_WR_ACTIVE); i++)
{
Sleep(1);
dwVal = INREG32(&pDMAReg->DMA4_CCR);
}
// disable DMA on the channel
CLRREG32(&pDMAReg->DMA4_CCR, DMA_CCR_ENABLE);
// clear pending interrupts
OUTREG32(&pDMAReg->DMA4_CSR, INREG32(&pDMAReg->DMA4_CSR));
DMA_ControllerSet(m_hCont, DMACP_L2IntAck, 1 << AUDIO_OUTPUT_DMA_CHANNEL);
// disable the rest of the channel
HWEnableOutputChannel(FALSE);
#if defined(DEBUG)
DumpDMA_LC(L"Stop Output", pDMAReg);
CheckDMAStatus(pDMAReg, FALSE);
#endif
#ifdef PROFILE_MIXER
LARGE_INTEGER liTotalTime;
LARGE_INTEGER liMixerTime;
GetOutputDeviceContext(0)->StopMixerProfiler(&liTotalTime,&liMixerTime);
DEBUGMSG(ZONE_DMA,(L"OMAP2420DMAContext::HWStopOutputDMA: "
L"Total play time: %dms, %dms while mixing\r\n", (DWORD) (liTotalTime.QuadPart), (DWORD) (liMixerTime.QuadPart)
));
#endif
DEBUGMSG(ZONE_FUNCTION, (L"-OMAP2420DMAContext::HWStopOutputDMA()\r\n"));
}
//------------------------------------------------------------------------------
//
// Function: ClockSetup
//
// Initializes clocks and power. Stack based initialization only - no
// global variables allowed.
//
void ClockSetup(pCPU_OPP_Settings opp_setting)
{
OMAP_PRCM_CLOCK_CONTROL_PRM_REGS* pPrcmClkPRM = OALPAtoUA(OMAP_PRCM_CLOCK_CONTROL_PRM_REGS_PA);
OMAP_PRCM_WKUP_CM_REGS* pPrcmWkupCM = OALPAtoUA(OMAP_PRCM_WKUP_CM_REGS_PA);
OMAP_PRCM_PER_CM_REGS* pPrcmPerCM = OALPAtoUA(OMAP_PRCM_PER_CM_REGS_PA);
OMAP_PRCM_CORE_CM_REGS* pPrcmCoreCM = OALPAtoUA(OMAP_PRCM_CORE_CM_REGS_PA);
// setup input system clock
OUTREG32(&pPrcmClkPRM->PRM_CLKSEL, BSP_PRM_CLKSEL);
if(gCPU_family == CPU_FAMILY_DM37XX)
{
Omap37xx_core_dpll_init();
Omap37xx_dpll4_init();
Mpu_dpll_init(opp_setting);
Iva_dpll_init(opp_setting);
Omap37xx_per_dpll_init();
}
else
{
/*Core_dpll_init();
Dpll4_init();
Mpu_dpll_init(opp_setting);
Iva_dpll_init(opp_setting);
Per_dpll_init();*/
}
//--------------------------
// Enable GPTIMER1, GPIO bank 1 (debug led)
SETREG32(&pPrcmWkupCM->CM_FCLKEN_WKUP, (CM_CLKEN_GPT1|CM_CLKEN_GPIO1));
SETREG32(&pPrcmWkupCM->CM_ICLKEN_WKUP, (CM_CLKEN_GPT1|CM_CLKEN_GPIO1));
// Enable UART3 (debug port) and GPIO banks that are accessed in the bootloader
SETREG32(&pPrcmPerCM->CM_FCLKEN_PER, (CM_CLKEN_UART3|CM_CLKEN_GPIO6|CM_CLKEN_GPIO5|CM_CLKEN_GPIO3));
SETREG32(&pPrcmPerCM->CM_ICLKEN_PER, (CM_CLKEN_UART3|CM_CLKEN_GPIO6|CM_CLKEN_GPIO5|CM_CLKEN_GPIO3));
// Disable HS USB OTG interface clock
CLRREG32(&pPrcmCoreCM->CM_ICLKEN1_CORE, CM_CLKEN_HSOTGUSB);
// Disable D2D interface clock
CLRREG32(&pPrcmCoreCM->CM_ICLKEN1_CORE, CM_CLKEN_D2D);
}
//------------------------------------------------------------------------------
//
// External: OmapProfilerStop
//
// stops the profiler.
//
void
OmapProfilerStop(
)
{
CLRREG32(&_pProfTimer->TCLR, GPTIMER_TCLR_ST);
while ((INREG32(&_pProfTimer->TWPS) & GPTIMER_TWPS_TCLR) != 0);
_profilerEnabled = FALSE;
PrcmDeviceEnableClocks(GPTIMER_DEVICE, FALSE);
}
// turn off TVE, turn off DACn...
int jz4755tve_close(void)
{
CLRREG32(A_TV_TVECR, TV_TVECR_DAPD);
#if (TV_VIDEO_OUT_MODE == TV_OUT_MODE_3DIV)
SETREG32(A_TV_TVECR, TV_TVECR_DAPD1 | TV_TVECR_DAPD2| TV_TVECR_DAPD3);
#else
SETREG32(A_TV_TVECR, TV_TVECR_DAPD1 | TV_TVECR_DAPD2);
#endif
SETREG32(A_TV_TVECR, TV_TVECR_SWRST);
}
void dma_nand_set_wait(void *tar,unsigned char src,unsigned int size)
{
unsigned int setdata[16];
unsigned int *ptemp;
ptemp = (unsigned int *)UNCACHE(((unsigned int)(&setdata)+ 31)& (~31));
*ptemp = (unsigned int) ((src << 24) | (src << 16) | (src << 8) | src);
if(((unsigned int)tar < 0xa0000000) && size)
dma_cache_wback_inv((unsigned long)tar, size);
CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE);
OUTREG32(A_DMA_DSA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)ptemp));
OUTREG32(A_DMA_DTA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)tar));
OUTREG32(A_DMA_DTC(DMA_NAND_COPY_CHANNEL), size / 32);
OUTREG32(A_DMA_DRT(DMA_NAND_COPY_CHANNEL), DRT_AUTO);
OUTREG32(A_DMA_DCM(DMA_NAND_COPY_CHANNEL),(DCM_DAI | DCM_SP_32BIT | DCM_DP_32BIT| DCM_TSZ_32BYTE));
CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL),(DCS_TT));
SETREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE | DCS_NDES);
while (!(INREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL)) & DCS_TT));
}
//------------------------------------------------------------------------------
void
PrcmVoltFlushVoltageLevels(
VoltageProcessor_e vp
)
{
switch (vp)
{
case kVoltageProcessor1:
SETREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP1_CONFIG, SMPS_INITVDD | SMPS_FORCEUPDATE);
CLRREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP1_CONFIG, SMPS_INITVDD | SMPS_FORCEUPDATE);
break;
case kVoltageProcessor2:
SETREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP2_CONFIG, SMPS_INITVDD | SMPS_FORCEUPDATE);
CLRREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP2_CONFIG, SMPS_INITVDD | SMPS_FORCEUPDATE);
break;
default:
return;
}
}
void dma_nand_copy_wait(void *tar,void *src,int size)
{
int timeout = 0x1000000;
if(((unsigned int)src < 0xa0000000) && size)
dma_cache_wback_inv((unsigned long)src, size);
if(((unsigned int)tar < 0xa0000000) && size)
dma_cache_wback_inv((unsigned long)tar, size);
CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE);
OUTREG32(A_DMA_DSA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)src));
OUTREG32(A_DMA_DTA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)tar));
OUTREG32(A_DMA_DTC(DMA_NAND_COPY_CHANNEL), size / 32);
OUTREG32(A_DMA_DRT(DMA_NAND_COPY_CHANNEL), DRT_AUTO);
OUTREG32(A_DMA_DCM(DMA_NAND_COPY_CHANNEL), (DCM_SAI| DCM_DAI | DCM_SP_32BIT | DCM_DP_32BIT | DCM_TSZ_32BYTE));
CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL),(DCS_TT));
SETREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE | DCS_NDES);
while ((!(INREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL)) & DCS_TT)) && (timeout--));
}
////////////////////////////////////////////////////
// 功能: 利用DMA播放数据
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
static int intr_handler_playback_dma(int arg)
{
int group,channle;
unsigned int stat,dmac;
//清除DMA标记
#ifdef KPRINTF_DEF
kprintf("play music interrupt happend\n");
#endif
channle = arg - IRQ_DMA_0;
group = (arg - IRQ_DMA_0) / HALF_DMA_NUM;
__dmac_channel_ack_irq( group , channle - group * HALF_DMA_NUM );
stat = INREG32(A_DMA_DCS(channle));
dmac = INREG32(A_DMA_DMAC(group));
#ifdef KPRINTF_DEF
if( stat & DCS_AR )
kprintf("dcs addr error\n");
if( stat & DCS_HLT)
kprintf("dcs halt error\n");
if( dmac & DMAC_ADDR_ERR )
kprintf("dmac addr error\n");
if( dmac & DMAC_HALT )
kprintf("dmac halt error\n");
#endif
if (stat & DCS_TT)
{
CLRREG32(A_DMA_DMAC(group), (DMAC_ADDR_ERR | DMAC_HALT) );
CLRREG32(A_DMA_DCS(channle), (DCS_AR | DCS_HLT | DCS_CTE | DCS_CT | DCS_TT));
DacClearPcmData(); //清空PCM数据
interrupt_count++;
}
else
kdebug(mod_media, PRINT_INFO, "stat & DCS_TT == 0\n");
return INT_DONE;
}
void JZ_InitIdleTimer(void (*handler)(unsigned int))
{
while(IdleTimer_Flag);
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_TIMER(TCU_IDLE_TIMER_CHN));
OUTREG16(A_TCU_TCSR(TCU_IDLE_TIMER_CHN), TCU_CLK_EXTAL | TCU_CLK_PRESCALE_CLK256);
OUTREG16(A_TCU_TDFR(TCU_IDLE_TIMER_CHN), 0xffff);
OUTREG16(A_TCU_TDHR(TCU_IDLE_TIMER_CHN), 0xffff);
OUTREG16(A_TCU_TCNT(TCU_IDLE_TIMER_CHN), 0x0000);
OUTREG32(A_TCU_TFCR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
OUTREG32(A_TCU_TMCR, TCU_INTR_FLAG(TCU_IDLE_TIMER_CHN));
request_irq(EIRQ_TCU2_BASE + TCU_IDLE_TIMER_CHN, handler, 0);
}
int Init_PerformanceCounter(void)
{
CLRREG32(A_CPM_CLKGR, CLKGR_STOP_TCU);
OUTREG16(A_TCU_TECR, TCU_OSTCL);
OUTREG32(A_OST_CSR, TCU_CLK_EXTAL | TCU_CLK_PRESCALE_CLK4);
OUTREG32(A_OST_DR, 0xFFFFFFFF);
OUTREG32(A_OST_CNT, 0);
SETREG32(A_TCU_TESR, TCU_OSTEN);
return ((OSC_CLOCK / 4 ) / 1000000);
}
void switch_asw_to_tv(bool tv_enable)
{
ACCFIX_DEBUG("[accfix]switch analog switch to tv is %d\n",tv_enable);
if(tv_enable)
{
SETREG32(ACCDET_STATE_SWCTRL,TV_DET_BIT);
//hwSPKClassABAnalogSwitchSelect(ACCDET_TV_CHA);
}
else
{
CLRREG32(ACCDET_STATE_SWCTRL,TV_DET_BIT);
//hwSPKClassABAnalogSwitchSelect(ACCDET_MIC_CHA);
}
}
////////////////////////////////////////////////////
// 功能: 触发DMA中断，传送数据
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
void DmaDataToAic(int arg,unsigned int sour_addr, unsigned int len,unsigned char mode)
{
if( !arg )
{ //放音DMA
dma_cache_wback_inv(sour_addr, len);
CLRREG32(AIC_SR, AIC_SR_TUR);
SETREG32(AIC_CR, AIC_CR_ERPL);
dma_start(PLAYBACK_CHANNEL, PHYADDR(sour_addr), PHYADDR(AIC_DR),len,mode);
if (INREG32(AIC_SR) & AIC_SR_TUR)
CLRREG32(AIC_SR, AIC_SR_TUR);
}
else
{ //录音DMA
__dcache_inv((unsigned long)sour_addr, len);
SETREG32(AIC_CR, AIC_CR_EREC);
dma_start(RECORD_CHANNEL, PHYADDR(AIC_DR), PHYADDR(sour_addr),len,mode);
if (INREG32(A_AIC_AICSR) & AICSR_ROR)
CLRREG32(A_AIC_AICSR, AICSR_ROR);
}
}
//////////
// Function Name : OTGDevice_HandleReset
// Function Desctiption : This function handles a USB RESET.
// Input : NONE
// Output : NONE
// Version :
void OTGDevice_HandleReset()
{
OUTREG32(GAHBCFG, MODE_SLAVE|BURST_SINGLE|GBL_INT_UNMASK);
OUTREG32(GINTMSK, OTGINTMASK); // Global Interrupt Mask
OUTREG32(DOEPMSK, CTRL_OUT_EP_SETUP_PHASE_DONE|AHB_ERROR|TRANSFER_DONE); // Out EP Int Mask
OUTREG32(DIEPMSK, INTKN_TXFEMP|NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE); // In EP Int Mask
OUTREG32(GRXFSIZ, RX_FIFO_SIZE); // Rx FIFO Size
OUTREG32(GNPTXFSIZ, NPTX_FIFO_SIZE<<16| NPTX_FIFO_START_ADDR<<0); // Non Periodic Tx FIFO Size
OUTREG32(GRSTCTL, (1<<5)|(1<<4)); // TX and RX FIFO Flush
CLRREG32(PCGCCTL, (1<<0)); //start PHY clock
}
void yuv_copy_nowait_init()
{
int i;
g_desc=(unsigned int*)(((unsigned int)(g_des_space)) | 0xa0000000);
for(i = 0;i < 3;i++)
{
g_desc[i * 8 + 0] = (DES_DAI | DES_SAI | DES_SP_32BIT | DES_DP_32BIT | DES_TSZ_32BIT | DCD_STRIDE_EN | DES_LINK_EN);
g_desc[i * 8 + 5] = DRT_AUTO;
}
g_desc[(--i) * 8 + 0] &= ~(DES_LINK_EN);
CLRREG32(A_CPM_CLKGR, ( 1 << 12 ));
SETREG32(A_DMA_DMAC(DMA_STRIDE_CPY_CHANNEL / 6),DMAC_DMA_EN);
OUTREG32(A_DMA_DCKE(DMA_STRIDE_CPY_CHANNEL / 6),(1 << (DMA_STRIDE_CPY_CHANNEL % 6)));//Open channel clock
CLRREG32(A_DMA_DMAC(DMA_STRIDE_CPY_CHANNEL / 6), (DMAC_HALT | DMAC_ADDR_ERR));//Ensure DMAC.AR = 0,DMAC.HLT = 0
CLRREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL), DCS_AR | DCS_HLT | DCS_TT | DCS_INV); // Ensure DCSn.AR = 0, DCSn.HLT = 0, DCSn.TT = 0, DCSn.INV = 0
OUTREG32(A_DMA_DTC(DMA_STRIDE_CPY_CHANNEL), 0);//DTCn = 0
CLRREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL), DCS_CTE);
CLRREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL), DCS_NDES);
SETREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL), DCS_DES8);
}
//------------------------------------------------------------------------------
//
// Function: OEMSetAlarmTime
//
// Set the RTC alarm time.
//
BOOL OEMSetAlarmTime(SYSTEMTIME *pTime)
{
BOOL rc = FALSE;
S3C2410X_RTC_REG *pRTCReg;
UINT32 irq;
OALMSG(OAL_RTC&&OAL_FUNC, (
L"+OEMSetAlarmTime(%d/%d/%d %d:%d:%d.%03d)\r\n",
pTime->wMonth, pTime->wDay, pTime->wYear, pTime->wHour, pTime->wMinute,
pTime->wSecond, pTime->wMilliseconds
));
if (pTime == NULL) goto cleanUp;
// Get uncached virtual address
pRTCReg = OALPAtoVA(S3C2410X_BASE_REG_PA_RTC, FALSE);
// Enable RTC control
SETREG32(&pRTCReg->RTCCON, 1);
OUTPORT32(&pRTCReg->ALMSEC, TO_BCD(pTime->wSecond));
OUTPORT32(&pRTCReg->ALMMIN, TO_BCD(pTime->wMinute));
OUTPORT32(&pRTCReg->ALMHOUR, TO_BCD(pTime->wHour));
OUTPORT32(&pRTCReg->ALMDATE, TO_BCD(pTime->wDay));
OUTPORT32(&pRTCReg->ALMMON, TO_BCD(pTime->wMonth));
OUTPORT32(&pRTCReg->ALMYEAR, TO_BCD(pTime->wYear - RTC_YEAR_DATUM));
// Enable the RTC alarm interrupt
OUTPORT32(&pRTCReg->RTCALM, 0x7F);
// Disable RTC control.
CLRREG32(&pRTCReg->RTCCON, 1);
// Enable/clear RTC interrupt
irq = IRQ_RTC;
OALIntrDoneIrqs(1, &irq);
// Done
rc = TRUE;
cleanUp:
OALMSG(OAL_RTC&&OAL_FUNC, (L"-OEMSetAlarmTime(rc = %d)\r\n", rc));
return rc;
}
bool platform_com_wait_forever_check(void)
{
#ifdef USBDL_DETECT_VIA_KEY
/* check download key */
if (TRUE == mtk_detect_key(COM_WAIT_KEY)) {
print("%s COM handshake timeout force disable: Key\n", MOD);
return TRUE;
}
#endif
#ifdef USBDL_DETECT_VIA_AT_COMMAND
/* check WDT_NONRST_REG */
if (MTK_WDT_NONRST_DL == (INREG32(MTK_WDT_NONRST_REG) & MTK_WDT_NONRST_DL)) {
print("%s COM handshake timeout force disable: AT Cmd\n", MOD);
CLRREG32(MTK_WDT_NONRST_REG, MTK_WDT_NONRST_DL);
return TRUE;
}
#endif
return FALSE;
}
void yuv_copy_nowait(unsigned int *tar,unsigned int *src,int *t_stride,int *s_stride,int *size,int *line)
{
int i;
while (!(INREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL)) & DCS_CT) ); //error
for(i = 0;i < 3;i++)
{
g_desc[8*i+1] = PHYSADDR(src[i]);
g_desc[8*i+2] = PHYSADDR(tar[i]);
g_desc[8*i+3] = (((unsigned int)&g_desc[8 * (i + 1)] & 0xff0)<<20 ) | ((*(line + i))<<16) | (*(size + i) );
g_desc[8*i+4] = ((*(t_stride + i)) << 16) | (*(s_stride + i));
}
OUTREG32(A_DMA_DDA(DMA_STRIDE_CPY_CHANNEL),PHYSADDR(g_desc));
OUTREG32(A_DMA_DRT(DMA_STRIDE_CPY_CHANNEL), DRT_AUTO);
CLRREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL),(DCS_TT | DCS_CT));
OUTREG32(A_DMA_DDRS(DMA_STRIDE_CPY_CHANNEL / 6), (1 << (DMA_STRIDE_CPY_CHANNEL % 6)));//add
SETREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL), DCS_CTE);
}
