/**
* Cleanup reconfig
*
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieTopologyCleanUpReconfigCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_CORE_0101_STRUCT D0F0xE4_CORE_0101;
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyCleanUpReconfigCZ Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
D0F0xE4_CORE_0101.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0101_ADDRESS),
Pcie
);
D0F0xE4_CORE_0101.Field.CONFIG_XFER_MODE = 0x1;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0101_ADDRESS),
D0F0xE4_CORE_0101.Value,
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyCleanUpReconfigCZ Exit\n");
}
/**
* Init core registers.
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieEarlyCoreInitCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
UINTN Index;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitCZ Enter\n");
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
for (Index = 0; Index < CoreInitTableCZ.Length; Index++) {
UINT32 Value;
Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (CoreId, CoreInitTableCZ.Table[Index].Reg),
Pcie
);
Value &= (~CoreInitTableCZ.Table[Index].Mask);
Value |= CoreInitTableCZ.Table[Index].Data;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (CoreId, CoreInitTableCZ.Table[Index].Reg),
Value,
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitCZ Exit\n");
}
}
/**
* Common Core Init
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieCommonCoreInit (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
UINTN Index;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n");
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
for (Index = 0; Index < sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY); Index++) {
UINT32 Value;
Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (CoreId, CoreInitTable[Index].Reg),
Pcie
);
Value &= (~CoreInitTable[Index].Mask);
Value |= CoreInitTable[Index].Data;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (CoreId, CoreInitTable[Index].Reg),
Value,
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Exit\n");
}
}
/**
* Lanes enable/disable control
*
* @param[in] Control Lane control action
* @param[in] LaneBitMap Core lanes bitmap
* @param[in] Wrapper Pointer to Wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyLaneControlCZ (
IN LANE_CONTROL Control,
IN UINT32 LaneBitMap,
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_CORE_0129_STRUCT D0F0xE4_CORE_0129;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyLaneControlCZ Enter\n");
D0F0xE4_CORE_0129.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0129_ADDRESS),
Pcie
);
if (Control == EnableLanes) {
D0F0xE4_CORE_0129.Value |= LaneBitMap;
} else if (Control == DisableLanes) {
D0F0xE4_CORE_0129.Value &= (~LaneBitMap);
}
D0F0xE4_CORE_0129.Value &= ((1 << Wrapper->NumberOfLanes) - 1);
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0129_ADDRESS),
D0F0xE4_CORE_0129.Value,
TRUE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyLaneControlCZ Exit\n");
}
/**
* Init core registers.
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieEarlyCoreInitTN (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
UINTN Index;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Enter\n");
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
for (Index = 0; Index < CoreInitTableTN.Length; Index++) {
UINT32 Value;
Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg),
Pcie
);
Value &= (~CoreInitTableTN.Table[Index].Mask);
Value |= CoreInitTableTN.Table[Index].Data;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg),
Value,
FALSE,
Pcie
);
}
if (GnbBuildOptionsTN.CfgLinkBwNotificationEn == FALSE) {
PcieRegisterRMW (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_00C1_ADDRESS),
D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK,
0 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET,
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Exit\n");
}
}
VOID
STATIC
PcieTopologySelectMasterPllCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
OUT BOOLEAN *ConfigChanged,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_CORE_0118_STRUCT D0F0xE4_CORE_0118;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPllCZ Enter\n");
D0F0xE4_CORE_0118.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0118_ADDRESS),
Pcie
);
//
// CZ PCIE master pll always select PHY0 (0 <= lane <= 7)
//
if (Wrapper->MasterPll == GNB_PCIE_MASTERPLL_A) {
D0F0xE4_CORE_0118.Field.MASTER_PCIE_PLL_SELECT = 0x0;
} else {
D0F0xE4_CORE_0118.Field.MASTER_PCIE_PLL_SELECT = 0x1;
}
if (ConfigChanged != NULL) {
*ConfigChanged = (D0F0xE4_CORE_0118.Field.MASTER_PCIE_PLL_SELECT == 0) ? FALSE : TRUE;
}
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0118_ADDRESS),
D0F0xE4_CORE_0118.Value,
FALSE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPllCZ Exit\n");
}
/**
* Prepare for reconfiguration
*
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyPrepareForReconfig (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
UINT8 CoreId;
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
0xf,
FALSE,
Pcie
);
}
D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0;
D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
}
}
VOID
PcieAcsCapabilityWrapperEnableV4 (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAcsCapabilityWrapperEnableV4 Enter\n");
if (!PcieLibIsPcieWrapper (Wrapper)) {
return;
}
//Step 1, Enable the ACS capability strap, which add ACS capability pointer to the PCIE extend capability list
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_00B0_ADDRESS),
D0F0xE4_CORE_00B0_Bitfield_6_6_OFFSET,
D0F0xE4_CORE_00B0_Bitfield_6_6_WIDTH,
0x1,
TRUE,
Pcie
);
}
//Step 2, Enable ACS capabilities strap, including sub-items, in WRP
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0000_ADDRESS),
D0F0xE4_WRAP_0000_Bitfield_24_24_MASK | D0F0xE4_WRAP_0000_Bitfield_25_25_MASK | D0F0xE4_WRAP_0000_Bitfield_26_26_MASK,
(0x1 << D0F0xE4_WRAP_0000_Bitfield_24_24_OFFSET) | (0x1 << D0F0xE4_WRAP_0000_Bitfield_25_25_OFFSET) | (0x1 << D0F0xE4_WRAP_0000_Bitfield_26_26_OFFSET),
TRUE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAcsCapabilityWrapperEnableV4 Exit\n");
}
VOID
PcieLockRegisters (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS),
D0F0xE4_CORE_0010_HwInitWrLock_OFFSET,
D0F0xE4_CORE_0010_HwInitWrLock_WIDTH,
0x1,
TRUE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n");
}
VOID
STATIC
PcieTopologyApplyLaneMuxCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT32 Index;
UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorArrayCZ)];
UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorArrayCZ)];
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMuxCZ Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
LibAmdMemCopy (
&TxLaneMuxSelectorArray[0],
&LaneMuxSelectorArrayCZ[0],
sizeof (LaneMuxSelectorArrayCZ),
GnbLibGetHeader (Pcie)
);
LibAmdMemCopy (
&RxLaneMuxSelectorArray[0],
&LaneMuxSelectorArrayCZ[0],
sizeof (LaneMuxSelectorArrayCZ),
GnbLibGetHeader (Pcie)
);
EngineList = PcieConfigGetChildEngine (Wrapper);
while (EngineList != NULL) {
if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
UINT32 CoreLaneBitmap;
UINT32 PifLaneBitmap;
UINT8 CurrentCoreLane;
UINT8 CurrentPifLane;
CoreLaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_CORE_ALLOC, 0, EngineList);
PifLaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, EngineList);
IDS_HDT_CONSOLE (GNB_TRACE, "CoreLaneBitmap - %x, CurrentPifLane - %x\n", CoreLaneBitmap, PifLaneBitmap);
while (CoreLaneBitmap != 0) {
CurrentCoreLane = LibAmdBitScanForward (CoreLaneBitmap);
CurrentPifLane = LibAmdBitScanForward (PifLaneBitmap);
if (TxLaneMuxSelectorArray[CurrentPifLane] != CurrentCoreLane) {
TxLaneMuxSelectorArray[PcieTopologyLocateMuxIndexCZ (TxLaneMuxSelectorArray, CurrentCoreLane)] = TxLaneMuxSelectorArray[CurrentPifLane];
TxLaneMuxSelectorArray[CurrentPifLane] = CurrentCoreLane;
}
if (RxLaneMuxSelectorArray[CurrentCoreLane] != CurrentPifLane) {
RxLaneMuxSelectorArray[PcieTopologyLocateMuxIndexCZ (RxLaneMuxSelectorArray, CurrentPifLane)] = RxLaneMuxSelectorArray[CurrentCoreLane];
RxLaneMuxSelectorArray[CurrentCoreLane] = CurrentPifLane;
}
CoreLaneBitmap &= (~ (1 << CurrentCoreLane));
PifLaneBitmap &= (~ (1 << CurrentPifLane));
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
for (Index = 0; Index < 2; ++Index) {
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0121_ADDRESS + Index),
((UINT32 *) TxLaneMuxSelectorArray) [Index],
FALSE,
Pcie
);
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0125_ADDRESS + Index),
((UINT32 *) RxLaneMuxSelectorArray) [Index],
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMuxCZ Exit\n");
}
VOID
PcieLinkInitHotplug (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxF0xE4_xB5_STRUCT DxF0xE4_xB5;
if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) {
DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie);
DxF0xE4_xB5.Field.LcEhpRxPhyCmd = 0x3;
DxF0xE4_xB5.Field.LcEhpTxPhyCmd = 0x3;
DxF0xE4_xB5.Field.LcEnhancedHotPlugEn = 0x1;
PciePortRegisterWrite (
Engine,
DxF0xE4_xB5_ADDRESS,
DxF0xE4_xB5.Value,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET,
D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH,
0x5,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET,
D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH,
0x1,
TRUE,
Pcie
);
}
if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
GnbLibPciRMW (
Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS,
AccessS3SaveWidth32,
0xffffffff,
1 << DxF0x6C_HotplugCapable_OFFSET,
GnbLibGetHeader (Pcie)
);
PciePortRegisterWriteField (
Engine,
DxF0xE4_x20_ADDRESS,
DxF0xE4_x20_TxFlushTlpDis_OFFSET,
DxF0xE4_x20_TxFlushTlpDis_WIDTH,
0x0,
TRUE,
Pcie
);
PciePortRegisterWriteField (
Engine,
DxF0xE4_x70_ADDRESS,
DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET,
DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH,
0x1,
FALSE,
Pcie
);
}
}
/**
* Pcie TxPreset loading sequence
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieEarlyWrapperTxPresetLoadingSequenceCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 Pif;
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyWrapperTxPresetLoadingSequenceCZ Enter\n");
// Step 1: program TX preset value of PCIE_WRAPPER:PSX80/81_WRP_BIF_LANE_EQUALIZATION_CNTL to 0x7 ( from h/w default 0xF )
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0050_ADDRESS),
D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlDsPortTxPreset_MASK | D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlUsPortTxPreset_MASK,
(7 << D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlDsPortTxPreset_OFFSET) | (7 << D0F0xE4_WRAP_0050_StrapBifPcieLaneEqCntlUsPortTxPreset_OFFSET),
TRUE,
Pcie
);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_BEFORE_TXPRESET_LOADING, Pcie, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
// Step 2: program TOGGLESTRAP bit of PCIE_WRAPPER:PSX80/81_BIF_SWRST_COMMAND_1 to 0x1
PcieRegisterRMW (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0103_ADDRESS),
D0F0xE4_CORE_0103_Togglestrap_MASK,
(1 << D0F0xE4_CORE_0103_Togglestrap_OFFSET),
TRUE,
Pcie
);
// Wait for ~50ns
GnbLibStall (1, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
// program TOGGLESTRAP bit of PCIE_WRAPPER:PSX80/81_BIF_SWRST_COMMAND_1 to 0x0
PcieRegisterRMW (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0103_ADDRESS),
D0F0xE4_CORE_0103_Togglestrap_MASK,
(0 << D0F0xE4_CORE_0103_Togglestrap_OFFSET),
TRUE,
Pcie
);
}
for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
// Step 3: program TXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_TX_CTRL to 0x1 ( from h/w default 0x2 )
// program RXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_RX_CTRL to 0x1 ( from h/w default 0x2 )
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
D0F0xE4_PIF_0008_TxpwrInInit_MASK,
(1 << D0F0xE4_PIF_0008_TxpwrInInit_OFFSET),
TRUE,
Pcie
);
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
D0F0xE4_PIF_000A_RxpwrInInit_MASK,
(1 << D0F0xE4_PIF_000A_RxpwrInInit_OFFSET),
TRUE,
Pcie
);
// Wait for ~1ns
GnbLibStall (1, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
//Step 5: program TXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_TX_CTRL back to 0x2
// program RXPWR_IN_INIT bit of PCIE_WRAPPER:PSX80/81_PIF0_RX_CTRL back to 0x2
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
D0F0xE4_PIF_0008_TxpwrInInit_MASK,
(2 << D0F0xE4_PIF_0008_TxpwrInInit_OFFSET),
TRUE,
Pcie
);
PcieRegisterRMW (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
D0F0xE4_PIF_000A_RxpwrInInit_MASK,
(2 << D0F0xE4_PIF_000A_RxpwrInInit_OFFSET),
TRUE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyWrapperTxPresetLoadingSequenceCZ Exit\n");
}
VOID
STATIC
PcieHwInitPowerGatingCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 Pif;
UINT32 Value;
D0F0xE4_PIF_0004_STRUCT D0F0xE4_PIF_0004;
D0F0xE4_PIF_0008_STRUCT D0F0xE4_PIF_0008;
D0F0xE4_PIF_000A_STRUCT D0F0xE4_PIF_000A;
D0F0xE4_CORE_012A_STRUCT D0F0xE4_CORE_012A;
D0F0xE4_CORE_012C_STRUCT D0F0xE4_CORE_012C;
D0F0xE4_CORE_012D_STRUCT D0F0xE4_CORE_012D;
GNB_BUILD_OPTIONS_CZ *GnbBuildOptionData;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieHwInitPowerGatingCZ Enter\n");
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, GnbLibGetHeader (Pcie));
ASSERT (GnbBuildOptionData != NULL);
Value = 0x0;
if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingL1Pg) == PcieHwInitPwrGatingL1Pg) {
Value = 0x1;
}
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_003D_ADDRESS),
D0F0xE4_CORE_003D_LC_L1_POWER_GATING_EN_OFFSET,
D0F0xE4_CORE_003D_LC_L1_POWER_GATING_EN_WIDTH,
Value,
TRUE,
Pcie
);
for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
D0F0xE4_PIF_0008.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
Pcie
);
D0F0xE4_PIF_000A.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
Pcie
);
D0F0xE4_PIF_0008.Field.TxpwrInOff = GnbBuildOptionData->CfgPcieTxpwrInOff;
D0F0xE4_PIF_000A.Field.RxpwrInOff = GnbBuildOptionData->CfgPcieRxpwrInOff;
D0F0xE4_PIF_000A.Field.RxEiDetInPs2Degrade = 0x0;
D0F0xE4_PIF_0008.Field.TxpwrGatingInL1 = 0x0;
D0F0xE4_PIF_000A.Field.RxpwrGatingInL1 = 0x0;
if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingL1Pg) == PcieHwInitPwrGatingL1Pg) {
D0F0xE4_PIF_0008.Field.TxpwrGatingInL1 = 0x1;
D0F0xE4_PIF_000A.Field.RxpwrGatingInL1 = 0x1;
}
D0F0xE4_PIF_0008.Field.TxpwrGatingInUnused = 0x0;
D0F0xE4_PIF_000A.Field.RxpwrGatingInUnused = 0x0;
if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingOffPg) == PcieHwInitPwrGatingOffPg) {
D0F0xE4_PIF_0008.Field.TxpwrGatingInUnused = 0x1;
D0F0xE4_PIF_000A.Field.RxpwrGatingInUnused = 0x1;
}
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS),
D0F0xE4_PIF_0008.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS),
D0F0xE4_PIF_000A.Value,
TRUE,
Pcie
);
D0F0xE4_PIF_0004.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0004_ADDRESS),
Pcie
);
D0F0xE4_PIF_0004.Field.PifDegradePwrPllMode = 0x0;
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0004_ADDRESS),
D0F0xE4_PIF_0004.Value,
TRUE,
Pcie
);
}
D0F0xE4_CORE_012A.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012A_ADDRESS),
Pcie
);
D0F0xE4_CORE_012C.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012C_ADDRESS),
Pcie
);
D0F0xE4_CORE_012D.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012D_ADDRESS),
Pcie
);
D0F0xE4_CORE_012A.Field.LMLaneDegrade0 = 1;
D0F0xE4_CORE_012A.Field.LMLaneDegrade1 = 1;
D0F0xE4_CORE_012A.Field.LMLaneDegrade2 = 1;
D0F0xE4_CORE_012A.Field.LMLaneDegrade3 = 1;
D0F0xE4_CORE_012C.Field.LMLaneUnused0 = 1;
D0F0xE4_CORE_012C.Field.LMLaneUnused1 = 1;
D0F0xE4_CORE_012C.Field.LMLaneUnused2 = 1;
D0F0xE4_CORE_012D.Field.LMLaneUnused3 = 1;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012A_ADDRESS),
D0F0xE4_CORE_012A.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012C_ADDRESS),
D0F0xE4_CORE_012C.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012D_ADDRESS),
D0F0xE4_CORE_012D.Value,
TRUE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieHwInitPowerGatingCZ Exit\n");
}
VOID
PciePwrClockGating (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011;
D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012;
D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014;
D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015;
D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016;
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n");
D0F0xE4_WRAP_8014.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8015.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8011.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
Pcie
);
if (Wrapper->Features.ClkGating == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.RcvrDetClkEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f;
D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f;
D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1;
D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0;
D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f;
D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1;
}
if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1;
}
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
D0F0xE4_WRAP_8014.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
D0F0xE4_WRAP_8015.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
D0F0xE4_WRAP_8012.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
D0F0xE4_WRAP_8011.Value,
TRUE,
Pcie
);
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
0xf,
TRUE,
Pcie
);
}
if (Wrapper->Features.LclkGating == 0x1) {
D0F0xE4_WRAP_8016.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1;
D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
D0F0xE4_WRAP_8016.Value,
TRUE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n");
}
/**
* Execute/clean up reconfiguration
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieTopologyExecuteReconfigCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_CORE_0101_STRUCT D0F0xE4_CORE_0101;
PCIe_SILICON_CONFIG *Silicon;
DEV_OBJECT DevObject;
UINT32 SmuArg[6];
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigCZ Enter\n");
D0F0xE4_CORE_0101.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
Pcie
);
D0F0xE4_CORE_0101.Field.RECONFIGURE_EN = 0x1;
D0F0xE4_CORE_0101.Field.RESET_PERIOD = 0x2;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
D0F0xE4_CORE_0101.Value,
FALSE,
Pcie
);
Silicon = PcieConfigGetParentSilicon (Wrapper);
DevObject.StdHeader = GnbLibGetHeader (Pcie);
DevObject.GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie));
DevObject.DevPciAddress.AddressValue = Silicon->Address.AddressValue;
LibAmdMemFill (SmuArg, 0x00, sizeof (SmuArg), GnbLibGetHeader (Pcie));
SmuArg [0] = Wrapper->WrapId;
GnbSmuServiceRequestV8 (
&DevObject,
SMC_MSG_RECONFIGURE_SB,
SmuArg,
0
);
D0F0xE4_CORE_0101.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
Pcie
);
D0F0xE4_CORE_0101.Field.RECONFIGURE_EN = 0x0;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
D0F0xE4_CORE_0101.Value,
FALSE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigCZ Exit\n");
}
}
VOID
STATIC
PcieLinkInitHotplugCZ (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxFxxE4_xB5_STRUCT DxFxxE4_xB5;
UINT32 Value;
if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) {
DxFxxE4_xB5.Value = PciePortRegisterRead (Engine, DxFxxE4_xB5_ADDRESS, Pcie);
DxFxxE4_xB5.Field.LcEhpRxPhyCmd = 0x3;
DxFxxE4_xB5.Field.LcEhpTxPhyCmd = 0x3;
DxFxxE4_xB5.Field.LcEnhancedHotPlugEn = 0x1;
DxFxxE4_xB5.Field.LcRcvrDetEnOverride = 0;
PciePortRegisterWrite (
Engine,
DxFxxE4_xB5_ADDRESS,
DxFxxE4_xB5.Value,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET,
D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH,
0x5,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0118_ADDRESS),
D0F0xE4_CORE_0118_RCVR_DET_CLK_ENABLE_OFFSET,
D0F0xE4_CORE_0118_RCVR_DET_CLK_ENABLE_WIDTH,
0x1,
TRUE,
Pcie
);
}
if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
GnbLibPciRMW (
Engine->Type.Port.Address.AddressValue | DxFxx6C_ADDRESS,
AccessS3SaveWidth32,
0xffffffff,
1 << DxFxx6C_HotplugCapable_OFFSET,
GnbLibGetHeader (Pcie)
);
PciePortRegisterWriteField (
Engine,
DxFxxE4_x20_ADDRESS,
DxFxxE4_x20_TxFlushTlpDis_OFFSET,
DxFxxE4_x20_TxFlushTlpDis_WIDTH,
0x0,
TRUE,
Pcie
);
PciePortRegisterWriteField (
Engine,
DxFxxE4_x70_ADDRESS,
DxFxxE4_x70_RxRcbCplTimeoutMode_OFFSET,
DxFxxE4_x70_RxRcbCplTimeoutMode_WIDTH,
0x1,
FALSE,
Pcie
);
}
if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) {
Value = 1;
} else {
Value = 0;
}
PciePortRegisterWriteField (
Engine,
DxFxxE4_x10_ADDRESS,
DxFxxE4_x10_NativePmeEn_OFFSET,
DxFxxE4_x10_NativePmeEn_WIDTH,
Value,
TRUE,
Pcie
);
}
VOID
STATIC
PcieEarlyPortInitCallbackCZ (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackCZ Enter\n");
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
PciePortProgramRegisterTable (PortInitEarlyTableCZ.Table, PortInitEarlyTableCZ.Length, Engine, FALSE, Pcie);
IDS_OPTION_HOOK (IDS_GNB_EQUAL_PRESET, Engine, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie);
PcieSetLinkWidthCap (Engine, Pcie);
PcieCompletionTimeout (Engine, Pcie);
PcieLinkSetSlotCap (Engine, Pcie);
PcieLinkInitHotplugCZ (Engine, Pcie);
//Move EXTENDED_FMT_SUPPORTED stting from Mid to here.
PciePortRegisterRMW (
Engine,
DxFxxE4_xC1_ADDRESS,
DxFxxE4_xC1_StrapE2EPrefixEn_MASK | DxFxxE4_xC1_StrapExtendedFmtSupported_MASK,
(1 << DxFxxE4_xC1_StrapE2EPrefixEn_OFFSET) | (1 << DxFxxE4_xC1_StrapExtendedFmtSupported_OFFSET),
FALSE,
Pcie
);
if (Engine->Type.Port.PortData.PortPresent == PortDisabled ||
(Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent &&
Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced &&
Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) {
ASSERT (!PcieConfigIsSbPcieEngine (Engine));
//
// Pass endpoint status in scratch
//
PciePortRegisterRMW (
Engine,
DxFxxE4_x01_ADDRESS,
0x1,
0x1,
FALSE,
Pcie
);
PcieTrainingSetPortStateV2 (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
if (PcieConfigIsSbPcieEngine (Engine)) {
PcieTrainingSetPortStateV2 (Engine, LinkStateTrainingSuccess, FALSE, Pcie);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_001C_ADDRESS),
D0F0xE4_CORE_001C_TX_ATOMIC_OPS_DISABLE_OFFSET,
D0F0xE4_CORE_001C_TX_ATOMIC_OPS_DISABLE_WIDTH,
0x1,
TRUE,
Pcie
);
}
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieTrainingSetPortStateV2 (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
}
IDS_OPTION_HOOK (IDS_GNB_GEN1_LOOPBACK, Engine, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackCZ Exit\n");
}
