static int
hwpstate_get_info_from_acpi_perf(device_t dev, device_t perf_dev)
{
struct hwpstate_softc *sc;
struct cf_setting *perf_set;
struct hwpstate_setting *hwpstate_set;
int count, error, i;
perf_set = malloc(MAX_SETTINGS * sizeof(*perf_set), M_TEMP, M_NOWAIT);
if (perf_set == NULL) {
HWPSTATE_DEBUG(dev, "nomem\n");
return (ENOMEM);
}
/*
* Fetch settings from acpi_perf.
* Now it is attached, and has info only flag.
*/
count = MAX_SETTINGS;
error = CPUFREQ_DRV_SETTINGS(perf_dev, perf_set, &count);
if (error) {
HWPSTATE_DEBUG(dev, "error: CPUFREQ_DRV_SETTINGS.\n");
goto out;
}
sc = device_get_softc(dev);
sc->cfnum = count;
hwpstate_set = sc->hwpstate_settings;
for (i = 0; i < count; i++) {
if (i == perf_set[i].spec[0]) {
hwpstate_set[i].pstate_id = i;
hwpstate_set[i].freq = perf_set[i].freq;
hwpstate_set[i].volts = perf_set[i].volts;
hwpstate_set[i].power = perf_set[i].power;
hwpstate_set[i].lat = perf_set[i].lat;
} else {
HWPSTATE_DEBUG(dev, "ACPI _PSS object mismatch.\n");
error = ENXIO;
goto out;
}
}
out:
if (perf_set)
free(perf_set, M_TEMP);
return (error);
}
static int
pn_decode_acpi(device_t dev, device_t perf_dev)
{
int i, j, n;
uint64_t status;
uint32_t ctrl;
u_int cpuid;
u_int regs[4];
struct pn_softc *sc;
struct powernow_state state;
struct cf_setting sets[POWERNOW_MAX_STATES];
int count = POWERNOW_MAX_STATES;
int type;
int rv;
if (perf_dev == NULL)
return (ENXIO);
rv = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count);
if (rv)
return (ENXIO);
rv = CPUFREQ_DRV_TYPE(perf_dev, &type);
if (rv || (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
return (ENXIO);
sc = device_get_softc(dev);
do_cpuid(0x80000001, regs);
cpuid = regs[0];
if ((cpuid & 0xfff) == 0x760)
sc->errata |= A0_ERRATA;
ctrl = 0;
sc->sgtc = 0;
for (n = 0, i = 0; i < count; ++i) {
ctrl = sets[i].spec[PX_SPEC_CONTROL];
switch (sc->pn_type) {
case PN7_TYPE:
state.fid = ACPI_PN7_CTRL_TO_FID(ctrl);
state.vid = ACPI_PN7_CTRL_TO_VID(ctrl);
if ((sc->errata & A0_ERRATA) &&
(pn7_fid_to_mult[state.fid] % 10) == 5)
continue;
state.freq = 100 * pn7_fid_to_mult[state.fid] * sc->fsb;
break;
case PN8_TYPE:
state.fid = ACPI_PN8_CTRL_TO_FID(ctrl);
state.vid = ACPI_PN8_CTRL_TO_VID(ctrl);
state.freq = 100 * pn8_fid_to_mult[state.fid] * sc->fsb;
break;
}
state.power = sets[i].power;
j = n;
while (j > 0 && sc->powernow_states[j - 1].freq < state.freq) {
memcpy(&sc->powernow_states[j],
&sc->powernow_states[j - 1],
sizeof(struct powernow_state));
--j;
}
memcpy(&sc->powernow_states[j], &state,
sizeof(struct powernow_state));
++n;
}
sc->powernow_max_states = n;
state = sc->powernow_states[0];
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
switch (sc->pn_type) {
case PN7_TYPE:
sc->sgtc = ACPI_PN7_CTRL_TO_SGTC(ctrl);
/*
* XXX Some bios forget the max frequency!
* This maybe indicates we have the wrong tables. Therefore,
* don't implement a quirk, but fallback to BIOS legacy
* tables instead.
*/
if (PN7_STA_MFID(status) != state.fid) {
device_printf(dev, "ACPI MAX frequency not found\n");
return (EINVAL);
}
break;
case PN8_TYPE:
sc->vst = ACPI_PN8_CTRL_TO_VST(ctrl),
sc->mvs = ACPI_PN8_CTRL_TO_MVS(ctrl),
sc->pll = ACPI_PN8_CTRL_TO_PLL(ctrl),
sc->rvo = ACPI_PN8_CTRL_TO_RVO(ctrl),
sc->irt = ACPI_PN8_CTRL_TO_IRT(ctrl);
sc->low = 0; /* XXX */
/*
* powernow k8 supports only one low frequency.
*/
if (sc->powernow_max_states >= 2 &&
(sc->powernow_states[sc->powernow_max_states - 2].fid < 8))
return (EINVAL);
break;
}
return (0);
}
