BOOL CPU_SPI_Xaction_Start(const SPI_CONFIGURATION& Configuration)
{
if (Configuration.SPI_mod >= TOTAL_SPI_PORT) return FALSE;
LPC_SSP_T *spi = SPI_REG(Configuration.SPI_mod);
int Bits, Mode;
// Configure options and clock
Bits = (Configuration.MD_16bits) ? 16 : 8;
Mode = (Configuration.MSK_IDLE) ? 2 : 0; // ToDo: Check
Mode |= (!Configuration.MSK_SampleEdge) ? 1 : 0;
SPI_Config(spi, Bits, Mode, 0);
SPI_Frequency(spi, (1000 * Configuration.Clock_RateKHz));
// I/O setup
GPIO_PIN msk, miso, mosi;
CPU_SPI_GetPins(Configuration.SPI_mod, msk, miso, mosi);
UINT32 alternate = 0x252; // AF5 = SPI1/SPI2
if (Configuration.SPI_mod == 2) alternate = 0x262; // AF6 = SPI3, speed = 2 (50MHz)
CPU_GPIO_DisablePin(msk, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin(miso, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin(mosi, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
// CS setup
CPU_GPIO_EnableOutputPin(Configuration.DeviceCS, Configuration.CS_Active);
if(Configuration.CS_Setup_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled(Configuration.CS_Setup_uSecs);
}
return TRUE;
}
BOOL I2C_Internal_Initialize()
{
NATIVE_PROFILE_HAL_PROCESSOR_I2C();
if (!(RCC->APB1ENR & RCC_APB1ENR_I2CxEN)) { // only once
currentI2CXAction = NULL;
currentI2CUnit = NULL;
CPU_GPIO_DisablePin( I2Cx_SDA_Pin, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_3 ); // open drain
CPU_GPIO_DisablePin( I2Cx_SCL_Pin, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_3 ); // open drain
RCC->APB1ENR |= RCC_APB1ENR_I2CxEN; // enable I2C clock
RCC->APB1RSTR = RCC_APB1RSTR_I2CxRST; // reset I2C peripheral
RCC->APB1RSTR = 0;
I2Cx->CR2 = SYSTEM_APB1_CLOCK_HZ / 1000000; // APB1 clock in MHz
I2Cx->CCR = (SYSTEM_APB1_CLOCK_HZ / 1000 / 2 - 1) / 100 + 1; // 100KHz
I2Cx->TRISE = SYSTEM_APB1_CLOCK_HZ / (1000 * 1000) + 1; // 1ns;
I2Cx->OAR1 = 0x4000; // init address register
I2Cx->CR1 = I2C_CR1_PE; // enable peripheral
CPU_INTC_ActivateInterrupt(I2Cx_EV_IRQn, STM32_I2C_EV_Interrupt, 0);
CPU_INTC_ActivateInterrupt(I2Cx_ER_IRQn, STM32_I2C_ER_Interrupt, 0);
}
return TRUE;
}
void LPC24XX_USART_Driver::ProtectPins ( int ComPortNum, BOOL On )
{
ASSERT(LPC24XX_USART_Driver::IsValidPortNum(ComPortNum));
static BOOL COM1_PinsProtected = TRUE; // start out doing work on first unprotect
static BOOL COM2_PinsProtected = TRUE; // start out doing work on first unprotect
static BOOL COM3_PinsProtected = TRUE; // start out doing work on first unprotect
static BOOL COM4_PinsProtected = TRUE; // start out doing work on first unprotect
GLOBAL_LOCK(irq);
UINT32 SER_TXD;
UINT32 SER_RXD;
BOOL* PinsProtected;
switch(ComPortNum)
{
case c_COM1: SER_TXD = LPC24XX_USART::c_SER1_TXD; SER_RXD = LPC24XX_USART::c_SER1_RXD; PinsProtected = &COM1_PinsProtected; break;
case c_COM2: SER_TXD = LPC24XX_USART::c_SER2_TXD; SER_RXD = LPC24XX_USART::c_SER2_RXD; PinsProtected = &COM2_PinsProtected; break;
case c_COM3: SER_TXD = LPC24XX_USART::c_SER3_TXD; SER_RXD = LPC24XX_USART::c_SER3_RXD; PinsProtected = &COM3_PinsProtected; break;
case c_COM4: SER_TXD = LPC24XX_USART::c_SER4_TXD; SER_RXD = LPC24XX_USART::c_SER4_RXD; PinsProtected = &COM4_PinsProtected; break;
default: return;
}
if (On)
{
if(!*PinsProtected)
{
*PinsProtected = TRUE;
TxBufferEmptyInterruptEnable( ComPortNum, FALSE );
// TODO Add config for uart pin protected state
CPU_GPIO_EnableOutputPin( SER_TXD, RESISTOR_DISABLED );
RxBufferFullInterruptEnable( ComPortNum, FALSE );
// TODO Add config for uart pin protected state
CPU_GPIO_EnableOutputPin( SER_RXD, RESISTOR_DISABLED );
}
}
else
{
if(*PinsProtected)
{
*PinsProtected = FALSE;
// Connect pin to UART
CPU_GPIO_DisablePin( SER_TXD, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
// Connect pin to UART
CPU_GPIO_DisablePin( SER_RXD, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
TxBufferEmptyInterruptEnable( ComPortNum, TRUE );
RxBufferFullInterruptEnable( ComPortNum, TRUE );
}
}
}
BOOL LPC178X_I2C_Driver::Initialize()
{
#if 0
LPC178X_I2C& I2C = LPC178X::I2C();
g_LPC178X_I2C_Driver.m_currentXAction = NULL;
g_LPC178X_I2C_Driver.m_currentXActionUnit = NULL;
CPU_GPIO_DisablePin( LPC178X_I2C::c_I2C_SDA, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC178X_I2C::c_I2C_SCL, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1 );
CPU_INTC_ActivateInterrupt(NVIC_TO_INTC(I2C0_IRQn), ISR, NULL );
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C0, ENABLE);
/* Set I2C operation to default */
I2C.I2CONCLR = (I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_I2ENC);
// enable the I2c module
I2C.I2CONSET = LPC178X_I2C::I2EN;
// set the Subordinate address
I2C.I2ADR = 0x7E;
#endif
return TRUE;
}
//--//
BOOL PXA271_SPI_Driver::Initialize()
{
//SPI 0 and SPI 1 is not initialized as we don't know what the connection is.Only SPI 2 is initialized as it is dedicated to the Zigbee chip.
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[2].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_3);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[2].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_3);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[2].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_3);
return TRUE;
}
BOOL LPC24XX_SPI_Driver::Initialize()
{
// allow peripheral control of pins
CPU_GPIO_DisablePin( LPC24XX_SPI::c_SPI0_SCLK, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_3);
CPU_GPIO_DisablePin( LPC24XX_SPI::c_SPI0_MOSI, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_3);
CPU_GPIO_DisablePin( LPC24XX_SPI::c_SPI0_MISO, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_3);
return TRUE;
}
void LPC24XX_DAC_Driver::Initialize( UINT32 SampleFrequencyHz )
{
//I'm leaving PCLK_DAC in PCLKSEL0 to the DEFAULT value (00)
//SET PINSEL1 to DAC
CPU_GPIO_DisablePin( LPC24XX_DAC::c_DAC_AOUT, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_2 );
//Init the SampleBuffer as empty.
g_LPC24XX_DAC_Driver.nextFrameWrite = 0;
g_LPC24XX_DAC_Driver.nextSampleRead = DAC_FRAME_BUFFER_SIZE_SAMPLES;
g_LPC24XX_DAC_Driver.nextFrameRead = DAC_FRAME_BUFFERS_NUM;
g_LPC24XX_DAC_Driver.SampleCount = 0;
g_LPC24XX_DAC_Driver.FrameCount = 0;
for(int i =0; i<DAC_FRAME_BUFFERS_NUM; i++)
g_LPC24XX_DAC_Driver.SamplesInFrame[i]=0;
//Set Sample output lenght
UINT32 SampleTimeInUsecs = 1000000/SampleFrequencyHz;
UINT32 CycleTimeInNanosecs = 1000000000/SYSTEM_CLOCK_HZ;
g_LPC24XX_DAC_Driver.SampleTimeInCycles = SampleTimeInUsecs * 1000 / CycleTimeInNanosecs;
/*
debug_printf("SampleTime= %dus, SYSTEM_CLOCK_HZ=%dHz (1 cycle = %dns)\r\n",SampleTimeInUsecs,SYSTEM_CLOCK_HZ,CycleTimeInNanosecs);
debug_printf("SampleTime= %dcycles = %dus * 1000 / %dns\r\n",g_LPC24XX_DAC_Driver.SampleTimeInCycles,SampleTimeInUsecs,CycleTimeInNanosecs);
*/
LPC24XX_DAC& DAC = LPC24XX::DAC();
//set the OUTPUT value at half scale
DAC.DACR = 0x7FC0;
}
BOOL CPU_SPI_Xaction_Start( const SPI_CONFIGURATION& Configuration )
{
NATIVE_PROFILE_HAL_PROCESSOR_SPI();
if (Configuration.SPI_mod >= STM32F4_SPI_MODS) return FALSE;
// CS setup
CPU_GPIO_EnableOutputPin( Configuration.DeviceCS, Configuration.CS_Active );
if(Configuration.CS_Setup_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled( Configuration.CS_Setup_uSecs );
}
// I/O setup
GPIO_PIN msk, miso, mosi;
CPU_SPI_GetPins(Configuration.SPI_mod, msk, miso, mosi);
UINT32 alternate = 0x252; // AF5 = SPI1/SPI2
if (Configuration.SPI_mod == 2) alternate = 0x262; // AF6 = SPI3, speed = 2 (50MHz)
CPU_GPIO_DisablePin( msk, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin( miso, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin( mosi, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
switch (Configuration.SPI_mod) {
case 0: RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; break; // enable SPI1 clock
case 1: RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; break; // enable SPI2 clock
case 2: RCC->APB1ENR |= RCC_APB1ENR_SPI3EN; break; // enable SPI3 clock
}
ptr_SPI_TypeDef spi = g_STM32_Spi_Port[Configuration.SPI_mod];
// set mode bits
UINT32 cr1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR | SPI_CR1_SPE;
if (Configuration.MD_16bits) cr1 |= SPI_CR1_DFF;
if (Configuration.MSK_IDLE) cr1 |= SPI_CR1_CPOL | SPI_CR1_CPHA;
if (!Configuration.MSK_SampleEdge) cr1 ^= SPI_CR1_CPHA; // toggle phase
// set clock prescaler
UINT32 clock = SYSTEM_APB2_CLOCK_HZ / 2000; // SPI1 on APB2
if (Configuration.SPI_mod != 0) clock = SYSTEM_APB1_CLOCK_HZ / 2000; // SPI2/3 on APB1
if (clock > Configuration.Clock_RateKHz << 3) {
clock >>= 4;
cr1 |= SPI_CR1_BR_2;
}
void PWM_Stop(PWM_CHANNEL channel, GPIO_PIN pin)
{
UINT16 ccer = TIM5->CCER;
ccer &= ~(TIM_CCER_CC1E << (4 * channel));
TIM5->CCER = ccer; // disable output
CPU_GPIO_DisablePin( pin, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY );
if ((ccer & (TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) == 0) { // idle
TIM5->CR1 &= ~TIM_CR1_CEN; // stop timer
}
}
BOOL AT91_TSADCC_Driver::Initialize(GPIO_INTERRUPT_SERVICE_ROUTINE touchIsrProc)
{
UINT32 i;
UINT32 dwValue;
struct AT91S_TSADC *pTSADC = (struct AT91S_TSADC *)AT91C_BASE_TSADCC;
AT91_PMC &pmc = AT91::PMC();
/* Selected as TSADCC pins */
for(i = 0; i < NO_PIN; i++)
{
CPU_GPIO_DisablePin( c_TSADCC[i], RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1);
}
pmc.EnablePeriphClock(AT91C_ID_TSADCC);
dwValue = (SYSTEM_PERIPHERAL_CLOCK_HZ/(ADC_CLOCK * 2)) - 1;
if(dwValue > 0X3F) // Saturation
dwValue = 0x3F;
//debug_printf("dwValue :%d\r\n", dwValue);
pTSADC->TSADC_MR = (AT91C_TSADC_TSAMOD_TS_ONLY_MODE |
AT91C_TSADC_PENDET |
(dwValue << 8) |
AT91C_TSADC_SLEEP |
STARTUP_TIME << 16 |
PEN_DEBOUNCE_TIME << 28);
pTSADC->TSADC_TSR = SAMPLE_AND_HOLD_TIME << 24;
pTSADC->TSADC_TRGR = AT91C_TSADC_TRGMOD_NO_TRIGGER;
pTSADC->TSADC_IER = AT91C_TSADC_PENCNT;
CPU_INTC_ActivateInterrupt( AT91C_ID_TSADCC, TSADCC_ISR, NULL);
for (i = 0; i<SAMPLE_NB; i++)
{
g_AT91_TSADCC_Driver.m_stiX_Samples[i] = 0;
g_AT91_TSADCC_Driver.m_stiY_Samples[i] = 0;
}
g_AT91_TSADCC_Driver.m_sdwSampleIndex = 0;
g_AT91_TSADCC_Driver.m_sdwSampleNo = 0;
g_AT91_TSADCC_Driver.m_siX_SampleSum = 0;
g_AT91_TSADCC_Driver.m_siY_SampleSum = 0;
g_AT91_TSADCC_Driver.m_TipState = 0;
g_AT91_TSADCC_Driver.m_UnCalX = 0;
g_AT91_TSADCC_Driver.m_UnCalY = 0;
g_AT91_TSADCC_Driver.m_touchIsrProc = touchIsrProc;
//debug_printf("AT91_TSADCC_Driver::Initialize called\r\n");
return TRUE;
}
BOOL PWM_Start(PWM_CHANNEL channel, GPIO_PIN pin)
{
CPU_GPIO_DisablePin( pin, RESISTOR_DISABLED, 1, GPIO_ALT_MODE_1 );
UINT16 enBit = TIM_CCER_CC1E << (4 * channel);
TIM5->CCER |= enBit; // enable output
UINT16 cr1 = TIM5->CR1;
if ((cr1 & TIM_CR1_CEN) == 0) { // timer stopped
TIM5->EGR = TIM_EGR_UG; // enforce register update
TIM5->CR1 = cr1 | TIM_CR1_CEN; // start timer
}
return TRUE;
}
void PWM_Stop(PWM_CHANNEL* channel, GPIO_PIN* pin, UINT32 count)
{
UINT16 ccer = TIM5->CCER;
for (int i = 0; i < count; i++) {
ccer &= ~(TIM_CCER_CC1E << (4 * channel[i]));
}
TIM5->CCER = ccer; // disable outputs
for (int i = 0; i < count; i++) {
CPU_GPIO_DisablePin( pin[i], RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY );
}
if ((ccer & (TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) == 0) { // idle
TIM5->CR1 &= ~TIM_CR1_CEN; // stop timer
}
}
BOOL AD_Initialize( ANALOG_CHANNEL channel, INT32 precisionInBits )
{
if (!(RCC->APB2ENR & RCC_APB2ENR_ADCxEN)) { // not yet initialized
RCC->APB2ENR |= RCC_APB2ENR_ADCxEN; // enable AD clock
ADC->CCR = 0; // ADCCLK = PB2CLK / 2;
ADCx->SQR1 = 0; // 1 conversion
ADCx->CR1 = 0;
ADCx->CR2 = ADC_CR2_ADON; // AD on
ADCx->SMPR1 = 0x01249249 * STM32F2_AD_SAMPLE_TIME;
ADCx->SMPR2 = 0x09249249 * STM32F2_AD_SAMPLE_TIME;
}
// set pin as analog input
CPU_GPIO_DisablePin(AD_GetPinForChannel(channel), RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1);
return TRUE;
}
BOOL PWM_Start(PWM_CHANNEL* channel, GPIO_PIN* pin, UINT32 count)
{
UINT16 enBits = 0;
for (int i = 0; i < count; i++) {
CPU_GPIO_DisablePin( pin[i], RESISTOR_DISABLED, 1, GPIO_ALT_MODE_1 );
enBits |= TIM_CCER_CC1E << (4 * channel[i]);
}
TIM5->CCER |= enBits; // enable outputs
UINT16 cr1 = TIM5->CR1;
if ((cr1 & TIM_CR1_CEN) == 0) { // timer stopped
TIM5->EGR = TIM_EGR_UG; // enforce register update
TIM5->CR1 = cr1 | TIM_CR1_CEN; // start timer
}
return TRUE;
}
BOOL AT91_SPI_Driver::Xaction_Start(const SPI_CONFIGURATION &Configuration)
{
NATIVE_PROFILE_HAL_PROCESSOR_SPI();
if(!g_AT91_SPI_Driver.m_Enabled[Configuration.SPI_mod])
{
g_AT91_SPI_Driver.m_Enabled[Configuration.SPI_mod] = TRUE;
UINT32 index = Configuration.SPI_mod;
AT91_SPI &spi = AT91::SPI(index);
// make sure we didn't start one in the middle of an existing transaction
/* if( spi.SPI_SR & AT91_SPI::SPI_SR_SPIENS )
{
lcd_printf("\fSPI Collision 1\r\n");
hal_printf("\fSPI Collision 1\r\n");
HARD_BREAKPOINT();
return FALSE;
}*/
if(Configuration.SPI_mod == 0)
{
//Alterate GPIO pins to periphal pins
CPU_GPIO_DisablePin(AT91_SPI0_SCLK, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1);
CPU_GPIO_DisablePin(AT91_SPI0_MOSI, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1);
CPU_GPIO_DisablePin(AT91_SPI0_MISO, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1);
// if (Configuration.DeviceCS == AT91_SPI0_NSS)
// CPU_GPIO_DisablePin(AT91_SPI0_NSS, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1);
}
#if defined(PLATFORM_ARM_SAM9261_ANY)
else
{
//Alterate GPIO pins to periphal pins
CPU_GPIO_DisablePin(AT91_SPI1_SCLK, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1);
CPU_GPIO_DisablePin(AT91_SPI1_MOSI, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1);
CPU_GPIO_DisablePin(AT91_SPI1_MISO, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1);
// we don't implement the NSS/CS function in th SPI core.
// if (Configuration.DeviceCS == AT91_SPI1_NSS)
// CPU_GPIO_DisablePin(AT91_SPI1_NSS, RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1);
}
#elif defined(PLATFORM_ARM_SAM7X_ANY)
else
{
BOOL AT91_Analog_Driver::Initialize( ANALOG_CHANNEL channel, INT32 precisionInBits )
{
if(channel >= ANALOG_MAX_PINS)
return FALSE;
AT91_PMC &pmc = AT91::PMC();
pmc.EnablePeriphClock(AT91C_ID_TSADCC);
if(channel >= 0 && channel <= ANALOG_MAX_PINS)
{
pmc.EnablePeriphClock(AT91C_ID_PIOA);
pmc.EnablePeriphClock(AT91C_ID_PIOD);
CPU_GPIO_DisablePin(AnalogPinTable[channel], RESISTOR_DISABLED, 0, GPIO_ALT_MODE_1);
}
else
{
return CLR_E_PIN_UNAVAILABLE;
}
TOUCHSCREEN_ADC_CONTROLLER_CHANNEL_SELECT = (1 << channel);//AnalogChannelTable[channel]); // Selects the channel in the register
// Explanation of the TOUCHSCREEN_ADC_CONTROLLER_MODE_REGISTER
//
// PENDET: Pen Detect Selection
// 0: Disable the Touch screen pins as analog inputs
// 1: enable the Touch screen pins as analog inputs
//
// PRESCAL: Prescaler Rate Selection
// ADCCLK = MCK / ( (PRESCAL+1) * 2 ) <-- MCK = 100 MHz
//
// SHTIM: Sample & Hold Time for ADC Channels
// Programming 0 for SHTIM gives a Sample & Hold Time equal to (2/ADCCLK).
// Sample & Hold Time = (SHTIM+1) / ADCCLK
TOUCHSCREEN_ADC_CONTROLLER_MODE_REGISTER = (1 << 6) /*PENDET*/| (63 << 8) /*PRESCAL*/ | (0xf << 24) /*SHTIM*/;
TOUCHSCREEN_ADC_CONTROLLER_TRIGGER_REGISTER = 6;
return TRUE;
}
BOOL MC9328MXL_SPI_Driver::Xaction_Start( const SPI_CONFIGURATION& Configuration )
{
NATIVE_PROFILE_HAL_PROCESSOR_SPI();
if(!g_MC9328MXL_SPI_Driver.m_Enabled[Configuration.SPI_mod])
{
g_MC9328MXL_SPI_Driver.m_Enabled[Configuration.SPI_mod] = TRUE;
UINT32 index = Configuration.SPI_mod;
MC9328MXL_SPI & SPI = MC9328MXL::SPI(index);
// make sure we didn't start one in the middle of an existing transaction
if( SPI.CONTROLREG & SPI.CONTROLREG_SPIEN )
{
lcd_printf("\fSPI Collision 1\r\n");
hal_printf("\fSPI Collision 1\r\n");
HARD_BREAKPOINT();
return FALSE;
}
// first build the mode register
SPI.CONTROLREG = MC9328MXL_SPI::ConfigurationToMode( Configuration );
// LCD Controller needs to have Pulse mode enabled
#if (HARDWARE_BOARD_TYPE >= HARDWARE_BOARD_i_MXS_DEMO_REV_V1_2)
if(Configuration.DeviceCS == MC9328MXL_SPI::c_SPI1_SS)
{
SPI.PERIODREG = 2;
SPI.CONTROLREG |= MC9328MXL_SPI::CONTROLREG_SSCTL_PULSE; // Pulse SS between bursts
// set the SSPOL to active lo as it is force at the ConfigurationMOde to not trigger SS for other SPI operation
SPI.CONTROLREG &= (~MC9328MXL_SPI::CONTROLREG_SSPOL_HIGH); // Pulse SS between bursts
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_SS,RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY);
}
#endif
SPI.CONTROLREG |= MC9328MXL_SPI::CONTROLREG_SPIEN;
#if (SPI_LOOP_BACK)
// for spi testing
SPI.TESTREG |= SPI.TESTREG_LBC;
#endif
// everything should be clean and idle
ASSERT( SPI.TransmitBufferEmpty());
ASSERT( SPI.ReceiveBufferEmpty());
ASSERT( SPI.ShiftBufferEmpty ());
// make sure not trigger the SS pin for the LCD when doing any SPI activity.
// but we can have LCD SPI activity, if so, we want the SS be able to drive
#if (HARDWARE_BOARD_TYPE >= HARDWARE_BOARD_i_MXS_DEMO_REV_V1_2)
if(Configuration.DeviceCS != MC9328MXL_SPI::c_SPI1_SS)
{
CPU_GPIO_EnableInputPin( MC9328MXL_SPI::c_SPI1_SS, FALSE, NULL, GPIO_INT_NONE, RESISTOR_PULLUP );
}
#endif
#if defined(PLATFORM_ARM_MC9328MXS)
// make sure that we don't trigger the SS pin for LCD
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_SCLK, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY);
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_MOSI, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY);
#else // MC9328MXL
if (index == MC9328MXL_SPI::c_SPI1)
{
// allow peripheral control of pins
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_SCLK, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY);
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_MOSI, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY);
}
else
{
// SPI2 need to set to Alternate function - AIN
CPU_GPIO_DisablePin(MC9328MXL_SPI::c_SPI2_SCLK, RESISTOR_DISABLED, MC9328MXL_GPIO::DDIR__OUT, GPIO_ALT_MODE_1);
CPU_GPIO_DisablePin(MC9328MXL_SPI::c_SPI2_MOSI, RESISTOR_DISABLED, MC9328MXL_GPIO::DDIR__OUT, GPIO_ALT_MODE_1);
}
#endif
// first set CS active as soon as clock and data pins are in proper initial state
if((Configuration.DeviceCS != MC9328MXL_GPIO::c_Pin_None) && (Configuration.DeviceCS != MC9328MXL_SPI::c_SPI1_SS))
{
CPU_GPIO_EnableOutputPin( Configuration.DeviceCS, Configuration.CS_Active );
}
#if defined(PLATFORM_ARM_MC9328MXS)
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_MISO, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY );
#else
if (index == MC9328MXL_SPI::c_SPI1)
{
CPU_GPIO_DisablePin( MC9328MXL_SPI::c_SPI1_MISO, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY );
}
else
{
// set AOUT mode for MISO for SPI 2
CPU_GPIO_DisablePin(MC9328MXL_SPI::c_SPI2_MISO, RESISTOR_DISABLED,MC9328MXL_GPIO::DDIR__IN ,GPIO_ALT_MODE_4);
MC9328MXL::SC().FMCR |= MC9328MXL_SC::FMCR__SPI2_RXD_SEL;
}
#endif
if(Configuration.CS_Setup_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled( Configuration.CS_Setup_uSecs );
}
}
else
{
lcd_printf( "\fSPI Collision 3\r\n" );
HARD_BREAKPOINT();
return FALSE;
}
return TRUE;
}
void PXA271_USART_Driver::ProtectPins( int comPort, BOOL on )
{
struct PXA271_USART_CONFIG* Config = &g_PXA271_USART_Config;
if(comPort < 0 || comPort >= TOTAL_USART_PORT)
return;
USART_PORT_INFO& USART_port = All_USART_ports[comPort];
GLOBAL_LOCK(irq);
if(on)
{
if(!USART_port.PinsProtected)
{
USART_port.PinsProtected = TRUE;
RxBufferFullInterruptEnable( comPort, FALSE );
if(Config->RxProtectInput)
{
CPU_GPIO_EnableInputPin( USART_port.RXD_Pin, FALSE, NULL, GPIO_INT_NONE, Config->RxProtectResistor );
}
else
{
CPU_GPIO_EnableOutputPin( USART_port.RXD_Pin, Config->RxProtectOutputValue );
}
TxBufferEmptyInterruptEnable( comPort, FALSE );
if(Config->TxProtectInput)
{
CPU_GPIO_EnableInputPin( USART_port.TXD_Pin, FALSE, NULL, GPIO_INT_NONE, Config->TxProtectResistor );
}
else
{
CPU_GPIO_EnableOutputPin( USART_port.TXD_Pin, Config->TxProtectOutputValue );
}
if(USART_port.CTS_Pin_used)
{
if(Config->CTSProtectInput)
{
CPU_GPIO_EnableInputPin( USART_port.CTS_Pin, FALSE, NULL, GPIO_INT_NONE, Config->CTSProtectResistor );
}
else
{
CPU_GPIO_EnableOutputPin( USART_port.CTS_Pin, Config->CTSProtectOutputValue );
}
}
if(USART_port.RTS_Pin_used)
{
if(Config->RTSProtectInput)
{
CPU_GPIO_EnableInputPin( USART_port.RTS_Pin, FALSE, NULL, GPIO_INT_NONE, Config->RTSProtectResistor );
}
else
{
CPU_GPIO_EnableOutputPin( USART_port.RTS_Pin, Config->RTSProtectOutputValue );
}
}
}
}
else
{
if(USART_port.PinsProtected)
{
USART_port.PinsProtected = FALSE;
CPU_GPIO_DisablePin( USART_port.TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT, USART_port.TXD_Pin_function );
TxBufferEmptyInterruptEnable( comPort, TRUE );
CPU_GPIO_DisablePin( USART_port.RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN, USART_port.RXD_Pin_function );
RxBufferFullInterruptEnable( comPort, TRUE );
if(USART_port.CTS_Pin_used)
CPU_GPIO_DisablePin( USART_port.CTS_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN, USART_port.CTS_Pin_function );
if(USART_port.RTS_Pin_used)
CPU_GPIO_DisablePin( USART_port.RTS_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT, USART_port.RTS_Pin_function );
}
}
}
BOOL PXA271_SPI_Driver::Xaction_Stop( const SPI_CONFIGURATION& Configuration )
{
if(g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].m_Enabled)
{
PXA271_SPI& SPI = PXA271::SPI(Configuration.SPI_mod);
// we should have cleared the last TBF on the last RBF true setting
// we should never bring CS inactive with the shifter busy
ASSERT(!SPI.TransmitFifoNotEmpty());
ASSERT( SPI.ReceiveFifoEmpty());
ASSERT( SPI.ShiftBufferEmpty());
if(Configuration.CS_Hold_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled( Configuration.CS_Hold_uSecs );
}
// avoid noise drawing excess power on a floating line by putting this in pulldown
if(Configuration.SPI_mod ==0)
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_1);
else if(Configuration.SPI_mod ==1)
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_2);
else
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_3);
// next, bring the CS to the proper inactive state
if(Configuration.DeviceCS != PXA271_GPIO::c_Pin_None)
{
CPU_GPIO_EnableOutputPin(Configuration.DeviceCS, !Configuration.CS_Active);
}
// put pins in output low state when not in use to avoid noise since clock stop and reset will cause these to become inputs
if(Configuration.SPI_mod ==0)
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
}
else if(Configuration.SPI_mod ==1)
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
}
else
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_3);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_3);
}
// disable spi bus so no new operations start
SPI.SSP_SSCR0 = 0;
SPI.SSP_SSCR1 = 0;
PXA271::CLKMNGR().CKEN &= ~g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].ClockIndex;
g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].m_Enabled = FALSE;
}
else
{
lcd_printf("\fSPI Collision 4\r\n");
HARD_BREAKPOINT();
return FALSE;
}
return TRUE;
}
BOOL PXA271_SPI_Driver::Xaction_Start( const SPI_CONFIGURATION& Configuration )
{
if(!g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].m_Enabled)
{
g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].m_Enabled= TRUE;
// enable the Periperal clock for this device
PXA271::CLKMNGR().CKEN |= g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].ClockIndex;
PXA271_SPI& SPI = PXA271::SPI(Configuration.SPI_mod);
// make sure we didn't start one in the middle of an existing transaction
if((0 != SPI.SSP_SSCR0)||(0 != SPI.SSP_SSCR1))
{
lcd_printf("\fSPI Collision 1\r\n");
HARD_BREAKPOINT();
return FALSE;
}
SPI.SSP_SSCR0= PXA271_SPI::ConfigurationControlReg0( Configuration );
SPI.SSP_SSCR1= PXA271_SPI::ConfigurationControlReg1( Configuration );
#ifdef SPI_LOOP_BACK_PXA271
SPI.SSP_SSCR1|= SPI_LOOPBACK;
#endif
SPI.SSP_SSCR0|= SPI.SSP_SSCR0__SSE;
//everything should be clean and idle
ASSERT(!SPI.TransmitFifoNotEmpty());
ASSERT( SPI.ReceiveFifoEmpty());
ASSERT( SPI.ShiftBufferEmpty());
if(Configuration.SPI_mod ==0)
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
}
else if(Configuration.SPI_mod ==1)
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_2);
}
else
{
//allow peripheral control of pins;
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].CLK_pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_3);
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].TXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_OUT,GPIO_ALT_MODE_3);
}
// first set CS active as soon as clock and data pins are in proper initial state
if(Configuration.DeviceCS != PXA271_GPIO::c_Pin_None)
{
CPU_GPIO_EnableOutputPin(Configuration.DeviceCS, Configuration.CS_Active);
}
if(Configuration.SPI_mod ==0)
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_1);
else if(Configuration.SPI_mod ==1)
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_2);
else
CPU_GPIO_DisablePin( g_PXA271_SPI_Driver.s_All_SPI_port[Configuration.SPI_mod].RXD_Pin, RESISTOR_DISABLED, PXA271_GPIO::GPDR__DIR_IN,GPIO_ALT_MODE_3);
if(Configuration.CS_Setup_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled( Configuration.CS_Setup_uSecs );
}
}
else
{
lcd_printf( "\fSPI Collision 3\r\n" );
HARD_BREAKPOINT();
return FALSE;
}
return TRUE;
}
void LPC24XX_EMAC_lwip_setpins ( BOOL mode )
{
/* Connect pins to EMAC controller */
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_TXD0, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_TXD1, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_TX_EN, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_CRS_DV, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_RXD0, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_RXD1, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_RX_ER, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_REF_CLK, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_MDC, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_MDIO, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
if (mode)
{
/* Additional pins for MII mode */
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_TXD2, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_TXD3, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_TX_ER, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_TX_CLK, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_COL, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_RXD2, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_RXD3, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
CPU_GPIO_DisablePin( LPC24XX_EMAC::c_ENET_RX_DV, RESISTOR_DISABLED, GPIO_ATTRIBUTE_NONE, GPIO_ALT_MODE_1 );
}
}
void __section("SectionForBootstrapOperations") BootstrapCode_GPIO()
{
/* GPIO pins connected to NOR Flash and SRAM on the MCBSTM32F400 board */
const uint8_t PortD_PinList[] = {0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 12 ,13, 14, 15};
#ifdef DEBUG
// PE2,3,4,5 are used for TRACECLK and TRACEDATA0-3 so don't enable them as address pins in debug builds
// This limits external FLASH and SRAM to 1MB addressable space each.
const uint8_t PortE_PinList[] = {0, 1, /*2, 3, 4, 5,*/ 7, 8, 9, 10, 11, 12, 13, 14, 15};
#else
const uint8_t PortE_PinList[] = {0, 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15};
#endif
const uint8_t PortF_PinList[] = {0, 1, 2, 3, 4, 5, 12, 13, 14, 15};
const uint8_t PortG_PinList[] = {0, 1, 2, 3, 4, 5, 10};
const uint32_t pinConfig = 0x3C2; // Speed 100Mhz, AF12 FSMC, Alternate Mode
const uint32_t pinMode = pinConfig & 0xF;
const GPIO_ALT_MODE alternateMode = (GPIO_ALT_MODE) pinConfig;
const GPIO_RESISTOR resistorConfig = RESISTOR_PULLUP;
uint32_t i;
/* Enable GPIO clocks */
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN
| RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN
| RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | RCC_AHB1ENR_GPIOIEN;
CPU_GPIO_EnableOutputPin(LED1, FALSE);
CPU_GPIO_EnableOutputPin(LED2, FALSE);
CPU_GPIO_EnableOutputPin(LED3, FALSE);
CPU_GPIO_EnableOutputPin(LED4, FALSE);
CPU_GPIO_EnableOutputPin(LED5, FALSE);
CPU_GPIO_EnableOutputPin(LED6, FALSE);
CPU_GPIO_EnableOutputPin(LED7, FALSE);
CPU_GPIO_EnableOutputPin(LED8, FALSE);
/*Initialize SRAM and NOR GPIOs */
for(i = 0; i < ARRAY_LENGTH(PortD_PinList); i++) /* Port D */
{
CPU_GPIO_ReservePin( PORT_PIN(GPIO_PORTD, PortD_PinList[i]), TRUE);
CPU_GPIO_DisablePin( PORT_PIN(GPIO_PORTD, PortD_PinList[i]), resistorConfig, 0, alternateMode);
STM32F4_GPIO_Pin_Config( PORT_PIN(GPIO_PORTD, PortD_PinList[i]), pinMode, resistorConfig, pinConfig ); // Workaround, since CPU_GPIO_DisablePin() does not correctly initialize pin speeds
}
for(i = 0; i < ARRAY_LENGTH(PortE_PinList); i++) /* Port E */
{
CPU_GPIO_ReservePin( PORT_PIN(GPIO_PORTE, PortE_PinList[i]), TRUE);
CPU_GPIO_DisablePin( PORT_PIN(GPIO_PORTE, PortE_PinList[i]), resistorConfig, 0, alternateMode);
STM32F4_GPIO_Pin_Config( PORT_PIN(GPIO_PORTE, PortE_PinList[i]), pinMode, resistorConfig, pinConfig ); // Workaround, since CPU_GPIO_DisablePin() does not correctly initialize pin speeds
}
for(i = 0; i < ARRAY_LENGTH(PortF_PinList); i++) /* Port F */
{
CPU_GPIO_ReservePin( PORT_PIN(GPIO_PORTF, PortF_PinList[i]), TRUE);
CPU_GPIO_DisablePin( PORT_PIN(GPIO_PORTF, PortF_PinList[i]), resistorConfig, 0, alternateMode);
STM32F4_GPIO_Pin_Config( PORT_PIN(GPIO_PORTF, PortF_PinList[i]), pinMode, resistorConfig, pinConfig ); // Workaround, since CPU_GPIO_DisablePin() does not correctly initialize pin speeds
}
for(i = 0; i < ARRAY_LENGTH(PortG_PinList); i++) /* Port G */
{
CPU_GPIO_ReservePin( PORT_PIN(GPIO_PORTG, PortG_PinList[i]), TRUE);
CPU_GPIO_DisablePin( PORT_PIN(GPIO_PORTG, PortG_PinList[i]), resistorConfig, 0, alternateMode);
STM32F4_GPIO_Pin_Config( PORT_PIN(GPIO_PORTG, PortG_PinList[i]), pinMode, resistorConfig, pinConfig ); // Workaround, since CPU_GPIO_DisablePin() does not correctly initialize pin speeds
}
/* Initialize NOR and SRAM */
InitNorFlash();
InitSram();
}
BOOL MC9328MXL_LCD_Driver::Initialize(DISPLAY_CONTROLLER_CONFIG& config)
{
NATIVE_PROFILE_HAL_PROCESSOR_LCD();
MC9328MXL_LCDC& LCDC = MC9328MXL::LCDC();
UINT32 Extras[offsetof(MC9328MXL_LCDC,LCDISR)/sizeof(UINT32) + 1];
memset(Extras, 0, sizeof(Extras));
for(int i=0; i<ARRAYSIZE(config.RegisterExtras); i++)
{
if(config.RegisterExtras[i].RegAddr == 0) break;
int val = GET_EXTRA_REG_INDEX(config.RegisterExtras[i].RegAddr);
if(val < 0 || ARRAYSIZE(Extras) < val) continue;
Extras[val] = config.RegisterExtras[i].RegValue;
}
// Disable GPIO on all the LCD Pins (SPI1, Port D6, 13 ~ 30)
{
static const UINT8 c_LCD[] =
{
MC9328MXL_GPIO::c_Port_D_06,
MC9328MXL_GPIO::c_Port_D_13,
MC9328MXL_GPIO::c_Port_D_14,
MC9328MXL_GPIO::c_Port_D_15,
MC9328MXL_GPIO::c_Port_D_16,
MC9328MXL_GPIO::c_Port_D_17,
MC9328MXL_GPIO::c_Port_D_18,
MC9328MXL_GPIO::c_Port_D_19,
MC9328MXL_GPIO::c_Port_D_20,
MC9328MXL_GPIO::c_Port_D_21,
MC9328MXL_GPIO::c_Port_D_22,
MC9328MXL_GPIO::c_Port_D_23,
MC9328MXL_GPIO::c_Port_D_24,
MC9328MXL_GPIO::c_Port_D_25,
MC9328MXL_GPIO::c_Port_D_26,
MC9328MXL_GPIO::c_Port_D_27,
MC9328MXL_GPIO::c_Port_D_28,
MC9328MXL_GPIO::c_Port_D_29,
MC9328MXL_GPIO::c_Port_D_30,
};
for(int pin=0; pin < ARRAYSIZE(c_LCD); pin++)
{
CPU_GPIO_DisablePin( c_LCD[pin], RESISTOR_DISABLED, MC9328MXL_GPIO::DDIR__OUT, GPIO_ALT_PRIMARY);
}
}
// Set Screen Start Addr, Resolution
LCDC.SSA = MC9328MXL_LCD_Driver::c_Screen_Buffer << MC9328MXL_LCDC::SSA__SSA_shift;
LCDC.SIZE = ((UINT32)config.Width << MC9328MXL_LCDC::SIZE__XMAX_shift) |
((UINT32)config.Height << MC9328MXL_LCDC::SIZE__YMAX_shift);
LCDC.VPW = ((UINT32)(config.Width + BITS_PER_PIXEL_TO_PIXELS_PER_WORD(config.BitsPerPixel) - 1) / BITS_PER_PIXEL_TO_PIXELS_PER_WORD(config.BitsPerPixel)) << MC9328MXL_LCDC::VPW__VPW_shift;
// LCD timing
{
UINT32 val = 0;
val |= config.EnableTFT? MC9328MXL_LCDC::PCR__TFT__Enable << MC9328MXL_LCDC::PCR__TFT_shift : 0;
val |= config.EnableColor? MC9328MXL_LCDC::PCR__COLOR__Enable << MC9328MXL_LCDC::PCR__COLOR_shift: 0;
switch(config.BusWidth)
{
case 1:
val |= MC9328MXL_LCDC::PCR__PBSIZ__1_Bit << MC9328MXL_LCDC::PCR__PBSIZ_shift;
break;
case 2:
val |= MC9328MXL_LCDC::PCR__PBSIZ__2_Bit << MC9328MXL_LCDC::PCR__PBSIZ_shift;
break;
case 4:
val |= MC9328MXL_LCDC::PCR__PBSIZ__4_Bit << MC9328MXL_LCDC::PCR__PBSIZ_shift;
break;
case 8:
val |= MC9328MXL_LCDC::PCR__PBSIZ__8_Bit << MC9328MXL_LCDC::PCR__PBSIZ_shift;
break;
case 16:
val |= MC9328MXL_LCDC::PCR__PBSIZ__TFT_16_Bit << MC9328MXL_LCDC::PCR__PBSIZ_shift;
break;
}
switch(config.BitsPerPixel)
{
case 1:
val |= MC9328MXL_LCDC::PCR__BPIX__1bpp << MC9328MXL_LCDC::PCR__BPIX_shift;
break;
case 2:
val |= MC9328MXL_LCDC::PCR__BPIX__2bpp << MC9328MXL_LCDC::PCR__BPIX_shift;
break;
case 4:
val |= MC9328MXL_LCDC::PCR__BPIX__4bpp << MC9328MXL_LCDC::PCR__BPIX_shift;
break;
case 8:
val |= MC9328MXL_LCDC::PCR__BPIX__8bpp << MC9328MXL_LCDC::PCR__BPIX_shift;
break;
case 12: // fall through
case 16:
val |= MC9328MXL_LCDC::PCR__BPIX__12bpp_16bpp << MC9328MXL_LCDC::PCR__BPIX_shift;
break;
}
val |= (!config.PixelPolarity ) ? MC9328MXL_LCDC::PCR__PIXPOL__Active_Low << MC9328MXL_LCDC::PCR__PIXPOL_shift : 0; // bit set indicates low polarity
val |= (!config.FirstLineMarkerPolarity) ? MC9328MXL_LCDC::PCR__FLMPOL__Active_Low << MC9328MXL_LCDC::PCR__FLMPOL_shift : 0; // bit set indicates low polarity
val |= (!config.LinePulsePolarity ) ? MC9328MXL_LCDC::PCR__LPPOL__Active_Low << MC9328MXL_LCDC::PCR__LPPOL_shift : 0; // bit set indicates low polarity
val |= (!config.ShiftClockPolarity ) ? MC9328MXL_LCDC::PCR__CLKPOL__Active_Low << MC9328MXL_LCDC::PCR__CLKPOL_shift : 0; // bit set indicates low polarity
val |= (!config.OutputEnablePolarity ) ? MC9328MXL_LCDC::PCR__OEPOL__Active_Low << MC9328MXL_LCDC::PCR__OEPOL_shift : 0; // bit set indicates low polarity
val |= config.ClockIdleEnable ? MC9328MXL_LCDC::PCR__SCLKIDLE__Enable_LSCLK << MC9328MXL_LCDC::PCR__SCLKIDLE_shift : 0;
val |= config.ClockSelectEnable ? MC9328MXL_LCDC::PCR__SCLKSEL_Enable_LSCLK << MC9328MXL_LCDC::PCR__SCLKSEL_shift : 0;
val |= (UINT32)config.PixelClockDivider << MC9328MXL_LCDC::PCR__PCD_shift;
LCDC.PCR = val | Extras[GET_EXTRA_REG_INDEX(&LCDC.PCR)];
}
{
UINT32 val = 0;
val |= (UINT32)config.HorizontalSyncPulseWidth << MC9328MXL_LCDC::HCR__H_WIDTH_shift;
val |= (UINT32)config.HorizontalSyncWait1 << MC9328MXL_LCDC::HCR__H_WAIT_1_shift;
val |= (UINT32)config.HorizontalSyncWait2 << MC9328MXL_LCDC::HCR__H_WAIT_2_shift;
LCDC.HCR = val;
}
{
UINT32 val = 0;
val |= (UINT32)config.VerticalSyncPulseWidth << MC9328MXL_LCDC::VCR__V_WIDTH_shift;
val |= (UINT32)config.VerticalSyncWait1 << MC9328MXL_LCDC::VCR__V_WAIT_1_shift;
val |= (UINT32)config.VerticalSyncWait2 << MC9328MXL_LCDC::VCR__V_WAIT_2_shift;
LCDC.VCR = val;
}
LCDC.LSCR1 = Extras[GET_EXTRA_REG_INDEX(&LCDC.LSCR1)];
LCDC.PWMR = Extras[GET_EXTRA_REG_INDEX(&LCDC.PWMR)];
LCDC.LCDICR = Extras[GET_EXTRA_REG_INDEX(&LCDC.LCDICR)];
LCDC.LCDISR = Extras[GET_EXTRA_REG_INDEX(&LCDC.LCDISR)];
// DMA control
if(Extras[GET_EXTRA_REG_INDEX(&LCDC.DMACR)])
{
LCDC.DMACR = Extras[GET_EXTRA_REG_INDEX(&LCDC.DMACR)];
}
else
{
UINT32 val = 0;
val |= 8 << MC9328MXL_LCDC::DMACR__TM_shift;
val |= 3 << MC9328MXL_LCDC::DMACR__HM_shift;
val |= MC9328MXL_LCDC::DMACR__BURST__DYNAMIC << MC9328MXL_LCDC::DMACR__BURST_shift;
LCDC.DMACR = val;
}
return TRUE;
}
//Initialize USB Host
// USB OTG Full Speed is controller 0
// USB OTG High Speed is controller 1
BOOL USBH_Initialize( int Controller ) {
CPU_GPIO_EnableOutputPin(16+2, TRUE);
// enable USB clock
OTG_TypeDef* OTG;
if (Controller == 0) {
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
OTG = OTG_FS;
}
else if (Controller == 1) {
RCC->AHB1ENR |= RCC_AHB1ENR_OTGHSEN;
OTG = OTG_HS;
}
else {
return FALSE;
}
//disable int
OTG->GAHBCFG &= ~OTG_GAHBCFG_GINTMSK;
//core init 1
OTG->GINTSTS |= OTG_GINTSTS_RXFLVL;
OTG->GAHBCFG |= OTG_GAHBCFG_PTXFELVL;
//core init 2
OTG->GUSBCFG &= ~OTG_GUSBCFG_HNPCAP;
OTG->GUSBCFG &= ~OTG_GUSBCFG_SRPCAP;
OTG->GUSBCFG &= ~OTG_GUSBCFG_TRDT;
OTG->GUSBCFG |= STM32F4_USB_TRDT<<10;
OTG->GUSBCFG |= OTG_GUSBCFG_PHYSEL;
//core init 3
OTG->GINTMSK |= OTG_GINTMSK_OTGINT | OTG_GINTMSK_MMISM;
//force host mode
OTG->GUSBCFG |= OTG_GUSBCFG_FHMOD;
//host init
OTG->GINTMSK |= OTG_GINTMSK_PRTIM;
OTG->HCFG = OTG_HCFG_FSLSPCS_48MHZ;
OTG->HPRT |= OTG_HPRT_PPWR;
OTG->GCCFG |= (OTG_GCCFG_VBUSBSEN | OTG_GCCFG_VBUSASEN | OTG_GCCFG_NOVBUSSENS | OTG_GCCFG_PWRDWN);
//
//config pins and ISR
if (Controller == 0) {
CPU_GPIO_DisablePin(10, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)0xA2);
CPU_GPIO_DisablePin(11, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)0xA2);
CPU_INTC_ActivateInterrupt(OTG_FS_IRQn, USBH_ISR, OTG);
}
else {
CPU_GPIO_DisablePin(16+14, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)0xC2);
CPU_GPIO_DisablePin(16+15, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)0xC2);
CPU_INTC_ActivateInterrupt(OTG_HS_IRQn, USBH_ISR, OTG);
}
for (int i = 0; i < 3; i++)
{
CPU_GPIO_SetPinState(18, 1);
HAL_Time_Sleep_MicroSeconds(200*1000);
CPU_GPIO_SetPinState(18, 0);
HAL_Time_Sleep_MicroSeconds(200*1000);
}
//enable interrupt
OTG->GINTSTS = 0xFFFFFFFF;
OTG->GAHBCFG |= OTG_GAHBCFG_GINTMSK;
return TRUE;
}
BOOL TSC2046_Driver::Disable()
{
CPU_GPIO_DisablePin( g_TSC2046_Config.InterruptPin, RESISTOR_DISABLED, 0, GPIO_ALT_PRIMARY);
return true;
}
BOOL SD_BS_Driver::ChipInitialize(void *context)
{
SD_BLOCK_CONFIG *config = (SD_BLOCK_CONFIG*)context;
if(!config || !config->BlockDeviceInformation)
{
return FALSE;
}
BlockDeviceInfo *pDevInfo = config->BlockDeviceInformation;
UINT32 alternate = 0x1C2;
CPU_GPIO_DisablePin(PC8_SD_D0, RESISTOR_PULLUP, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin(PC9_SD_D1, RESISTOR_PULLUP, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin(PC10_SD_D2, RESISTOR_PULLUP, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin(PC11_SD_D3, RESISTOR_PULLUP, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin(PC12_SD_CLK, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin(PD2_SD_CMD, RESISTOR_PULLUP, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_ReservePin( PC8_SD_D0, TRUE );
CPU_GPIO_ReservePin( PC9_SD_D1, TRUE );
CPU_GPIO_ReservePin( PC10_SD_D2, TRUE );
CPU_GPIO_ReservePin( PC11_SD_D3, TRUE );
CPU_GPIO_ReservePin( PC12_SD_CLK, TRUE );
CPU_GPIO_ReservePin( PD2_SD_CMD, TRUE );
RCC->APB2ENR |= (1 << 11);
CPU_INTC_ActivateInterrupt( /*UINT32 Irq_Index*/SDIO_IRQn, /*HAL_CALLBACK_FPN ISR*/SDIO_IRQHandler, /*void* ISR_Param*/0 );
__IO SD_Error errorstatus = SD_OK;
//errorstatus = SD_PowerON();
errorstatus = SD_Init();
CPU_INTC_InterruptEnable( /*UINT32 Irq_Index*/SDIO_IRQn );
memset(pBuffer, 0xFF, 512);
errorstatus = SD_ReadBlock(pBuffer, 0, 512);
//errorstatus = SD_WaitReadOperation();
//while(SD_GetStatus() != SD_TRANSFER_OK);
if (SD_GetStatus() != SD_TRANSFER_OK)
{
if (SD_GetStatus_WithTimeOut(SD_INITIALIZE_TIMEOUT)== FALSE)
return FALSE;
}
//CPU_FlushCaches();
// // Variables to setup SD Card Dynamically.
// //BYTE regCSD[16]; <-- Not used because we have better register access.
BYTE C_SIZE_MULT = 0;
BYTE TAAC, NSAC, MAX_RAN_SPEED, READ_BL_LEN, SECTOR_SIZE;
BOOL ERASE_BL_EN;
UINT32 C_SIZE;
UINT64 MemCapacity = 0; //total memory size, in unit of byte
TAAC = SDCardInfo.SD_csd.TAAC; // regCSD[1]; /* STM // Original */
NSAC = SDCardInfo.SD_csd.NSAC; // regCSD[2]; /* STM // Original */
MAX_RAN_SPEED = SDCardInfo.SD_csd.MaxBusClkFrec; // regCSD[3]; /* STM // Original */
READ_BL_LEN = SDCardInfo.SD_csd.RdBlockLen; // regCSD[5] &0x0F; /* STM // Original */
// Checks to see if the SD card is Version 1.0: Standard or Version 2.0: High Capacity
if(SDCardInfo.SD_csd.CSDStruct == 0x00) /*if(regCSD[0] == 0x00)*/
// SD Version1.0
{
C_SIZE = SDCardInfo.SD_csd.DeviceSize; // ((regCSD[6] &0x3) << 10) | (regCSD[7] << 2) | ((regCSD[8] &0xC0) >> 6); /* STM // Original */
C_SIZE_MULT = SDCardInfo.SD_csd.DeviceSizeMul; // ((regCSD[9] &0x03) << 1) | ((regCSD[10] &0x80) >> 7); /* STM // Original */
ERASE_BL_EN = (SDCardInfo.SD_csd.EraseGrSize == 0x00) ? FALSE : TRUE; // ((regCSD[10] &0x40) == 0x00) ? FALSE : TRUE; /* STM // Original */
SECTOR_SIZE = SDCardInfo.SD_csd.EraseGrMul; // ((regCSD[10] &0x3F) << 1) | ((regCSD[11] &0x80) >> 7); /* STM // Original */
MemCapacity = SDCardInfo.CardCapacity; // (C_SIZE + 1) * (0x1 << (C_SIZE_MULT + 2)) * (0x1 << READ_BL_LEN); /* STM // Original */
IsSDCardHC = FALSE;
}
else
// SD Version2.0
{
C_SIZE = SDCardInfo.SD_csd.DeviceSize; // ((regCSD[7] &0x3F) << 16) | (regCSD[8] << 8) | regCSD[9]; /* STM // Original */
ERASE_BL_EN = (SDCardInfo.SD_csd.EraseGrSize == 0x00) ? FALSE : TRUE; // ((regCSD[10] &0x40) == 0x00) ? FALSE : TRUE; /* STM // Original */
SECTOR_SIZE = SDCardInfo.SD_csd.EraseGrMul; // ((regCSD[10] &0x3F) << 1) | ((regCSD[11] &0x80) >> 7); /* STM // Original */
MemCapacity = SDCardInfo.CardCapacity; // (C_SIZE + 1) * 512 * 1024; /* STM // Original */
IsSDCardHC = TRUE;
}
//Update SD config according to CSD register
UINT32 SectorsPerBlock = (ERASE_BL_EN == TRUE) ? 1 : (SECTOR_SIZE + 1);
pDevInfo->BytesPerSector = 512; // data bytes per sector is always 512
pDevInfo->Size = (ByteAddress)MemCapacity;
BlockRegionInfo* pRegions = (BlockRegionInfo*)&pDevInfo->Regions[0];
pRegions[0].BytesPerBlock = SectorsPerBlock * pDevInfo->BytesPerSector;
pRegions[0].NumBlocks = (UINT32)(MemCapacity / pRegions[0].BytesPerBlock);
BlockRange* pRanges = (BlockRange*)&pRegions[0].BlockRanges[0];
pRanges[0].StartBlock = 0;
pRanges[0].EndBlock = pRegions[0].NumBlocks-1;
return TRUE;
}
