CSL_Status CSL_edmaHwChannelSetup( /** pointer to the object that holds reference to the channel * instance of the Specified DMA */ CSL_EdmaChanHandle hCh, /** pointer to the setup structure */ CSL_EdmaHwChannelSetup *setup ) { if (hCh==NULL) return CSL_ESYS_BADHANDLE; if (setup==NULL) return CSL_ESYS_INVPARAMS; CSL_edmaChannelSetEvtQue(hCh,setup->que); if (hCh->chaNum < CSL_EDMA_NUM_DMACH) { #if CSL_EDMA_CHMAPEXIST CSL_FINS(hCh->ccregs->DCHMAP[hCh->chaNum], EDMACC_DCHMAP_PAENTRY,setup->paramEntry); #endif } else hCh->ccregs->QCHMAP[hCh->chaNum-CSL_EDMA_NUM_DMACH] = CSL_FMK(EDMACC_QCHMAP_PAENTRY,setup->paramEntry) | CSL_FMK(EDMACC_QCHMAP_TRWORD,setup->triggerWord); return CSL_SOK; }
/** ============================================================================ * @n@b MDIO_open() * * @b Description * @n Opens the MDIO peripheral and start searching for a PHY device. * * It is assumed that the MDIO module is reset prior to calling this * function. * * @b Arguments * @verbatim mdioModeFlags mode flags pof MII @endverbatim * * <b> Return Value </b> Handle to the opened MDIO instance * * <b> Pre Condition </b> * @n The MDIO module must be reset prior to calling this function. * * <b> Post Condition </b> * @n Opens the MDIO peripheral and start searching for a PHY device. * * @b Example: * @verbatim #define MDIO_MODEFLG_FD1000 0x0020 #define MDIO_MODEFLG_EXTLOOPBACK 0x0100 Uint32 mdioModeFlags = MDIO_MODEFLG_FD1000 | MDIO_MODEFLG_LOOPBACK; MDIO_open ( mdioModeFlags ); @endverbatim * ============================================================================ */ Handle MDIO_open( Uint32 mdioModeFlags ) { /* * Note: In a multi-instance environment, we'd have to allocate "localDev" */ static MDIO_Device localDev; /* Find out what interface we are working with */ //macsel = CSL_FEXT(DEV_REGS->DEVSTAT, DEV_DEVSTAT_MACSEL); /* Get the mode flags from the user - clear our reserved flag */ localDev.ModeFlags = mdioModeFlags & ~MDIO_MODEFLG_NWAYACTIVE; /* Setup the MDIO state machine */ MDIO_initStateMachine( &localDev ); /* Enable MDIO and setup divider */ MDIO_REGS->CONTROL = CSL_FMKT(MDIO_CONTROL_ENABLE,YES) | CSL_FMK(MDIO_CONTROL_CLKDIV,VBUSCLK) ; /* We're done for now - all the rest is done via MDIO_event() */ return( &localDev ); }
/** ============================================================================ * @n@b Init_MDIO * * @b Description * @n Not supported at moment. MDIO is not simulated yet. * * @param[in] * @n None * * @return * @n None * ============================================================================= */ Void Init_MDIO (uint8_t phy_addr) { #ifdef TI_SUPPORT_EXT_LOOPBACK //Enable MDIO Control hMdioRegs->CONTROL_REG |= 0x410000ff; // Register 18 = 0 (disable all interrupts hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR,18) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 9 = 0x1F00 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 9) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x1F00; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 0 = 0x9140 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 0) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x9140; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 29 = 7 page 7 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 29) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x0007; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 30 = 0x0808 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 30) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x0808; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 29 = 0x10 page 16 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 29) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x10; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 30 = 0x005A hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 30) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x005A; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 29 = 0x12 page 18 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 29) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x12; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 30 = 0x8241 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 30) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x8241; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Disable MDIO Control hMdioRegs->CONTROL_REG &= 0xBFFFFFFFF; uart_write ("PHY %d configured in TI SUPPORT external loopback mode \n",phy_addr); #endif #ifdef EXT_LOOPBACK //Enable MDIO Control hMdioRegs->CONTROL_REG |= 0x410000ff; // Register 18 = 0 (disable all interrupts hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR,18) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 9 = 0x1F00 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 9) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x1B00; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 0 = 0x9140 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 0) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x9140; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 29 = 7 page 7 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 29) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x0007; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 30 = 0x0808 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 30) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x0808; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 29 = 0x10 page 16 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 29) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x10; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 30 = 0x005A hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 30) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x0042; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 29 = 0x12 page 18 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 29) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x12; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Register 30 = 0x8241 hMdioRegs->USER_GROUP [0].USER_ACCESS_REG = CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, phy_addr) | CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, 30) | CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 1) | CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u)| 0x8901; // Wait for MDIO state machine finishing while (CSL_MDIO_isUserAccessPending (0)); // Disable MDIO Control hMdioRegs->CONTROL_REG &= 0xBFFFFFFFF; uart_write ("PHY %d configured in MARVELL external loopback mode \n",phy_addr); #endif /* Return success. */ return; }
void configureFFTRegs(CSL_FftcRegs* regs){ /* The FFTC Local Configuration consists of configuration of the following * queue specific registers: * 1. FFTC Queue x Destination Queue Register * 2. FFTC Queue x Scaling & Shifting Register * 3. FFTC Queue x Cyclic Prefix Register * 4. FFTC Queue x Control Register * 5. FFTC Queue x LTE Frequency Shift Register */ /* Step 1. Configure the FFTC Queue 'n' Destination Queue Register */ regs->Q0_DEST = CSL_FMK (FFTC_Q0_DEST_FFTC_SHIFT_LEFT_RIGHT_OUTPUT, 0) | CSL_FMK (FFTC_Q0_DEST_FFTC_SHIFT_LEFT_RIGHT_INPUT, 0) | CSL_FMK (FFTC_Q0_DEST_FFTC_VARIABLE_SHIFT_INPUT, 0) | CSL_FMK (FFTC_Q0_DEST_DEFAULT_DEST, 0x3FFF); /* Step 2. Configure the Queue 'n' Scaling and Shift Register configuration. */ regs->Q0_SCALE_SHIFT = CSL_FMK (FFTC_Q0_SCALE_SHIFT_DYNAMIC_SCALING_ENABLE, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_OUTPUT_SCALING, 2) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_OUT_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_6_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_5_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_4_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_3_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_2_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_1_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_0_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_LTE_SHIFT_SCALING, 0); /* Step 3. Configure Queue 'n' Cyclic Prefix Register */ regs->Q0_CYCLIC_PREFIX = CSL_FMK (FFTC_Q0_CYCLIC_PREFIX_CYCLIC_PREFIX_REMOVE_EN, 0) | CSL_FMK (FFTC_Q0_CYCLIC_PREFIX_CYCLIC_PREFIX_REMOVE_OFFSET, 0) | CSL_FMK (FFTC_Q0_CYCLIC_PREFIX_CYCLIC_PREFIX_ADDITION, 0); /* Step 4. Configure Queue 'n' Control Register */ regs->Q0_CONTROL = CSL_FMK (FFTC_Q0_CONTROL_SUPPRESSED_SIDE_INFO, 1) | CSL_FMK (FFTC_Q0_CONTROL_DFT_IDFT_SELECT, 1) | /* DFT */ CSL_FMK (FFTC_Q0_CONTROL_ZERO_PAD_MODE, 0) | CSL_FMK (FFTC_Q0_CONTROL_ZERO_PAD_VAL, 0) | CSL_FMK (FFTC_Q0_CONTROL_DFT_SIZE, 6); /* 6 -> 256 */ /* Step 5. Finally configure the Queue 'n' LTE Frequency Shift Register */ regs->Q0_LTE_FREQ = CSL_FMK (FFTC_Q0_LTE_FREQ_LTE_FREQ_SHIFT_EN, 0) | CSL_FMK (FFTC_Q0_LTE_FREQ_LTE_FREQ_SHIFT_DIR, 0) | CSL_FMK (FFTC_Q0_LTE_FREQ_LTE_FREQ_SHIFT_FACTOR, 0) | CSL_FMK (FFTC_Q0_LTE_FREQ_LTE_FREQ_SHIFT_PHASE, 0) | CSL_FMK (FFTC_Q0_LTE_FREQ_LTE_FREQ_SHIFT_INDEX, 0); }
void setFFTSize(int id, int size){ CSL_FftcRegs* regs; switch(id){ case 0: regs = fftc_a_cfg_regs; break; case 1: regs = fftc_b_cfg_regs; break; default: printf("Unhandled case in setFFTSize\n"); } int logSize = log2(size)-2; regs->Q0_SCALE_SHIFT = CSL_FMK (FFTC_Q0_SCALE_SHIFT_DYNAMIC_SCALING_ENABLE, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_OUTPUT_SCALING, 16) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_OUT_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_6_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_5_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_4_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_3_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_2_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_1_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_0_SCALING, 0) | CSL_FMK (FFTC_Q0_SCALE_SHIFT_STAGE_LTE_SHIFT_SCALING, 0); /* Step 4. Configure Queue 'n' Control Register */ regs->Q0_CONTROL = CSL_FMK (FFTC_Q0_CONTROL_SUPPRESSED_SIDE_INFO, 1) | CSL_FMK (FFTC_Q0_CONTROL_DFT_IDFT_SELECT, 1) | /* DFT */ CSL_FMK (FFTC_Q0_CONTROL_ZERO_PAD_MODE, 0) | CSL_FMK (FFTC_Q0_CONTROL_ZERO_PAD_VAL, 0) | CSL_FMK (FFTC_Q0_CONTROL_DFT_SIZE, logSize); }