static void SerialBSP_AT91_USART3_CfgInt (SERIAL_DEV *pdev,
SERIAL_ERR *perr)
{
CSP_IntSrcCfg(CSP_INT_CTRL_NBR_MAIN,
CSP_INT_SRC_NBR_UART_03,
0u,
CSP_INT_POL_LEVEL_HIGH);
#if (CSP_CFG_INT_ISR_ARG_EN == DEF_ENABLED)
CSP_IntVectReg((CSP_DEV_NBR )CSP_INT_CTRL_NBR_MAIN,
(CSP_DEV_NBR )CSP_INT_SRC_NBR_UART_03,
(CPU_FNCT_PTR )SerialBSP_AT91_USARTx_IntHandler,
(void *)pdev);
#else
SerialBSP_AT91_USART3_DevPtr = pdev;
CSP_IntVectReg((CSP_DEV_NBR )CSP_INT_CTRL_NBR_MAIN,
(CSP_DEV_NBR )CSP_INT_SRC_NBR_UART_03,
(CPU_FNCT_PTR )SerialBSP_AT91_USART3_IntHandler,
(void *)pdev);
#endif
CSP_IntEn(CSP_INT_CTRL_NBR_MAIN, CSP_INT_SRC_NBR_UART_03);
*perr = SERIAL_ERR_NONE;
}
CPU_BOOLEAN CSP_DMA_InitExt (void)
{
CSP_DMA_REG *p_dma_reg;
CSP_DMA_CH_REG *p_dma_ch_reg;
CSP_DMA_CH *p_ch_tbl;
CPU_INT08U ch_nbr;
CSP_IntDis(CSP_INT_CTRL_NBR_MAIN, /* Disable DMA interrupts */
CSP_INT_SRC_NBR_DMA_00);
CSP_PM_PerClkEn(CSP_PM_PER_CLK_NBR_DMA_00); /* Enable DMA controller clock. */
p_dma_reg = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;
p_dma_reg->IntTCClr = DEF_INT_08_MASK; /* Clear all pending interrupts. */
p_dma_reg->IntErrClr = DEF_INT_08_MASK;
/* Initialize DMA channels register & table */
for (ch_nbr = 0u; ch_nbr < CSP_DMA_CH_MAX_NBR; ch_nbr++) {
p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
p_ch_tbl = &CSP_DMA_ChTbl[ch_nbr];
p_ch_tbl->State = CSP_DMA_CH_STATE_FREE;
p_ch_tbl->CallBackFnctPtr = (CSP_DMA_CALLBACK_PTR )0;
p_ch_tbl->CallBackArgPtr = (void *)0;
p_dma_ch_reg->SrcAddr = 0u;
p_dma_ch_reg->DestAddr = 0u;
p_dma_ch_reg->LLI = 0u;
p_dma_ch_reg->Ctrl = DEF_BIT_NONE;
p_dma_ch_reg->Cfg = DEF_BIT_NONE;
}
p_dma_reg->Cfg = CSP_DMA_REG_CFG_DMA_EN; /* Enable DMA controller. */
(void)CSP_IntVectReg((CSP_DEV_NBR )CSP_INT_CTRL_NBR_MAIN, /* Install global DMA interrupt handler. */
(CSP_DEV_NBR )CSP_INT_SRC_NBR_DMA_00,
(CPU_FNCT_PTR )CSP_DMA_IntHandler,
(void *)0);
CSP_IntEn(CSP_INT_CTRL_NBR_MAIN,
CSP_INT_SRC_NBR_DMA_00);
return (DEF_OK);
}
int main (void)
{
OS_ERR os_err;
#if (CPU_CFG_NAME_EN == DEF_ENABLED)
CPU_ERR cpu_err;
#endif
BSP_PreInit(); /* initialize basic board support routines */
#if (CPU_CFG_NAME_EN == DEF_ENABLED)
CPU_NameSet((CPU_CHAR *)CSP_DEV_NAME,
(CPU_ERR *)&cpu_err);
#endif
Mem_Init(); /* Initialize memory management module */
OSInit(&os_err); /* Init uC/OS-III */
// Debug_printf(Debug_Level_1, "Starting init");
#if 0
/* Enable Timer0 Interrupt.*/
CSP_IntVectReg((CSP_DEV_NBR )CSP_INT_CTRL_NBR_MAIN,
(CSP_DEV_NBR )CSP_INT_SRC_NBR_TMR_00,
(CPU_FNCT_PTR )App_TMR0_IntHandler,
(void *)0);
CSP_IntEn(CSP_INT_CTRL_NBR_MAIN, CSP_INT_SRC_NBR_TMR_00);
/* Enable Timer1 Interrupt.*/
CSP_IntVectReg((CSP_DEV_NBR )CSP_INT_CTRL_NBR_MAIN,
(CSP_DEV_NBR )CSP_INT_SRC_NBR_TMR_01,
(CPU_FNCT_PTR )App_TMR1_IntHandler,
(void *)0);
CSP_IntEn(CSP_INT_CTRL_NBR_MAIN, CSP_INT_SRC_NBR_TMR_01);
/* Enable Timer2 Interrupt.*/
CSP_IntVectReg((CSP_DEV_NBR )CSP_INT_CTRL_NBR_MAIN,
(CSP_DEV_NBR )CSP_INT_SRC_NBR_TMR_02,
(CPU_FNCT_PTR )App_TMR2_IntHandler,
(void *)0);
CSP_IntEn(CSP_INT_CTRL_NBR_MAIN, CSP_INT_SRC_NBR_TMR_02);
CSP_TmrInit();
CSP_TmrCfg (CSP_TMR_NBR_00,TIMER_FREQ);
CSP_TmrCfg (CSP_TMR_NBR_01,TIMER_FREQ);
CSP_TmrCfg (CSP_TMR_NBR_02,TIMER_FREQ);
#endif
#if 0
// Init the Ethernet PHY
EMAC_PinCfg();
emacConfigStruct.Mode = EMAC_MODE_100M_FULL;
emacConfigStruct.pbEMAC_Addr = EthernetLinkLayer_macAddress();
OS_EMAC_Init(EthernetLinkLayer_rxSemaphore());
EMAC_Init(&emacConfigStruct);
EMAC_SetFilterMode(EMAC_RFC_UCAST_EN, ENABLE);
EMAC_SetFilterMode(EMAC_RFC_BCAST_EN, ENABLE);
EMAC_SetFilterMode(EMAC_RFC_MCAST_EN, ENABLE);
EMAC_SetFilterMode(EMAC_RFC_PERFECT_EN, ENABLE);
EMAC_SetFilterMode(EMAC_RFC_MAGP_WOL_EN, DISABLE);
EMAC_SetFilterMode(EMAC_RFC_PFILT_WOL_EN, DISABLE);
// Init the Ethernt interrupt vecotrs
CSP_IntVectReg((CSP_DEV_NBR )CSP_INT_CTRL_NBR_MAIN,
(CSP_DEV_NBR )CSP_INT_SRC_NBR_ETHER_00,
(CPU_FNCT_PTR )CSP_IntETH_Handler,
(void *)0);
CSP_IntEn(CSP_INT_CTRL_NBR_MAIN, CSP_INT_SRC_NBR_ETHER_00);
EthernetLinkLayer_setMacAddress(macAddress);
Ip_initialize();
Ip_setIPv4Address(ipv4Address);
#endif
#if 0
USBInit(); /* USB Initialization */
/* register descriptors */
USBRegisterDescriptors(abDescriptors); /* USB Descriptor Initialization */
/* register endpoint handlers */
USBHwRegisterEPIntHandler(BULK_IN_EP, BulkIn); /* register BulkIn Handler for EP */
USBHwRegisterEPIntHandler(BULK_OUT_EP, BulkOut); /* register BulkOut Handler for EP */
USBHwRegisterEPIntHandler(INT_IN_EP, NULL);
USBHwEPConfig(BULK_IN_EP, MAX_PACKET_SIZE); /* Configure Packet Size for outgoing Transfer */
USBHwEPConfig(BULK_OUT_EP, MAX_PACKET_SIZE); /* Configure Packet Size for incoming Transfer */
/* enable bulk-in interrupts on NAKs */
USBHwNakIntEnable(INACK_BI);
#endif
//Cb_initialize(&cncQueueBuffer, CNC_QUEUE_BUFFER_SIZE, sizeof(QueueItem), (void*)&cncQueueBufferData);
// Debug_printf(Debug_Level_1, "Init finished");
if(os_err != OS_ERR_NONE)
for(;;);
OSTaskCreate((OS_TCB *)&App_TaskStartTCB, /* Create the Start Task */
(CPU_CHAR *)"Start",
(OS_TASK_PTR )App_TaskStart,
(void *)0,
(OS_PRIO )4,
(CPU_STK *)App_TaskStartStk,
(CPU_STK_SIZE )APP_CFG_TASK_START_STK_SIZE_LIMIT,
(CPU_STK_SIZE )APP_CFG_TASK_START_STK_SIZE,
(OS_MSG_QTY )0u,
(OS_TICK )0u,
(void *)0,
(OS_OPT )(OS_OPT_TASK_STK_CHK | OS_OPT_TASK_STK_CLR),
(OS_ERR *)&os_err);
OSStart(&os_err); /* Start Multitasking */
if(os_err != OS_ERR_NONE) /* shall never get here */
for(;;);
return (0);
}
