// Initialize FlexBus for use until we have main clock.
// Asynchronous mode.
static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
hal_flexbus_init_initial(void)
{
cyghwr_hal_kinetis_fb_t *fb_p = CYGHWR_HAL_KINETIS_FB_P;
CYGHWR_IO_CLOCK_ENABLE(CYGHWR_HAL_KINETIS_SIM_SCGC_FLEXBUS);
# ifdef CYGHWR_HAL_KINETIS_FB_CS0
fb_p->csel[0] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS0_AR,
CYGHWR_HAL_KINETIS_FB_CS0_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(0) };
# endif
# ifdef CYGHWR_HAL_KINETIS_FB_CS1
fb_p->csel[1] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS1_AR,
CYGHWR_HAL_KINETIS_FB_CS1_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(1) };
# endif
# ifdef CYGHWR_HAL_KINETIS_FB_CS2
fb_p->csel[2] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS2_AR,
CYGHWR_HAL_KINETIS_FB_CS2_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(2) };
# endif
# ifdef CYGHWR_HAL_KINETIS_FB_CS3
fb_p->csel[3] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS3_AR,
CYGHWR_HAL_KINETIS_FB_CS3_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(3) };
# endif
# ifdef CYGHWR_HAL_KINETIS_FB_CS4
fb_p->csel[4] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS4_AR,
CYGHWR_HAL_KINETIS_FB_CS4_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(4) };
# endif
# ifdef CYGHWR_HAL_KINETIS_FB_CS4
fb_p->csel[5] = (cyghwr_hal_kinetis_fbcs_t) { CYGHWR_HAL_KINETIS_FB_CS5_AR,
CYGHWR_HAL_KINETIS_FB_CS5_MR, CYGHWR_HAL_KINETIS_FB_CS_CR_IS(5) };
# endif
fb_p->cspmcr = CYGHWR_HAL_FB_CSPMCR_SETSEL;
HAL_SET_PINS(flexbus_pins);
}
static void dspi_bus_setup(cyg_spi_freescale_dspi_bus_t* spi_bus_p)
{
cyghwr_devs_freescale_dspi_t* dspi_p = spi_bus_p->setup_p->dspi_p;
cyghwr_hal_freescale_dma_set_t* dma_set_p;
cyghwr_hal_freescale_edma_t* edma_p;
cyg_uint32 dma_chan_i;
// Set up the clocking.
CYGHWR_IO_CLOCK_ENABLE(spi_bus_p->setup_p->clk_gate);
spi_bus_p->clock_freq = CYGHWR_IO_SPI_FREESCALE_DSPI_CLOCK;
DEBUG1_PRINTF("DSPI BUS %p: SysClk=%d\n", spi_bus_p, spi_bus_p->clock_freq);
// Set up the pins.
dspi_pin_setup(spi_bus_p->setup_p->spi_pin_list_p,
spi_bus_p->setup_p->cs_pin_list_p,
spi_bus_p->setup_p->cs_pin_num);
// Set up default SPI configuration.
dspi_p->mcr = spi_bus_p->setup_p->mcr_opt | FREESCALE_DSPI_MCR_MSTR_M |
FREESCALE_DSPI_MCR_CLR_RXF_M | FREESCALE_DSPI_MCR_CLR_TXF_M |
FREESCALE_DSPI_MCR_MDIS_M;
// Enable DSPI controller.
dspi_enable(dspi_p);
if((dma_set_p=spi_bus_p->setup_p->dma_set_p)) {
// Initialize DMA channels
hal_freescale_edma_init_chanset(dma_set_p);
#if DEBUG_SPI >= 1
hal_freescale_edma_diag(dma_set_p, 0xffff);
cyghwr_devs_freescale_dspi_diag(spi_bus_p);
#endif
// Set up DMA transfer control descriptors
edma_p = dma_set_p->edma_p;
dma_chan_i = dma_set_p->chan_p[SPI_DMA_CHAN_TX_I].dma_chan_i;
hal_freescale_edma_transfer_init(edma_p, dma_chan_i,
spi_bus_p->tx_dma_tcd_ini_p);
#if DEBUG_SPI >= 1
hal_freescale_edma_transfer_diag(edma_p, dma_chan_i, true);
#endif
dma_chan_i = dma_set_p->chan_p[SPI_DMA_CHAN_RX_I].dma_chan_i;
hal_freescale_edma_transfer_init(edma_p, dma_chan_i,
spi_bus_p->rx_dma_tcd_ini_p);
#if DEBUG_SPI >= 1
hal_freescale_edma_transfer_diag(edma_p, dma_chan_i, true);
#endif
}
#if DEBUG_SPI >= 1
cyghwr_devs_freescale_dspi_diag(spi_bus_p);
#endif
// Initialise the synchronisation primitivies.
cyg_drv_mutex_init (&spi_bus_p->transfer_mutex);
cyg_drv_cond_init (&spi_bus_p->transfer_done, &spi_bus_p->transfer_mutex);
// Hook up the ISR and DSR.
cyg_drv_interrupt_create (spi_bus_p->setup_p->intr_num,
spi_bus_p->setup_p->intr_prio,
(cyg_addrword_t) spi_bus_p,
dma_set_p ? dspi_dma_ISR : dspi_nodma_ISR,
dspi_DSR, &spi_bus_p->intr_handle,
&spi_bus_p->intr_data);
cyg_drv_interrupt_attach (spi_bus_p->intr_handle);
dspi_p->ctar[1] = dspi_calc_ctar(&aux_clocking, spi_bus_p->clock_freq);
// Call upper layer bus init.
CYG_SPI_BUS_COMMON_INIT(&spi_bus_p->spi_bus);
}
