/*******************************************************************************
* Function Name: Cy_MCWDT_Init
****************************************************************************//**
*
* Initializes the MCWDT block.
*
* \param base
* The base pointer to a structure that describes the registers.
*
* \param config
* The pointer to a structure that contains component configuration data.
*
* \return cy_en_mcwdt_status_t
* *base checking result. If the pointer is NULL, returns error.
*
* \note
* This API should not be called when the counters are running. Prior to calling
* this API the counter should be disabled.
*
*******************************************************************************/
cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_t const *config)
{
cy_en_mcwdt_status_t ret = CY_MCWDT_BAD_PARAM;
if ((base != NULL) && (config != NULL))
{
CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID(config->c0ClearOnMatch, config->c0Match));
CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID(config->c1ClearOnMatch, config->c1Match));
CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(config->c2ToggleBit));
CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c0Mode));
CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c1Mode));
CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c2Mode));
MCWDT_STRUCT_MCWDT_MATCH(base) = _VAL2FLD(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, config->c1Match) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, config->c0Match);
MCWDT_STRUCT_MCWDT_CONFIG(base) = _VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, config->c2ToggleBit) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2, config->c2Mode) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, config->c0ClearOnMatch) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, config->c1ClearOnMatch) |
(config->c1c2Cascade ? MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Msk : 0UL) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1, config->c1Mode) |
(config->c0c1Cascade ? MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk : 0UL) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0, config->c0Mode);
ret = CY_MCWDT_SUCCESS;
}
return (ret);
}
/*******************************************************************************
* Function Name: Cy_SysInt_Init
****************************************************************************//**
*
* \brief Initializes the referenced interrupt by setting the priority and the
* interrupt vector.
*
* Note that the interrupt vector will only be relocated if the vector table was
* moved to __ramVectors in SRAM. Otherwise it is ignored.
*
* Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt.
*
* \param config
* Interrupt configuration structure
*
* \param userIsr
* Address of the ISR
*
* \return
* Initialization status
*
* \funcusage
* \snippet sysint/sysint_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_SysInt_Init
*
*******************************************************************************/
cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr)
{
cy_en_sysint_status_t status = CY_SYSINT_SUCCESS;
if(NULL != config)
{
CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
#if (CY_CPU_CORTEX_M0P)
if (config->intrSrc > SysTick_IRQn)
{
/* Configure the interrupt mux */
Cy_SysInt_SetIntSource(config->intrSrc, config->cm0pSrc);
}
#endif
NVIC_SetPriority(config->intrSrc, config->intrPriority);
/* Only set the new vector if it was moved to __ramVectors */
if (SCB->VTOR == (uint32_t)&__ramVectors)
{
CY_ASSERT_L1(CY_SYSINT_IS_VECTOR_VALID(userIsr));
(void)Cy_SysInt_SetVector(config->intrSrc, userIsr);
}
}
else
{
status = CY_SYSINT_BAD_PARAM;
}
return(status);
}
/*******************************************************************************
* Function Name: Cy_Crypto_Core_V2_Aes_Init
****************************************************************************//**
*
* Sets AES mode and prepares inverse key.
*
* \param base
* The pointer to the CRYPTO instance.
*
* \param key
* The pointer to the encryption/decryption key.
*
* \param keyLength
* \ref cy_en_crypto_aes_key_length_t
*
* \param aesState
* The pointer to the AES state structure allocated by the user. The user
* must not modify anything in this structure.
*
* \return
* \ref cy_en_crypto_status_t
*
*******************************************************************************/
cy_en_crypto_status_t Cy_Crypto_Core_V2_Aes_Init(CRYPTO_Type *base,
uint8_t const *key,
cy_en_crypto_aes_key_length_t keyLength,
cy_stc_crypto_aes_state_t *aesState)
{
CY_ASSERT_L1(NULL != key);
CY_ASSERT_L1(NULL != aesState);
CY_ASSERT_L3(CY_CRYPTO_IS_KEYLENGTH_VALID(keyLength));
Cy_Crypto_Core_V2_MemSet(base, aesState, 0u, sizeof(cy_stc_crypto_aes_state_t));
aesState->key = (uint8_t *)key;
aesState->keyLength = keyLength;
REG_CRYPTO_AES_CTL(base) = (uint32_t)(_VAL2FLD(CRYPTO_AES_CTL_KEY_SIZE, aesState->keyLength));
return (CY_CRYPTO_SUCCESS);
}
/*******************************************************************************
* Function Name: Cy_DMAC_Descriptor_SetDescriptorType
****************************************************************************//**
*
* Sets the descriptor's type for the specified descriptor.
* Moves the next descriptor pointer and X data count values into the proper
* place in accordance to the actual descriptor type.
* During the descriptor's type changing, the Xloop and Yloop settings, such as
* data count and source/destination increment (i.e. the content of the
* xIncr, ySize and yIncr descriptor registers) might be lost (overriden by the
* next descriptor/X data count values) because of the different descriptor
* registers structures for different descriptor types.
* Set up carefully the Xloop (and Yloop, if used) data count and
* source/destination increment if the descriptor type is changed from a simpler
* to a more complicated type ("single transfer" -> "1D", "1D" -> "2D", etc.).
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
*
* \param descriptorType
* The descriptor type \ref cy_en_dmac_descriptor_type_t.
*
* \funcusage
* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Descriptor_SetNextDescriptor
*
*******************************************************************************/
void Cy_DMAC_Descriptor_SetDescriptorType(cy_stc_dmac_descriptor_t * descriptor, cy_en_dmac_descriptor_type_t descriptorType)
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L3(CY_DMAC_IS_TYPE_VALID(descriptorType));
if (descriptorType != Cy_DMAC_Descriptor_GetDescriptorType(descriptor)) /* Don't perform if the type is not changed */
{
/* Store the current nextDescriptor pointer. */
cy_stc_dmac_descriptor_t * locNextDescriptor = Cy_DMAC_Descriptor_GetNextDescriptor(descriptor);
/* Store the current X data counter. */
uint32_t locXcount = Cy_DMAC_Descriptor_GetXloopDataCount(descriptor);
/* Change the descriptor type. */
CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_DESCR_TYPE, descriptorType);
Cy_DMAC_Descriptor_SetXloopDataCount(descriptor, locXcount);
/* Restore the nextDescriptor pointer into the proper place. */
Cy_DMAC_Descriptor_SetNextDescriptor(descriptor, locNextDescriptor);
}
}
/*******************************************************************************
* Function Name: Cy_DMAC_Descriptor_Init
****************************************************************************//**
*
* Initializes the descriptor structure in SRAM from a pre-initialized
* configuration structure.
* This function initializes only the descriptor and not the channel.
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
*
* \param config
* This is a configuration structure that has all initialization information for
* the descriptor.
*
* \return
* The status /ref cy_en_dmac_status_t.
*
* \funcusage
* \snippet dmac\1.0\snippet\main.c snippet_Cy_DMAC_Enable
*
*******************************************************************************/
cy_en_dmac_status_t Cy_DMAC_Descriptor_Init(cy_stc_dmac_descriptor_t * descriptor, const cy_stc_dmac_descriptor_config_t * config)
{
cy_en_dmac_status_t ret = CY_DMAC_BAD_PARAM;
if ((NULL != descriptor) && (NULL != config))
{
CY_ASSERT_L3(CY_DMAC_IS_RETRIGGER_VALID(config->retrigger));
CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->interruptType));
CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->triggerOutType));
CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->triggerInType));
CY_ASSERT_L3(CY_DMAC_IS_XFER_SIZE_VALID(config->srcTransferSize));
CY_ASSERT_L3(CY_DMAC_IS_XFER_SIZE_VALID(config->dstTransferSize));
CY_ASSERT_L3(CY_DMAC_IS_CHANNEL_STATE_VALID(config->channelState));
CY_ASSERT_L3(CY_DMAC_IS_DATA_SIZE_VALID(config->dataSize));
CY_ASSERT_L3(CY_DMAC_IS_TYPE_VALID(config->descriptorType));
descriptor->ctl =
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT, config->retrigger) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_INTR_TYPE, config->interruptType) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE, config->triggerOutType) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE, config->triggerInType) |
_BOOL2FLD(DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH, config->dataPrefetch) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE, config->srcTransferSize) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE, config->dstTransferSize) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_CH_DISABLE, config->channelState) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_DATA_SIZE, config->dataSize) |
_VAL2FLD(DMAC_CH_V2_DESCR_CTL_DESCR_TYPE, config->descriptorType);
descriptor->src = (uint32_t)config->srcAddress;
switch(config->descriptorType)
{
case CY_DMAC_SINGLE_TRANSFER:
{
descriptor->dst = (uint32_t)config->dstAddress;
descriptor->xSize = (uint32_t)config->nextDescriptor;
break;
}
case CY_DMAC_1D_TRANSFER:
{
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->srcXincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->dstXincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_COUNT_VALID(config->xCount));
descriptor->dst = (uint32_t)config->dstAddress;
/* Convert the data count from the user's range (1-65536) into the machine range (0-65535). */
descriptor->xSize = _VAL2FLD(DMAC_CH_V2_DESCR_X_SIZE_X_COUNT, config->xCount - 1UL);
descriptor->xIncr = _VAL2FLD(DMAC_CH_V2_DESCR_X_INCR_SRC_X, config->srcXincrement) |
_VAL2FLD(DMAC_CH_V2_DESCR_X_INCR_DST_X, config->dstXincrement);
descriptor->ySize = (uint32_t)config->nextDescriptor;
break;
}
case CY_DMAC_2D_TRANSFER:
{
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->srcXincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->dstXincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_COUNT_VALID(config->xCount));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->srcYincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->dstYincrement));
CY_ASSERT_L2(CY_DMAC_IS_LOOP_COUNT_VALID(config->yCount));
descriptor->dst = (uint32_t)config->dstAddress;
/* Convert the data count from the user's range (1-65536) into the machine range (0-65535). */
descriptor->xSize = _VAL2FLD(DMAC_CH_V2_DESCR_X_SIZE_X_COUNT, config->xCount - 1UL);
descriptor->xIncr = _VAL2FLD(DMAC_CH_V2_DESCR_X_INCR_SRC_X, config->srcXincrement) |
_VAL2FLD(DMAC_CH_V2_DESCR_X_INCR_DST_X, config->dstXincrement);
/* Convert the data count from the user's range (1-65536) into the machine range (0-65535). */
descriptor->ySize = _VAL2FLD(DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT, config->yCount - 1UL);
descriptor->yIncr = _VAL2FLD(DMAC_CH_V2_DESCR_Y_INCR_SRC_Y, config->srcYincrement) |
_VAL2FLD(DMAC_CH_V2_DESCR_Y_INCR_DST_Y, config->dstYincrement);
descriptor->nextPtr = (uint32_t)config->nextDescriptor;
break;
}
case CY_DMAC_MEMORY_COPY:
{
CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->srcXincrement));
descriptor->dst = (uint32_t)config->dstAddress;
/* Convert the data count from the user's range (1-65536) into the machine range (0-65535). */
descriptor->xSize = _VAL2FLD(DMAC_CH_V2_DESCR_X_SIZE_X_COUNT, config->xCount - 1UL);
descriptor->xIncr = (uint32_t)config->nextDescriptor;
break;
}
case CY_DMAC_SCATTER_TRANSFER:
{
/* Convert the data count from the user's range (1-65536) into the machine range (0-65535). */
descriptor->dst = _VAL2FLD(DMAC_CH_V2_DESCR_X_SIZE_X_COUNT, config->xCount - 1UL);
descriptor->xSize = (uint32_t)config->nextDescriptor;
break;
}
default:
{
/* An unsupported type of a descriptor */
break;
}
}
ret = CY_DMAC_SUCCESS;
}
return ret;
}
/*******************************************************************************
* Function Name: Cy_SCB_EZI2C_Init
****************************************************************************//**
*
* Initializes the SCB for the EZI2C operation.
*
* \param base
* The pointer to the EZI2C SCB instance.
*
* \param config
* The pointer to the configuration structure \ref cy_stc_scb_ezi2c_config_t.
*
* \param context
* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t
* allocated by the user. The structure is used during the EZI2C operation for
* internal configuration and data retention. The user must not modify anything
* in this structure.
*
* \return
* \ref cy_en_scb_ezi2c_status_t
*
* \note
* Ensure that the SCB block is disabled before calling this function.
*
*******************************************************************************/
cy_en_scb_ezi2c_status_t Cy_SCB_EZI2C_Init(CySCB_Type *base, cy_stc_scb_ezi2c_config_t const *config,
cy_stc_scb_ezi2c_context_t *context)
{
/* Input parameters verification */
if ((NULL == base) || (NULL == config) || (NULL == context))
{
return CY_SCB_EZI2C_BAD_PARAM;
}
CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(config->slaveAddress1));
CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(config->slaveAddress2));
CY_ASSERT_L2(config->slaveAddress1 != config->slaveAddress2);
CY_ASSERT_L3(CY_SCB_EZI2C_IS_NUM_OF_ADDR_VALID (config->numberOfAddresses));
CY_ASSERT_L3(CY_SCB_EZI2C_IS_SUB_ADDR_SIZE_VALID(config->subAddressSize));
/* Configure the EZI2C interface */
base->CTRL = _BOOL2FLD(SCB_CTRL_ADDR_ACCEPT, (config->numberOfAddresses == CY_SCB_EZI2C_TWO_ADDRESSES)) |
_BOOL2FLD(SCB_CTRL_EC_AM_MODE, config->enableWakeFromSleep) |
SCB_CTRL_BYTE_MODE_Msk;
base->I2C_CTRL = CY_SCB_EZI2C_I2C_CTRL;
/* Configure the RX direction */
base->RX_CTRL = CY_SCB_EZI2C_RX_CTRL;
base->RX_FIFO_CTRL = 0UL;
/* Set the default address and mask */
if (config->numberOfAddresses == CY_SCB_EZI2C_ONE_ADDRESS)
{
context->address2 = 0U;
Cy_SCB_EZI2C_SetAddress1(base, config->slaveAddress1, context);
}
else
{
Cy_SCB_EZI2C_SetAddress1(base, config->slaveAddress1, context);
Cy_SCB_EZI2C_SetAddress2(base, config->slaveAddress2, context);
}
/* Configure the TX direction */
base->TX_CTRL = CY_SCB_EZI2C_TX_CTRL;
base->TX_FIFO_CTRL = CY_SCB_EZI2C_HALF_FIFO_SIZE;
/* Configure the interrupt sources */
base->INTR_SPI_EC_MASK = 0UL;
base->INTR_I2C_EC_MASK = 0UL;
base->INTR_RX_MASK = 0UL;
base->INTR_TX_MASK = 0UL;
base->INTR_M_MASK = 0UL;
base->INTR_S_MASK = CY_SCB_EZI2C_SLAVE_INTR;
/* Initialize the context */
context->status = 0UL;
context->state = CY_SCB_EZI2C_STATE_IDLE;
context->subAddrSize = config->subAddressSize;
context->buf1Size = 0UL;
context->buf1rwBondary = 0UL;
context->baseAddr1 = 0UL;
context->buf1Size = 0UL;
context->buf1rwBondary = 0UL;
context->baseAddr2 = 0UL;
return CY_SCB_EZI2C_SUCCESS;
}
