void
CourseGetName(UInt16 courseID, MemHandle *charHandle, Boolean longformat)
{
if (! CacheValid(gCourseNameCacheID)) {
// Cache has not yet been initialized
gCourseNameCacheID = CacheRegister(CourseNameCacheNumI, CourseNameCacheLoad, CourseNameCacheFree);
}
CacheGet(gCourseNameCacheID, courseID, charHandle, longformat ? 0 : 3);
}
/*
* ATIMach64Sync --
*
* This is called to wait for the draw engine to become idle.
*/
void
ATIMach64Sync
(
ScrnInfoPtr pScreenInfo
)
{
ATIPtr pATI = ATIPTR(pScreenInfo);
#ifdef XF86DRI_DEVEL
if ( pATI->directRenderingEnabled && pATI->NeedDRISync )
{
ATIHWPtr pATIHW = &pATI->NewHW;
if (pATI->OptionMMIOCache) {
/* "Invalidate" the MMIO cache so the cache slots get updated */
UncacheRegister(SRC_CNTL);
UncacheRegister(HOST_CNTL);
UncacheRegister(PAT_CNTL);
UncacheRegister(SC_LEFT_RIGHT);
UncacheRegister(SC_TOP_BOTTOM);
UncacheRegister(DP_BKGD_CLR);
UncacheRegister(DP_FRGD_CLR);
UncacheRegister(DP_WRITE_MASK);
UncacheRegister(DP_MIX);
UncacheRegister(CLR_CMP_CNTL);
}
ATIDRIWaitForIdle(pATI);
outr( BUS_CNTL, pATIHW->bus_cntl );
/* DRI uses GUI_TRAJ_CNTL, which is a composite of
* src_cntl, dst_cntl, pat_cntl, and host_cntl
*/
outf( SRC_CNTL, pATIHW->src_cntl );
outf( DST_CNTL, pATIHW->dst_cntl );
outf( PAT_CNTL, pATIHW->pat_cntl );
outf( HOST_CNTL, pATIHW->host_cntl );
outf( DST_OFF_PITCH, pATIHW->dst_off_pitch );
outf( SRC_OFF_PITCH, pATIHW->src_off_pitch );
outf( DP_SRC, pATIHW->dp_src );
outf( DP_MIX, pATIHW->dp_mix );
outf( DP_FRGD_CLR, pATIHW->dp_frgd_clr );
outf( DP_WRITE_MASK, pATIHW->dp_write_mask );
outf( DP_PIX_WIDTH, pATIHW->dp_pix_width );
outf( CLR_CMP_CNTL, pATIHW->clr_cmp_cntl );
outf( ALPHA_TST_CNTL, 0 );
outf( Z_CNTL, 0 );
outf( SCALE_3D_CNTL, 0 );
ATIMach64WaitForFIFO(pATI, 2);
outf( SC_LEFT_RIGHT,
SetWord(pATIHW->sc_right, 1) | SetWord(pATIHW->sc_left, 0) );
outf( SC_TOP_BOTTOM,
SetWord(pATIHW->sc_bottom, 1) | SetWord(pATIHW->sc_top, 0) );
if (pATI->OptionMMIOCache) {
/* Now that the cache slots reflect the register state, re-enable MMIO cache */
CacheRegister(SRC_CNTL);
CacheRegister(HOST_CNTL);
CacheRegister(PAT_CNTL);
CacheRegister(SC_LEFT_RIGHT);
CacheRegister(SC_TOP_BOTTOM);
CacheRegister(DP_BKGD_CLR);
CacheRegister(DP_FRGD_CLR);
CacheRegister(DP_WRITE_MASK);
CacheRegister(DP_MIX);
CacheRegister(CLR_CMP_CNTL);
}
ATIMach64WaitForIdle(pATI);
if (pATI->OptionMMIOCache && pATI->OptionTestMMIOCache) {
/* Only check registers we didn't restore */
TestRegisterCaching(PAT_REG0);
TestRegisterCaching(PAT_REG1);
TestRegisterCaching(CLR_CMP_CLR);
TestRegisterCaching(CLR_CMP_MSK);
if (pATI->Block1Base)
{
TestRegisterCaching(OVERLAY_Y_X_START);
TestRegisterCaching(OVERLAY_Y_X_END);
TestRegisterCaching(OVERLAY_GRAPHICS_KEY_CLR);
TestRegisterCaching(OVERLAY_GRAPHICS_KEY_MSK);
TestRegisterCaching(OVERLAY_KEY_CNTL);
TestRegisterCaching(OVERLAY_SCALE_INC);
TestRegisterCaching(OVERLAY_SCALE_CNTL);
TestRegisterCaching(SCALER_HEIGHT_WIDTH);
TestRegisterCaching(SCALER_TEST);
TestRegisterCaching(VIDEO_FORMAT);
if (pATI->Chip < ATI_CHIP_264VTB)
{
TestRegisterCaching(BUF0_OFFSET);
TestRegisterCaching(BUF0_PITCH);
TestRegisterCaching(BUF1_OFFSET);
TestRegisterCaching(BUF1_PITCH);
}
else
{
TestRegisterCaching(SCALER_BUF0_OFFSET);
TestRegisterCaching(SCALER_BUF1_OFFSET);
TestRegisterCaching(SCALER_BUF_PITCH);
TestRegisterCaching(OVERLAY_EXCLUSIVE_HORZ);
TestRegisterCaching(OVERLAY_EXCLUSIVE_VERT);
if (pATI->Chip >= ATI_CHIP_264GTPRO)
{
TestRegisterCaching(SCALER_COLOUR_CNTL);
TestRegisterCaching(SCALER_H_COEFF0);
TestRegisterCaching(SCALER_H_COEFF1);
TestRegisterCaching(SCALER_H_COEFF2);
TestRegisterCaching(SCALER_H_COEFF3);
TestRegisterCaching(SCALER_H_COEFF4);
TestRegisterCaching(SCALER_BUF0_OFFSET_U);
TestRegisterCaching(SCALER_BUF0_OFFSET_V);
TestRegisterCaching(SCALER_BUF1_OFFSET_U);
TestRegisterCaching(SCALER_BUF1_OFFSET_V);
}
}
}
}
pATI->NeedDRISync = FALSE;
}
else
#endif /* XF86DRI_DEVEL */
{
ATIMach64WaitForIdle(pATI);
if (pATI->OptionMMIOCache && pATI->OptionTestMMIOCache)
{
/*
* For debugging purposes, attempt to verify that each cached register
* should actually be cached.
*/
TestRegisterCaching(SRC_CNTL);
TestRegisterCaching(HOST_CNTL);
TestRegisterCaching(PAT_REG0);
TestRegisterCaching(PAT_REG1);
TestRegisterCaching(PAT_CNTL);
if (RegisterIsCached(SC_LEFT_RIGHT) && /* Special case */
(CacheSlot(SC_LEFT_RIGHT) !=
(SetWord(inm(SC_RIGHT), 1) | SetWord(inm(SC_LEFT), 0))))
{
UncacheRegister(SC_LEFT_RIGHT);
xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
"SC_LEFT_RIGHT write cache disabled!\n");
}
if (RegisterIsCached(SC_TOP_BOTTOM) && /* Special case */
(CacheSlot(SC_TOP_BOTTOM) !=
(SetWord(inm(SC_BOTTOM), 1) | SetWord(inm(SC_TOP), 0))))
{
UncacheRegister(SC_TOP_BOTTOM);
xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
"SC_TOP_BOTTOM write cache disabled!\n");
}
TestRegisterCaching(DP_BKGD_CLR);
TestRegisterCaching(DP_FRGD_CLR);
TestRegisterCaching(DP_WRITE_MASK);
TestRegisterCaching(DP_MIX);
TestRegisterCaching(CLR_CMP_CLR);
TestRegisterCaching(CLR_CMP_MSK);
TestRegisterCaching(CLR_CMP_CNTL);
if (pATI->Block1Base)
{
TestRegisterCaching(OVERLAY_Y_X_START);
TestRegisterCaching(OVERLAY_Y_X_END);
TestRegisterCaching(OVERLAY_GRAPHICS_KEY_CLR);
TestRegisterCaching(OVERLAY_GRAPHICS_KEY_MSK);
TestRegisterCaching(OVERLAY_KEY_CNTL);
TestRegisterCaching(OVERLAY_SCALE_INC);
TestRegisterCaching(OVERLAY_SCALE_CNTL);
TestRegisterCaching(SCALER_HEIGHT_WIDTH);
TestRegisterCaching(SCALER_TEST);
TestRegisterCaching(VIDEO_FORMAT);
if (pATI->Chip < ATI_CHIP_264VTB)
{
TestRegisterCaching(BUF0_OFFSET);
TestRegisterCaching(BUF0_PITCH);
TestRegisterCaching(BUF1_OFFSET);
TestRegisterCaching(BUF1_PITCH);
}
else
{
TestRegisterCaching(SCALER_BUF0_OFFSET);
TestRegisterCaching(SCALER_BUF1_OFFSET);
TestRegisterCaching(SCALER_BUF_PITCH);
TestRegisterCaching(OVERLAY_EXCLUSIVE_HORZ);
TestRegisterCaching(OVERLAY_EXCLUSIVE_VERT);
if (pATI->Chip >= ATI_CHIP_264GTPRO)
{
TestRegisterCaching(SCALER_COLOUR_CNTL);
TestRegisterCaching(SCALER_H_COEFF0);
TestRegisterCaching(SCALER_H_COEFF1);
TestRegisterCaching(SCALER_H_COEFF2);
TestRegisterCaching(SCALER_H_COEFF3);
TestRegisterCaching(SCALER_H_COEFF4);
TestRegisterCaching(SCALER_BUF0_OFFSET_U);
TestRegisterCaching(SCALER_BUF0_OFFSET_V);
TestRegisterCaching(SCALER_BUF1_OFFSET_U);
TestRegisterCaching(SCALER_BUF1_OFFSET_V);
}
}
}
}
}
/*
* For VTB's and later, the first CPU read of the framebuffer will return
* zeroes, so do it here. This appears to be due to some kind of engine
* caching of framebuffer data I haven't found any way of disabling, or
* otherwise circumventing. Thanks to Mark Vojkovich for the suggestion.
*/
if (pATI->pXAAInfo)
pATI->pXAAInfo->NeedToSync = FALSE;
pATI = *(volatile ATIPtr *)pATI->pMemory;
}
