/* Get divider value */
STATIC uint8_t getClkDiv(LPC_ADC_T *pADC, bool burstMode, uint32_t adcRate, uint8_t clks)
{
	uint32_t adcBlockFreq;
	uint32_t fullAdcRate;
	uint8_t div;

	/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
	   A/D converter, which should be less than or equal to 4.5MHz.
	   A fully conversion requires (bits_accuracy+1) of these clocks.
	   ADC Clock = PCLK_ADC0 / (CLKDIV + 1);
	   ADC rate = ADC clock / (the number of clocks required for each conversion);
	 */
#if defined(CHIP_LPC175X_6X)
	adcBlockFreq = Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_ADC);
#else
	adcBlockFreq = Chip_Clock_GetPeripheralClockRate();
#endif
#if defined(ADC_ACC_12BITS)
	fullAdcRate = adcRate * getFullConvClk();
#else
	if (burstMode) {
		fullAdcRate = adcRate * clks;
	}
	else {
		fullAdcRate = adcRate * getFullConvClk();
	}
#endif
	/* Get the round value by fomular: (2*A + B)/(2*B) */
	div = ((adcBlockFreq * 2 + fullAdcRate) / (fullAdcRate * 2)) - 1;
	return div;
}
Beispiel #2
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static void initHardware(void)
{
    SystemCoreClockUpdate();
    SysTick_Config(SystemCoreClock/1000);
    Board_Init();
    Board_LED_Set(0, false);

    /* Timer */
    Chip_TIMER_Init(LPC_TIMER1);
    Chip_TIMER_PrescaleSet(LPC_TIMER1,
#ifdef lpc1769
                           Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_TIMER1) / 1000000 - 1
#else
                           Chip_Clock_GetRate(CLK_MX_TIMER1) / 1000000 - 1
#endif
                          );

    /* Match 0 (period) */
    Chip_TIMER_MatchEnableInt(LPC_TIMER1, 0);
    Chip_TIMER_ResetOnMatchEnable(LPC_TIMER1, 0);
    Chip_TIMER_StopOnMatchDisable(LPC_TIMER1, 0);
    Chip_TIMER_SetMatch(LPC_TIMER1, 0, 1000);

    /* Match 1 (duty) */
    Chip_TIMER_MatchEnableInt(LPC_TIMER1, 1);
    Chip_TIMER_ResetOnMatchDisable(LPC_TIMER1, 1);
    Chip_TIMER_StopOnMatchDisable(LPC_TIMER1, 1);
    Chip_TIMER_SetMatch(LPC_TIMER1, 1, 100);

    Chip_TIMER_Reset(LPC_TIMER1);
    Chip_TIMER_Enable(LPC_TIMER1);

    NVIC_EnableIRQ(TIMER1_IRQn);
}
Beispiel #3
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static uint32_t Chip_UART_GetClockRate(LPC_USART_T *pUART) {
#if !defined(CHIP_LPC175X_6X)
	return Chip_Clock_GetPeripheralClockRate();
#else
	/* Pick clock for uart BASED ON SELECTED uart */
	if (pUART == LPC_UART1) {
		return Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_UART1);
	}
	else if (pUART == LPC_UART2) {
		return Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_UART2);
	}
	else if (pUART == LPC_UART3) {
		return Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_UART3);
	}
	else {
		return Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_UART0);
	}
#endif
}
/* Set SD_CLK Clock */
void Chip_SDC_SetClock(LPC_SDC_T *pSDC, uint32_t freq)
{
	uint32_t PClk;
	uint32_t ClkValue = 0;

	PClk = Chip_Clock_GetPeripheralClockRate();

	ClkValue = (PClk + 2 * freq - 1) / (2 * freq);
	if (ClkValue > 0) {
		ClkValue -= 1;
	}
	Chip_SDC_SetClockDiv(pSDC, ClkValue);
}
Beispiel #5
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/* Get divider value for  */
STATIC uint8_t getAdcClkDiv(uint32_t adcRate)
{
	uint32_t adcBlockFreq;
	uint32_t fullAdcRate;
	uint8_t div;

	/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
	 * A/D converter, which should be less than or equal to 12.4MHz.
	 * A fully conversion requires 31 of these clocks.
	 * ADC clock = PCLK_ADC0 / (CLKDIV + 1);
	 * ADC rate = ADC clock / (the number of clocks required for each conversion);
	 */
#if defined(CHIP_LPC175X_6X)
	adcBlockFreq = Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_ADC);
	fullAdcRate = adcRate * 65;
#else
	adcBlockFreq = Chip_Clock_GetPeripheralClockRate();
	fullAdcRate = adcRate * 31;
#endif

	/* Get the round value by fomular: (2*A + B)/(2*B) */
	div = ((adcBlockFreq * 2 + fullAdcRate) / (fullAdcRate * 2)) - 1;
	return div;
}
Beispiel #6
0
/* Configure I2S for Audio Format input */
Status Chip_I2S_Config(LPC_I2S_T *pI2S, uint8_t TRMode, Chip_I2S_Audio_Format_T *audio_format)
{
	uint32_t pClk;
	uint32_t x, y;
	uint64_t divider;
	uint16_t dif;
	uint16_t x_divide = 0, y_divide = 0;
	uint32_t N;
	uint16_t err, ErrorOptimal = 0xFFFF;

	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_I2S);
#if defined(CHIP_LPC175X_6X)
	pClk = Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_I2S);
#else
	pClk = Chip_Clock_GetPeripheralClockRate();
#endif

	/* divider is a fixed point number with 16 fractional bits */
	divider = (((uint64_t) (audio_format->SampleRate) * 2 * (audio_format->WordWidth) * 2) << 16) / pClk;
	/* find N that make x/y <= 1 -> divider <= 2^16 */
	for (N = 64; N > 0; N--) {
		if ((divider * N) < (1 << 16)) {
			break;
		}
	}
	if (N == 0) {
		return ERROR;
	}
	divider *= N;
	for (y = 255; y > 0; y--) {
		x = y * divider;
		if (x & (0xFF000000)) {
			continue;
		}
		dif = x & 0xFFFF;
		if (dif > 0x8000) {
			err = 0x10000 - dif;
		}
		else {
			err = dif;
		}
		if (err == 0) {
			y_divide = y;
			break;
		}
		else if (err < ErrorOptimal) {
			ErrorOptimal = err;
			y_divide = y;
		}
	}
	x_divide = ((uint64_t) y_divide * (audio_format->SampleRate) * 2 * (audio_format->WordWidth) * N * 2) / pClk;
	if (x_divide >= 256) {
		x_divide = 0xFF;
	}
	if (x_divide == 0) {
		x_divide = 1;
	}
	if (audio_format->WordWidth <= 8) {
		IP_I2S_SetWordWidth(pI2S, TRMode, I2S_WORDWIDTH_8);
	}
	else if (audio_format->WordWidth <= 16) {
		IP_I2S_SetWordWidth(pI2S, TRMode, I2S_WORDWIDTH_16);
	}
	else {
		IP_I2S_SetWordWidth(pI2S, TRMode, I2S_WORDWIDTH_32);
	}
	IP_I2S_SetMono(pI2S, TRMode, (audio_format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO);
	IP_I2S_SetMasterSlaveMode(pI2S, TRMode, I2S_MASTER_MODE);
	IP_I2S_SetWS_Halfperiod(pI2S, TRMode, audio_format->WordWidth - 1);
	IP_I2S_ModeConfig(pI2S, TRMode, I2S_TXMODE_CLKSEL(0), !I2S_TXMODE_4PIN_ENABLE, !I2S_TXMODE_MCENA);
	IP_I2S_SetBitRate(pI2S, TRMode, N - 1);
	IP_I2S_SetXYDivider(pI2S, TRMode, x_divide, y_divide);
	return SUCCESS;
}