void SetupSystemRegs(void) { unsigned int nTimer; // Set FER regs to MUX in Ethernet pins // MUX these pins to Ethernet #if (__SILICON_REVISION__ < 0x0001) // Workaround silicon anomaly 05000212 u32 temp = *pPORTH_FER; *pPORTH_FER = 0xffff; #endif *pPORTH_FER = 0xffff; // Program EMAC2 System Control Reg // set MDC clock divisor (min period is 400 ns) // sysctl = EMAC2_MDCDIV(26); // %54 for 132 MHz SCLK // sysctl = EMAC2_MDCDIV(10); // %22 for 54 MHz SCLK // sysctl = SET_MDCDIV(23); // %23 for 120 MHz SCLK //KG *pEMAC_SYSCTL = ( (SET_MDCDIV(23)) | RXCKS | RXDWA); WrPHYReg(BR_BUB_PHYADD, PHY_CNTL_REG, PHY_CNTL_RST); // ulEndTime = (GetTickCount() + 10000); // do{ // asm("nop;"); // }while( (PHY_CNTL_RST & RdPHYReg(BR_BUB_PHYADD, PHY_CNTL_REG)) && (GetTickCount() < ulEndTime) ); nTimer = SetTimeout(10000); if( ((unsigned int)-1) != nTimer ) { do{ asm("nop;"); }while( (PHY_CNTL_RST & RdPHYReg(BR_BUB_PHYADD, PHY_CNTL_REG)) && (!IsTimedout(nTimer)) ); } ClearTimeout(nTimer); // The status register (reg 1) should read 0x7809 to show no link detected // Program PHY registers WrPHYReg(BR_BUB_PHYADD, PHY_CNTL_REG, (PHY_CNTL_DPLX|PHY_CNTL_ANEG_RST|PHY_CNTL_SPEED) ); // stay here until the link is detected // ulEndTime = (GetTickCount() + 10000); // do{ // asm("nop;"); // }while ( ((PHY_STAT_LINK & RdPHYReg(BR_BUB_PHYADD, PHY_STAT_REG)) == 0) && (GetTickCount() < ulEndTime) ); nTimer = SetTimeout(10000); if( ((unsigned int)-1) != nTimer ) { do{ asm("nop;"); }while ( ((PHY_STAT_LINK & RdPHYReg(BR_BUB_PHYADD, PHY_STAT_REG)) == 0) && (!IsTimedout(nTimer)) ); } ClearTimeout(nTimer); }
bool I2C::IsError() { bool isError = false; if (IsARLO()) { ClearARLO(); isError = true; ++_errorCountARLO; } if (IsAF()) { ClearAF(); isError = true; ++_errorCountAF; } if (IsTimeout()) { ClearTimeout(); isError = true; ++_errorCountTO; } if (IsBusError()) { ClearBusError(); isError = true; ++_errorCountBE; } return isError; }
void I2C::HandleErrorInterrupt() { if (_irqErrorHandler) { I2C_IRQ_Error_Info info; if (IsBusError()) { info.BusError = true; ClearBusError(); } if (IsARLO()) { info.ArbitrationLoss = true; ClearARLO(); } if (IsAF()) { info.AckFailure = true; ClearAF(); } if (IsOVR()) { info.OverrunUnderrun = true; ClearOVR(); } if (IsPECError()) { info.PECError = true; ClearPECERR(); } if (IsTimeout()) { info.Timeout = true; ClearTimeout(); } if (IsSMBAlert()) { info.SMBAlert = true; ClearSMBAlert(); } _irqErrorHandler->HandleErrorInterrupt(this, info); } }
void PollMdcDone(void) { /* unsigned long ulEndTime = (GetTickCount() + 10000); // poll the STABUSY bit do{ asm("nop;"); }while( ((*pEMAC_STAADD) & STABUSY) && (GetTickCount() < ulEndTime) ); */ unsigned int nTimer = SetTimeout(10000); if( ((unsigned int)-1) != nTimer ) { // poll the STABUSY bit do{ asm("nop;"); }while( ((*pEMAC_STAADD) & STABUSY) && (!IsTimedout(nTimer)) ); } ClearTimeout(nTimer); }
int LanTest() { int iResult = 1; //unsigned long ulEndTime; unsigned int nTimer; ADI_ETHER_BUFFER *txbuf = NULL; ADI_ETHER_BUFFER *txfst = NULL; ADI_ETHER_BUFFER *txlst = NULL; ADI_ETHER_BUFFER *rxfst = NULL; ADI_ETHER_BUFFER *rxbuf = NULL; ADI_ETHER_BUFFER *rxlst = NULL; int ib; int irxh; int itxh; int RxCounter = 0; u32 txstatus; u32 rxstatus; // first, we setup various non-EMAC stuff SetupSystemRegs(); // next, we set up a MAC ADDRESS SetupMacAddr(g_SrcAddr); // initialize the TX DMA channel registers *pDMA2_X_COUNT = 0; *pDMA2_X_MODIFY = 4; // initialize the RX DMA channel registers *pDMA1_X_COUNT = 0; *pDMA1_X_MODIFY = 4; // set up a transmit frames and form a chain of them txlst = NULL; txfst = NULL; for( ib = 0; ib < NO_TX_BUFS; ib++ ) { txbuf = SetupTxBuffer(TXFRM_SIZE,ib); if( NULL == txbuf ) { // memory allocation failed return 0; } if (txfst==NULL) txfst = txbuf; if (txlst != NULL) { txlst->pNext = txbuf; // chain this buffer on txlst->Dma[1].NEXT_DESC_PTR = &txbuf->Dma[0]; // chain the descriptors txlst->Dma[1].CONFIG.b_NDSIZE = 5; // five elements txlst->Dma[1].CONFIG.b_FLOW = 7; // large descriptors } txlst = txbuf; } // loop the transmit chain txlst->Dma[1].NEXT_DESC_PTR = &txfst->Dma[0]; txlst->Dma[1].CONFIG.b_NDSIZE = 5; // five elements txlst->Dma[1].CONFIG.b_FLOW = 7; // large descriptors txlst->pNext = txfst; // set up a receive frames and form a chain of them rxlst = NULL; rxfst = NULL; for (ib=0;ib<NO_RX_BUFS;ib++) { rxbuf = SetupRxBuffer(); if( NULL == rxbuf ) { // memory allocation failed return 0; } if (rxfst==NULL) rxfst = rxbuf; if (rxlst != NULL) { rxlst->pNext = rxbuf; // chain this buffer on rxlst->Dma[1].NEXT_DESC_PTR = &rxbuf->Dma[0]; // chain the descriptors rxlst->Dma[1].CONFIG.b_NDSIZE = 5; // five elements rxlst->Dma[1].CONFIG.b_FLOW = 7; // large descriptors } rxlst = rxbuf; } // loop the receive chain rxlst->Dma[1].NEXT_DESC_PTR = &rxfst->Dma[0]; rxlst->Dma[1].CONFIG.b_NDSIZE = 5; // five elements rxlst->Dma[1].CONFIG.b_FLOW = 7; // large descriptors rxlst->pNext = rxfst; // start the TX DMA channel before enabling the MAC txbuf = txfst; if (txfst != NULL) { *pDMA2_NEXT_DESC_PTR = &txfst->Dma[0]; *pDMA2_CONFIG = *((u16*)&txfst->Dma[0].CONFIG); } // start the RX DMA channel before enabling the MAC rxbuf = rxfst; if (rxfst != NULL) { *pDMA1_NEXT_DESC_PTR = &rxfst->Dma[0]; *pDMA1_CONFIG = *((u16*)&rxfst->Dma[0].CONFIG); } // reset counters, allow rollover, enable counters *pEMAC_MMC_CTL = RSTC | CROLL | MMCE; // finally enable sending/receiving at the mac PollMdcDone(); // enable RX, TX, and full duplex *pEMAC_OPMODE = (TE | RE | FDMODE); // now poll for completion on the tx and rx buffers txbuf = txfst; itxh = 0; rxbuf = rxfst; irxh = 0; // ulEndTime = (GetTickCount() + 0x200000); nTimer = SetTimeout(0x200000); while ( ((rxbuf!=NULL) || (txbuf!=NULL)) ) { if( IsTimedout(nTimer) ) { iResult = 0; break; } else { if ((txbuf != NULL) && ((txbuf->StatusWord & TX_COMP) !=0)) { // enable the transmit DMA for the sending the next packets PollMdcDone(); if( NO_TX_BUFS > 0 ) { *pEMAC_OPMODE &= (~TE); } // frame marked as transmitted txstatus = txbuf->StatusWord; // save the status txbuf->StatusWord = 0; if(TX_OK != (txstatus & TX_OK) ) { iResult = 0; break; } txbuf = txbuf->pNext; // store current status in history list if (++itxh >= NO_TX_BUFS) { itxh = 0; } // enable the transmit DMA for the sending the next packets // start the TX DMA channel before enabling the MAC txbuf = txfst; if (txfst != NULL) { *pDMA2_NEXT_DESC_PTR = &txfst->Dma[0]; *pDMA2_CONFIG = *((u16*)&txfst->Dma[0].CONFIG); } PollMdcDone(); if( NO_TX_BUFS > 0 ) { *pEMAC_OPMODE |= TE; } } if ((rxbuf != NULL) && ((rxbuf->StatusWord & RX_COMP) !=0)) { // frame marked as received rxstatus = rxbuf->StatusWord; // save the status rxbuf->StatusWord = 0; if( rxstatus & RX_OK ) { // recvved OK memcpy(g_rx_src_addr,rxbuf->Data->Srce,6); RxCounter++; if ((RxCounter % 1000000) == 0x0) { iResult = 1; break; } memset(g_rx_src_addr,0x0,6); } else { iResult = 0; break; } rxbuf = rxbuf->pNext; if (++irxh >= NO_RX_BUFS) { irxh = 0; } } }// end else(tickcount) } ClearTimeout(nTimer); *pEMAC_OPMODE = 0; if( iResult ) { // this will verify that the correct PHY address is being used if( 0xFFFF == RdPHYReg(BR_BUB_PHYADD, 31) ) { iResult = 0; } } // delete the tx & rx buffers { ADI_ETHER_BUFFER *pHead; ADI_ETHER_BUFFER *pTemp = txfst; do{ pHead = pTemp; pTemp = pHead->pNext; pHead->pNext = NULL; memset(pHead, 0x00, sizeof(ADI_ETHER_BUFFER) ); free(pHead); }while( NULL != pTemp->pNext ); pTemp = rxfst; do{ pHead = pTemp; pTemp = pHead->pNext; pHead->pNext = NULL; memset(pHead, 0x00, sizeof(ADI_ETHER_BUFFER) ); free(pHead); }while( NULL != pTemp->pNext ); } return iResult; }