#include "de_clock.h"
static u32 de_base = 0;
static de_clk_para de_clk_tbl[] =
{
/* mod_id freq bus reset dram gate div */
DE_TOP_CFG(DE_CLK_CORE0, 250000000, 0x04, 0, 0x08, 0, 0x00, 32, 0x00, 0, 0x0c, 0, 4)
DE_TOP_CFG(DE_CLK_CORE1, 250000000, 0x04, 1, 0x08, 2, 0x00, 32, 0x00, 1, 0x0c, 4, 4)
DE_TOP_CFG(DE_CLK_WB, 250000000, 0x04, 2, 0x08, 2, 0x00, 32, 0x00, 2, 0x0c, 8, 4)
};
static s32 de_clk_set_div(u32 clk_no, u32 div)
{
u32 i = 0;
u32 reg_val;
for(i=0; i<(sizeof(de_clk_tbl)/sizeof(de_clk_para)); i++) {
if((de_clk_tbl[i].clk_no == clk_no)) {
reg_val = disp_readl(de_clk_tbl[i].mod_div_adr + de_base);
reg_val = SET_BITS(de_clk_tbl[i].mod_div_shift, de_clk_tbl[i].mod_div_width, reg_val, (div - 1));
disp_writel(reg_val, de_clk_tbl[i].mod_div_adr + de_base);
return 0;
}
}
__wrn("clk %d not foundis not initializd\n", clk_no);
return -1;
}
#include "de_clock.h"
static u32 top_base = 0;
static u32 de_clk_freq = 0;
de_top_para disp_de_top_tbl[] =
{
/* mod_id freq gate reset dram mod div */
DE_TOP_CFG(MOD_CLK_DEBE0, 396000000, 0xf3000008, 8, 0xf300000c, 8, 0xf3000004, 8, 0xf3000000, 8, 0xf3000020, 16)
DE_TOP_CFG(MOD_CLK_DEBE1, 396000000, 0xf3000008, 9, 0xf300000c, 9, 0xf3000004, 9, 0xf3000000, 9, 0xf3000020, 20)
DE_TOP_CFG(MOD_CLK_DEBE2, 396000000, 0xf3000008, 10, 0xf300000c, 10, 0xf3000004, 10, 0xf3000000, 10, 0xf3000020, 24)
DE_TOP_CFG(MOD_CLK_DEFE0, 396000000, 0xf3000008, 0, 0xf300000c, 0, 0xf3000004, 0, 0xf3000000, 0, 0xf3000020, 0)
DE_TOP_CFG(MOD_CLK_DEFE1, 396000000, 0xf3000008, 1, 0xf300000c, 1, 0xf3000004, 1, 0xf3000000, 1, 0xf3000020, 4)
DE_TOP_CFG(MOD_CLK_DEFE2, 396000000, 0xf3000008, 2, 0xf300000c, 2, 0xf3000004, 2, 0xf3000000, 2, 0xf3000020, 8)
DE_TOP_CFG(MOD_CLK_IEPDEU0, 0, 0xf3000008, 4, 0xf300000c, 4, 0xf3000004, 4, 0xf3000000, 4, 0x0, 32)
DE_TOP_CFG(MOD_CLK_IEPDEU1, 0, 0xf3000008, 5, 0xf300000c, 5, 0xf3000004, 5, 0xf3000000, 5, 0x0, 32)
DE_TOP_CFG(MOD_CLK_IEPDRC0, 0, 0xf3000008, 12, 0xf300000c, 12, 0xf3000004, 12, 0xf3000000, 12, 0x0, 32)
DE_TOP_CFG(MOD_CLK_IEPDRC1, 0, 0xf3000008, 13, 0xf300000c, 13, 0xf3000004, 13, 0xf3000000, 13, 0x0, 32)
DE_TOP_CFG(MOD_CLK_MERGE, 0, 0x0 , 32, 0xf300000c, 20, 0x0, 32, 0xf3000000, 20, 0x0, 32)
};
#define disp_clk_inf(clk_id, clk_name, clk_src_name, clk_freq)\
{.id = clk_id, .name = clk_name, .src_name = clk_src_name, .freq = clk_freq}
__disp_clk_t disp_clk_pll_tbl[] =
{
disp_clk_inf(SYS_CLK_PLL7, "pll7", NULL, 0),
disp_clk_inf(SYS_CLK_PLL8, "pll8", NULL, 297000000),
disp_clk_inf(SYS_CLK_PLL10, "pll10", NULL, 0),
};
#include "de_clock.h"
static u32 de_base = 0;
static de_clk_para de_clk_tbl[] =
{
/* mod_id freq bus reset dram gate div */
DE_TOP_CFG(DE_CLK_CORE0, 250000000, 0x04, 0, 0x08, 0, 0x00, 32, 0x00, 0, 0x0c, 0, 4)
DE_TOP_CFG(DE_CLK_CORE1, 250000000, 0x04, 1, 0x08, 2, 0x00, 32, 0x00, 1, 0x0c, 4, 4)/* hw limit:core1 & wb share 1 reset bit*/
DE_TOP_CFG(DE_CLK_WB, 250000000, 0x04, 2, 0x08, 2, 0x00, 32, 0x00, 2, 0x0c, 8, 4)
};
static s32 de_clk_set_div(u32 clk_no, u32 div)
{
u32 i = 0;
u32 reg_val;
for(i=0; i<(sizeof(de_clk_tbl)/sizeof(de_clk_para)); i++) {
if((de_clk_tbl[i].clk_no == clk_no)) {
reg_val = readl(de_clk_tbl[i].mod_div_adr + de_base);
reg_val = SET_BITS(de_clk_tbl[i].mod_div_shift, de_clk_tbl[i].mod_div_width, reg_val, (div - 1));
writel(reg_val, de_clk_tbl[i].mod_div_adr + de_base);
return 0;
}
}
__wrn("clk %d not foundis not initializd\n", clk_no);
return -1;
}
