void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)
{
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
uint32_t tmpreg;
tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
}
void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
{
assert(tcd != NULL);
assert(((uint32_t)tcd & 0x1FU) == 0);
uint32_t tmpreg;
tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
}
/**
* @brief 初始化DMA模块
* @param DMA_InitStruct :DMA初始化配置结构体，详见dma.h
* @retval 分配到的DMA 通道
*/
uint32_t DMA_Init(DMA_InitTypeDef *DMA_InitStruct)
{
uint8_t chl;
/* enable DMA and DMAMUX clock */
#if defined(DMAMUX0)
SIM->SCGC6 |= SIM_SCGC6_DMAMUX0_MASK;
#endif
#if defined(DMAMUX1)
SIM->SCGC6 |= SIM_SCGC6_DMAMUX1_MASK;
#endif
#if defined(DMAMUX)
SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
#endif
SIM->SCGC7 |= SIM_SCGC7_DMA_MASK;
chl = DMA_InitStruct->chl;
/* disable chl first */
DMA0->ERQ &= ~(1<<(chl));
/* dma chl source config */
DMAMUX_InstanceTable[0]->CHCFG[chl] = DMAMUX_CHCFG_SOURCE(DMA_InitStruct->chlTriggerSource);
/* trigger mode */
switch(DMA_InitStruct->triggerSourceMode)
{
case kDMA_TriggerSource_Normal:
DMAMUX_InstanceTable[0]->CHCFG[chl] &= ~DMAMUX_CHCFG_TRIG_MASK;
break;
case kDMA_TriggerSource_Periodic:
DMAMUX_InstanceTable[0]->CHCFG[chl] |= DMAMUX_CHCFG_TRIG_MASK;
break;
default:
break;
}
/* clear some register */
DMA0->TCD[chl].ATTR = 0;
DMA0->TCD[chl].CSR = 0;
/* minor loop cnt */
DMA0->TCD[chl].NBYTES_MLNO = DMA_NBYTES_MLNO_NBYTES(DMA_InitStruct->minorLoopByteCnt);
/* major loop cnt */
DMA0->TCD[chl].CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(DMA_InitStruct->majorLoopCnt);
DMA0->TCD[chl].BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(DMA_InitStruct->majorLoopCnt);
/* source config */
DMA0->TCD[chl].SADDR = DMA_InitStruct->sAddr;
DMA0->TCD[chl].SOFF = DMA_InitStruct->sAddrOffset;
DMA0->TCD[chl].ATTR |= DMA_ATTR_SSIZE(DMA_InitStruct->sDataWidth);
DMA0->TCD[chl].ATTR |= DMA_ATTR_SMOD(DMA_InitStruct->sMod);
DMA0->TCD[chl].SLAST = DMA_SLAST_SLAST(DMA_InitStruct->sLastAddrAdj);
/* destation config */
DMA0->TCD[chl].DADDR = DMA_InitStruct->dAddr;
DMA0->TCD[chl].DOFF = DMA_InitStruct->dAddrOffset;
DMA0->TCD[chl].ATTR |= DMA_ATTR_DSIZE(DMA_InitStruct->dDataWidth);
DMA0->TCD[chl].ATTR |= DMA_ATTR_DMOD(DMA_InitStruct->dMod);
DMA0->TCD[chl].DLAST_SGA = DMA_DLAST_SGA_DLASTSGA(DMA_InitStruct->dLastAddrAdj);
/* auto close enable(disable req on major loop complete)*/
DMA0->TCD[chl].CSR |= DMA_CSR_DREQ_MASK;
/* enable DMAMUX */
DMAMUX_InstanceTable[0]->CHCFG[chl] |= DMAMUX_CHCFG_ENBL_MASK;
return chl;
}
