void dma_stream_reset(u32 dma, u8 stream)
{
/* Disable stream (must be done before register is otherwise changed). */
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
/* Reset all config bits. */
DMA_SCR(dma, stream) = 0;
/* Reset data transfer number. */
DMA_SNDTR(dma, stream) = 0;
/* Reset peripheral and memory addresses. */
DMA_SPAR(dma, stream) = 0;
DMA_SM0AR(dma, stream) = 0;
DMA_SM1AR(dma, stream) = 0;
/* This is the default setting */
DMA_SFCR(dma, stream) = 0x21;
/* Reset all stream interrupt flags using the interrupt flag clear register. */
u32 mask = DMA_ISR_MASK(stream);
if (stream < 4)
{
DMA_LIFCR(dma) |= mask;
}
else
{
DMA_HIFCR(dma) |= mask;
}
}
void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts)
{
/* Get offset to interrupt flag location in stream field */
u32 flags = (interrupts << DMA_ISR_OFFSET(stream));
/* First four streams are in low register. Flag clear must be set then reset. */
if (stream < 4)
{
DMA_LIFCR(dma) = flags;
}
else
{
DMA_HIFCR(dma) = flags;
}
}
void DMA_UART_IRQHandler(volatile u32* pall)
{
/* The following is for consistency in the code in this file. ('nvic_dma_mgr.c' uses volatile u32*) */
struct CB_UART* pctl = (struct CB_UART*)pall;
/* Clear all interrupt flags for this DMA stream */
if (pctl->txdma_stream > 3)
{// High register
DMA_HIFCR(pctl->idma) = (0x3d << tcif_tbl[pctl->txdma_stream-4]);
}
else
{ // Low register
DMA_LIFCR(pctl->idma) = (0x3d << tcif_tbl[pctl->txdma_stream]);
}
pctl->txbuff_out = pctl->txbuff_dmanext; // Update where in the buffer we have xmitted
/* Here, check if there are bytes buffered and if so, figure out how to send them. */
common_dma(pctl);
return;
}
