/**
* \brief Configures Dma
*
* \param chanNum - Dma channel number
*
* \return Dma handle
*/
CSL_DMA_Handle CSL_configDmaForUart(CSL_DMA_ChannelObj *dmaChanObj,
CSL_DMAChanNum chanNum)
{
CSL_DMA_Handle dmaHandle;
CSL_Status status;
dmaHandle = NULL;
/* Initialize Dma */
status = DMA_init();
if (status != CSL_SOK)
{
printf("DMA_init Failed!\n");
}
/* Open A Dma channel */
dmaHandle = DMA_open(chanNum, dmaChanObj, &status);
if(dmaHandle == NULL)
{
printf("DMA_open Failed!\n");
}
/* Configure a Dma channel */
status = DMA_config(dmaHandle, &dmaConfig);
if(status != CSL_SOK)
{
printf("DMA_config Failed!\n");
dmaHandle = NULL;
}
return(dmaHandle);
}
struct Computer *createComputer() {
struct Computer *computer = (struct Computer *) malloc(sizeof(struct Computer));
// REFERENCES
computer->screen = NULL;
// OBJECTS
CPU_init(&computer->cpu);
computer->cpu.clockRate = 6000; // 6 Khz
computer->cpu.interruptVectorTable = computer->ram.buffer + INT_VECTOR_TABLE_ADDR;
computer->cpu.ram = &computer->ram;
GPU_init(&computer->gpu);
computer->gpu.refreshRate = 60; // 60 Hz
computer->gpu.vram = computer->ram.buffer + VRAM_ADDR;
RAM_init(&computer->ram);
RAM_setAccess(&computer->ram, 0, RAM_SIZE, RAM_READ | RAM_WRITE);
DMA_init(&computer->dma);
computer->dma.ptrIO = computer->ram.buffer + IO_DMA_ADDR;
computer->dma.ram = &computer->ram;
return computer;
}
void DMAInit(void)
{
DMA_disableTransferDuringReadModifyWrite();
DMA_initParam initParam = {0};
initParam.channelSelect = DMA_CHANNEL_0;
initParam.transferModeSelect = DMA_TRANSFER_REPEATED_BLOCK;
initParam.transferSize = 3;
initParam.triggerSourceSelect = DMA_TRIGGERSOURCE_24;
initParam.transferUnitSelect = DMA_SIZE_SRCWORD_DSTWORD;
initParam.triggerTypeSelect = DMA_TRIGGER_RISINGEDGE;
DMA_init(&initParam);
DMA_setSrcAddress(DMA_CHANNEL_0,
ADC12_A_getMemoryAddressForDMA(ADC12_A_BASE,
ADC12_A_MEMORY_0),
DMA_DIRECTION_INCREMENT);
DMA_setDstAddress(DMA_CHANNEL_0,
(uint32_t)&DMA_DST,
DMA_DIRECTION_INCREMENT);
//Enable DMA channel 0 interrupt
DMA_clearInterrupt(DMA_CHANNEL_0);
DMA_enableInterrupt(DMA_CHANNEL_0);
//Enable transfers on DMA channel 0
DMA_enableTransfers(DMA_CHANNEL_0);
}
//this function inits the DMA
void USB_initMemcpy (void)
{
USB_TX_memcpy = memcpyV;
USB_RX_memcpy = memcpyV;
if (USB_DMA_CHAN != 0xFF) {
#ifndef DRIVERLIB_LEGACY_MODE
DMA_init (USB_DMA_CHAN, DMA_TRANSFER_BLOCK, 0,
DMA_TRIGGERSOURCE_0, DMA_SIZE_SRCBYTE_DSTBYTE, DMA_TRIGGER_HIGH);
#else
DMA_init (DMA_BASE, USB_DMA_CHAN, DMA_TRANSFER_BLOCK, 0,
DMA_TRIGGERSOURCE_0, DMA_SIZE_SRCBYTE_DSTBYTE, DMA_TRIGGER_HIGH);
#endif
USB_TX_memcpy = memcpyDMA;
USB_RX_memcpy = memcpyDMA;
}
}
void pc_basic_device_init(qemu_irq *isa_irq,
FDCtrl **floppy_controller,
ISADevice **rtc_state)
{
int i;
DriveInfo *fd[MAX_FD];
PITState *pit;
qemu_irq rtc_irq = NULL;
qemu_irq *a20_line;
ISADevice *i8042;
qemu_irq *cpu_exit_irq;
register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
if (!no_hpet) {
DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL);
for (i = 0; i < 24; i++) {
sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);
}
rtc_irq = qdev_get_gpio_in(hpet, 0);
}
*rtc_state = rtc_init(2000, rtc_irq);
qemu_register_boot_set(pc_boot_set, *rtc_state);
pit = pit_init(0x40, isa_reserve_irq(0));
pcspk_init(pit);
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
if (serial_hds[i]) {
serial_isa_init(i, serial_hds[i]);
}
}
for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
if (parallel_hds[i]) {
parallel_init(i, parallel_hds[i]);
}
}
a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
i8042 = isa_create_simple("i8042");
i8042_setup_a20_line(i8042, a20_line);
vmmouse_init(i8042);
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
DMA_init(0, cpu_exit_irq);
for(i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
}
*floppy_controller = fdctrl_init_isa(fd);
}
//this function inits the DMA
VOID USB_initMemcpy (VOID)
{
USB_TX_memcpy = memcpyV;
USB_RX_memcpy = memcpyV;
if (USB_DMA_CHAN != 0xFF) {
DMA_init (DMA_BASE, USB_DMA_CHAN, DMA_TRANSFER_BLOCK, 0,
DMA_TRIGGERSOURCE_0, DMA_SIZE_SRCBYTE_DSTBYTE, DMA_TRIGGER_HIGH);
USB_TX_memcpy = memcpyDMA;
USB_RX_memcpy = memcpyDMA;
}
}
uint32_t c_ICS43432::init(int32_t fsamp, int32_t *buffer, uint32_t nbuf)
{
i2s_init();
float fs = i2s_speedConfig(ICS43432_DEV,N_BITS, fsamp);
if(fs<1.0f) return 0;
i2s_config(1, N_BITS, I2S_RX_2CH, 0);
i2s_configurePorts(2);
DMA_init();
i2s_setupInput(buffer,nbuf,2,5); //port, prio (8=normal)
return (uint32_t) fs;
}
//this function inits the DMA
void USB_initMemcpy (void)
{
//set DMA parameters
DMA_initParam dmaParams = {0};
dmaParams.channelSelect = USB_DMA_CHAN;
dmaParams.transferModeSelect = DMA_TRANSFER_BLOCK;
dmaParams.transferSize = 0;
dmaParams.triggerSourceSelect = DMA_TRIGGERSOURCE_0;
dmaParams.transferUnitSelect = DMA_SIZE_SRCBYTE_DSTBYTE;
dmaParams.triggerTypeSelect = DMA_TRIGGER_HIGH;
USB_TX_memcpy = memcpyV;
USB_RX_memcpy = memcpyV;
if (USB_DMA_CHAN != 0xFF) {
DMA_init(&dmaParams);
USB_TX_memcpy = memcpyDMA;
USB_RX_memcpy = memcpyDMA;
}
}
static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
{
MemoryRegion *address_space = get_system_memory();
char *filename;
int bios_size, n;
MIPSCPU *cpu;
CPUClass *cc;
CPUMIPSState *env;
qemu_irq *i8259;
rc4030_dma *dmas;
IOMMUMemoryRegion *rc4030_dma_mr;
MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
MemoryRegion *isa_io = g_new(MemoryRegion, 1);
MemoryRegion *rtc = g_new(MemoryRegion, 1);
MemoryRegion *i8042 = g_new(MemoryRegion, 1);
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev, *rc4030;
SysBusDevice *sysbus;
ISABus *isa_bus;
ISADevice *pit;
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset, dma_enable;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios2 = g_new(MemoryRegion, 1);
/* init CPUs */
cpu = MIPS_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
/* Chipset returns 0 in invalid reads and do not raise data exceptions.
* However, we can't simply add a global memory region to catch
* everything, as memory core directly call unassigned_mem_read/write
* on some invalid accesses, which call do_unassigned_access on the
* CPU, which raise an exception.
* Handle that case by hijacking the do_unassigned_access method on
* the CPU, and do not raise exceptions for data access. */
cc = CPU_GET_CLASS(cpu);
real_do_unassigned_access = cc->do_unassigned_access;
cc->do_unassigned_access = mips_jazz_do_unassigned_access;
/* allocate RAM */
memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
machine->ram_size);
memory_region_add_subregion(address_space, 0, ram);
memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
&error_fatal);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
0, MAGNUM_BIOS_SIZE);
memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
/* load the BIOS image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0xfff00000LL,
MAGNUM_BIOS_SIZE);
g_free(filename);
} else {
bios_size = -1;
}
if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
error_report("Could not load MIPS bios '%s'", bios_name);
exit(1);
}
/* Init CPU internal devices */
cpu_mips_irq_init_cpu(cpu);
cpu_mips_clock_init(cpu);
/* Chipset */
rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
sysbus = SYS_BUS_DEVICE(rc4030);
sysbus_connect_irq(sysbus, 0, env->irq[6]);
sysbus_connect_irq(sysbus, 1, env->irq[3]);
memory_region_add_subregion(address_space, 0x80000000,
sysbus_mmio_get_region(sysbus, 0));
memory_region_add_subregion(address_space, 0xf0000000,
sysbus_mmio_get_region(sysbus, 1));
memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
memory_region_add_subregion(address_space, 0x90000000, isa_io);
memory_region_add_subregion(address_space, 0x91000000, isa_mem);
isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
/* ISA devices */
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_irqs(isa_bus, i8259);
DMA_init(isa_bus, 0);
pit = pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_bus, pit);
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
dev = qdev_create(NULL, "sysbus-g364");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x60080000);
sysbus_mmio_map(sysbus, 1, 0x40000000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
{
/* Simple ROM, so user doesn't have to provide one */
MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
&error_fatal);
memory_region_set_readonly(rom_mr, true);
uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
memory_region_add_subregion(address_space, 0x60000000, rom_mr);
rom[0] = 0x10; /* Mips G364 */
}
break;
case JAZZ_PICA61:
isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
break;
default:
break;
}
/* Network controller */
for (n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!nd->model)
nd->model = g_strdup("dp83932");
if (strcmp(nd->model, "dp83932") == 0) {
qemu_check_nic_model(nd, "dp83932");
dev = qdev_create(NULL, "dp8393x");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint8(dev, "it_shift", 2);
qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80001000);
sysbus_mmio_map(sysbus, 1, 0x8000b000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
break;
} else if (is_help_option(nd->model)) {
fprintf(stderr, "qemu: Supported NICs: dp83932\n");
exit(1);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
exit(1);
}
}
/* SCSI adapter */
esp_init(0x80002000, 0,
rc4030_dma_read, rc4030_dma_write, dmas[0],
qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
/* Floppy */
for (n = 0; n < MAX_FD; n++) {
fds[n] = drive_get(IF_FLOPPY, 0, n);
}
/* FIXME: we should enable DMA with a custom IsaDma device */
fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
/* Real time clock */
rtc_init(isa_bus, 1980, NULL);
memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
i8042, 0x1000, 0x1);
memory_region_add_subregion(address_space, 0x80005000, i8042);
/* Serial ports */
if (serial_hds[0]) {
serial_mm_init(address_space, 0x80006000, 0,
qdev_get_gpio_in(rc4030, 8), 8000000/16,
serial_hds[0], DEVICE_NATIVE_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(address_space, 0x80007000, 0,
qdev_get_gpio_in(rc4030, 9), 8000000/16,
serial_hds[1], DEVICE_NATIVE_ENDIAN);
}
/* Parallel port */
if (parallel_hds[0])
parallel_mm_init(address_space, 0x80008000, 0,
qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
/* NVRAM */
dev = qdev_create(NULL, "ds1225y");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80009000);
/* LED indicator */
sysbus_create_simple("jazz-led", 0x8000f000, NULL);
}
///// program flow reaches expected exit point(s).
/////
void main(void)
{
CSL_DMA_ChannelObj dmaObj;
CSL_Status status;
Uint16 chanNumber;
Uint16 i;
printf("\n DMA POLLED MODE TEST!\n");
for(i = 0; i < CSL_DMA_BUFFER_SIZE; i++)
{
dmaSRCBuff[i] = 0xFFFF;
dmaDESTBuff[i] = 0x0000;
}
#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514) || defined(CHIP_C5517))
dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
#endif
dmaConfig.autoMode = CSL_DMA_AUTORELOAD_DISABLE;
dmaConfig.burstLen = CSL_DMA_TXBURST_8WORD;
dmaConfig.trigger = CSL_DMA_SOFTWARE_TRIGGER;
dmaConfig.dmaEvt = CSL_DMA_EVT_NONE;
dmaConfig.dmaInt = CSL_DMA_INTERRUPT_DISABLE;
dmaConfig.chanDir = CSL_DMA_READ;
dmaConfig.trfType = CSL_DMA_TRANSFER_MEMORY;
dmaConfig.dataLen = CSL_DMA_BUFFER_SIZE * 2;
dmaConfig.srcAddr = (Uint32)dmaSRCBuff;
dmaConfig.destAddr = (Uint32)dmaDESTBuff;
status = DMA_init();
if (status != CSL_SOK)
{
printf("DMA_init() Failed \n");
/////INSTRUMENTATION FOR BATCH TESTING -- Part 2 --
///// Reseting PaSs_StAtE to 0 if error detected here.
PaSs_StAtE = 0x0000; // Was intialized to 1 at declaration.
/////
}
for( chanNumber = 0; chanNumber < CSL_DMA_CHAN_MAX; chanNumber++)
{
printf("\n Test for DMA Channel No : %d \t", chanNumber);
dmaHandle = DMA_open((CSL_DMAChanNum)chanNumber,&dmaObj, &status);
if (dmaHandle == NULL)
{
printf("DMA_open() Failed \n");
break;
}
status = DMA_config(dmaHandle, &dmaConfig);
if (status != CSL_SOK)
{
printf("DMA_config() Failed \n");
break;
}
status = DMA_getConfig(dmaHandle, &getdmaConfig);
if (status != CSL_SOK)
{
printf("DMA_getConfig() Failed \n");
break;
}
status = DMA_start(dmaHandle);
if (status != CSL_SOK)
{
printf("DMA_start() Failed \n");
break;
}
while(DMA_getStatus(dmaHandle));
status = DMA_reset(dmaHandle);
if (status != CSL_SOK)
{
printf("DMA_close() Failed \n");
break;
}
status = DMA_close(dmaHandle);
if (status != CSL_SOK)
{
printf("DMA_reset() Failed \n");
break;
}
/* validation for set and get config parameter */
if((dmaConfig.autoMode) != (getdmaConfig.autoMode))
{
printf("Mode not matched\n");
}
if(((dmaConfig.burstLen) != (getdmaConfig.burstLen)))
{
printf("Burst length not matched\n");
}
if(((dmaConfig.trigger) != (getdmaConfig.trigger)))
{
printf("Triger type not matched\n");
}
if(((dmaConfig.dmaEvt) != (getdmaConfig.dmaEvt)) )
{
printf("Event not matched\n");
}
if(((dmaConfig.dmaInt) != (getdmaConfig.dmaInt)))
{
printf("Interrupt state not matched\n");
}
if(((dmaConfig.chanDir) != (getdmaConfig.chanDir)))
{
printf("Direction read or write not matched\n");
}
if(((dmaConfig.trfType) != (getdmaConfig.trfType)))
{
printf("Transfer type not matched\n");
}
if(((dmaConfig.dataLen) != (getdmaConfig.dataLen)))
{
printf("data length of transfer not matched\n");
}
if(((dmaConfig.srcAddr) != (getdmaConfig.srcAddr)))
{
printf("Source address not matched\n");
}
if(((dmaConfig.destAddr) != (getdmaConfig.destAddr)))
{
printf("Destination address not matched\n");
}
for(i = 0; i < CSL_DMA_BUFFER_SIZE; i ++)
{
if(dmaSRCBuff[i] != dmaDESTBuff[i])
{
printf("Buffer miss matched at position %d\n",i);
break;
}
}
if(i == CSL_DMA_BUFFER_SIZE)
{
printf("Success");
}
for(i = 0; i < CSL_DMA_BUFFER_SIZE; i++)
{
dmaSRCBuff[i] = 0xFFFF;
dmaDESTBuff[i] = 0x0000;
}
}
if(chanNumber == 16)
{
printf("\n\n DMA POLLED MODE TEST PASSED!!\n");
}
else
{
printf("\n\n DMA POLLED MODE TEST FAILED!!\n");
/////INSTRUMENTATION FOR BATCH TESTING -- Part 2 --
///// Reseting PaSs_StAtE to 0 if error detected here.
PaSs_StAtE = 0x0000; // Was intialized to 1 at declaration.
/////
}
/////INSTRUMENTATION FOR BATCH TESTING -- Part 3 --
///// At program exit, copy "PaSs_StAtE" into "PaSs".
PaSs = PaSs_StAtE; //If flow gets here, override PaSs' initial 0 with
///// // pass/fail value determined during program execution.
///// Note: Program should next exit to C$$EXIT and halt, where DSS, under
///// control of a host PC script, will read and record the PaSs' value.
/////
}
OSStatus spi_init( spi_driver_t* spi_driver, SPI_MemMapPtr spi_peripheral, uint32_t baud_rate_bps, uint8_t chip_select, bool polarity, bool phase, bool use_dma )
{
uint8_t br = get_baud_rate_scaler_register_value( baud_rate_bps );
spi_driver->spi_peripheral = spi_peripheral;
spi_driver->baud_rate_bps = baud_rate_bps;
spi_driver->chip_select = chip_select;
spi_driver->polarity = polarity;
spi_driver->phase = phase;
spi_driver->use_dma = use_dma;
/* Enable SPI peripheral clock */
set_spi_peripheral_clock( spi_peripheral, true );
/* Enable SPI peripheral and clean up (stop) any previous transfer
* MDIS = 0 to enable
* HALT = 1 to stop transfer
* MSTR = 1 for master mode
* DCONF = 0 for SPI
* PCSIS[x] = 1 for CS active low
*/
SPI_MCR_REG( spi_peripheral ) &= ~(uint32_t) ( SPI_MCR_MDIS_MASK | SPI_MCR_DCONF(0) );
SPI_MCR_REG( spi_peripheral ) |= (uint32_t) ( (0x1<<24)|SPI_MCR_HALT_MASK | SPI_MCR_MSTR_MASK | SPI_MCR_PCSIS( 1 << chip_select ) );
/* Select Clock and Transfer Attributes Register (CTAR). Always use CTAR0 */
SPI_PUSHR_REG( spi_peripheral ) &= ~(uint32_t) SPI_PUSHR_CTAS(CTAR_REG_USED);
/* Reset Clock and Transfer Attributes (CTAR) register */
SPI_CTAR_REG( spi_peripheral, CTAR_REG_USED ) = 0;
/* Set SPI configuration
* FMSZ = 7. Set frame size to 8-bit. frame size = FMSZ + 1
* CPOL = phase
* CPHA = polarity
* DBR = 00
* PBR = 2
* BR = calculate based on baud_rate_Mbps
* PCSSCK = 0
* PASC = 0
* PDT = 0
* CSSCK = BR - 1
* ASC = BR - 1
* DT = 0
*/
SPI_CTAR_REG( spi_peripheral, CTAR_REG_USED ) |= (uint32_t) ( SPI_CTAR_CPOL_MASK & (uint32_t)( polarity << SPI_CTAR_CPOL_SHIFT ) ) |
(uint32_t) ( SPI_CTAR_CPHA_MASK & (uint32_t)( phase << SPI_CTAR_CPHA_SHIFT ) ) |
(uint32_t) ( SPI_CTAR_FMSZ( 8 - 1 ) ) |
(uint32_t) ( SPI_CTAR_DBR_MASK & ( DOUBLE_BAUD_RATE << SPI_CTAR_DBR_SHIFT ) ) |
(uint32_t) ( SPI_CTAR_PBR( CTAR_PBR ) ) |
(uint32_t) ( SPI_CTAR_BR( br ) ) |
(uint32_t) ( SPI_CTAR_CSSCK( br - 1 ) ) |
(uint32_t) ( SPI_CTAR_ASC( br - 1 ) );
clear_spi_fifos( spi_peripheral );
/* Enable the start transfer bit */
SPI_MCR_REG( spi_peripheral ) &= ~(uint32_t) ( SPI_MCR_HALT_MASK );
if(use_dma)
{
SPI_RSER_REG( spi_peripheral ) |= (0x3<<24)|(0x3<<16);
DMA_init();
}
spi_status_print(spi_peripheral);
return kNoErr;
}
static void mips_jazz_init(MemoryRegion *address_space,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
const char *cpu_model,
enum jazz_model_e jazz_model)
{
char *filename;
int bios_size, n;
MIPSCPU *cpu;
CPUMIPSState *env;
qemu_irq *rc4030, *i8259;
rc4030_dma *dmas;
void* rc4030_opaque;
MemoryRegion *rtc = g_new(MemoryRegion, 1);
MemoryRegion *i8042 = g_new(MemoryRegion, 1);
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev;
SysBusDevice *sysbus;
ISABus *isa_bus;
ISADevice *pit;
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset, dma_enable;
qemu_irq *cpu_exit_irq;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios2 = g_new(MemoryRegion, 1);
/* init CPUs */
if (cpu_model == NULL) {
#ifdef TARGET_MIPS64
cpu_model = "R4000";
#else
/* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
cpu_model = "24Kf";
#endif
}
cpu = cpu_mips_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
/* allocate RAM */
memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size);
vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space, 0, ram);
memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
vmstate_register_ram_global(bios);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
0, MAGNUM_BIOS_SIZE);
memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
/* load the BIOS image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0xfff00000LL,
MAGNUM_BIOS_SIZE);
g_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
bios_name);
exit(1);
}
/* Init CPU internal devices */
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
/* Chipset */
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
address_space);
memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA devices */
isa_bus = isa_bus_new(NULL, address_space_io);
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_irqs(isa_bus, i8259);
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
DMA_init(0, cpu_exit_irq);
pit = pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_bus, pit);
/* ISA IO space at 0x90000000 */
isa_mmio_init(0x90000000, 0x01000000);
isa_mem_base = 0x11000000;
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
dev = qdev_create(NULL, "sysbus-g364");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x60080000);
sysbus_mmio_map(sysbus, 1, 0x40000000);
sysbus_connect_irq(sysbus, 0, rc4030[3]);
{
/* Simple ROM, so user doesn't have to provide one */
MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000);
vmstate_register_ram_global(rom_mr);
memory_region_set_readonly(rom_mr, true);
uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
memory_region_add_subregion(address_space, 0x60000000, rom_mr);
rom[0] = 0x10; /* Mips G364 */
}
break;
case JAZZ_PICA61:
isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
break;
default:
break;
}
/* Network controller */
for (n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!nd->model)
nd->model = g_strdup("dp83932");
if (strcmp(nd->model, "dp83932") == 0) {
dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
rc4030_opaque, rc4030_dma_memory_rw);
break;
} else if (is_help_option(nd->model)) {
fprintf(stderr, "qemu: Supported NICs: dp83932\n");
exit(1);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
exit(1);
}
}
/* SCSI adapter */
esp_init(0x80002000, 0,
rc4030_dma_read, rc4030_dma_write, dmas[0],
rc4030[5], &esp_reset, &dma_enable);
/* Floppy */
if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
fprintf(stderr, "qemu: too many floppy drives\n");
exit(1);
}
for (n = 0; n < MAX_FD; n++) {
fds[n] = drive_get(IF_FLOPPY, 0, n);
}
fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
/* Real time clock */
rtc_init(isa_bus, 1980, NULL);
memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
memory_region_add_subregion(address_space, 0x80005000, i8042);
/* Serial ports */
if (serial_hds[0]) {
serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
serial_hds[0], DEVICE_NATIVE_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
serial_hds[1], DEVICE_NATIVE_ENDIAN);
}
/* Parallel port */
if (parallel_hds[0])
parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
parallel_hds[0]);
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
/* NVRAM */
dev = qdev_create(NULL, "ds1225y");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80009000);
/* LED indicator */
sysbus_create_simple("jazz-led", 0x8000f000, NULL);
}
void neomaple_hard_init(uint8_t *buffer) {
WS2812_buffer = buffer;
GPIO_init();
DMA_init();
TIM2_init();
}
static
void mips_jazz_init (ram_addr_t ram_size,
const char *cpu_model,
enum jazz_model_e jazz_model)
{
char *filename;
int bios_size, n;
CPUState *env;
qemu_irq *rc4030, *i8259;
rc4030_dma *dmas;
void* rc4030_opaque;
int s_rtc, s_dma_dummy;
NICInfo *nd;
PITState *pit;
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
/* init CPUs */
if (cpu_model == NULL) {
#ifdef TARGET_MIPS64
cpu_model = "R4000";
#else
/* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
cpu_model = "24Kf";
#endif
}
env = cpu_init(cpu_model);
if (!env) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
ram_offset = qemu_ram_alloc(ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE);
cpu_register_physical_memory(0x1fc00000LL,
MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
cpu_register_physical_memory(0xfff00000LL,
MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
/* load the BIOS image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0xfff00000LL,
MAGNUM_BIOS_SIZE);
qemu_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
bios_name);
exit(1);
}
/* Init CPU internal devices */
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
/* Chipset */
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
/* ISA devices */
i8259 = i8259_init(env->irq[4]);
isa_bus_new(NULL);
isa_bus_irqs(i8259);
DMA_init(0);
pit = pit_init(0x40, i8259[0]);
pcspk_init(pit);
/* ISA IO space at 0x90000000 */
isa_mmio_init(0x90000000, 0x01000000);
isa_mem_base = 0x11000000;
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
break;
case JAZZ_PICA61:
isa_vga_mm_init(0x40000000, 0x60000000, 0);
break;
default:
break;
}
/* Network controller */
for (n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!nd->model)
nd->model = qemu_strdup("dp83932");
if (strcmp(nd->model, "dp83932") == 0) {
dp83932_init(nd, 0x80001000, 2, rc4030[4],
rc4030_opaque, rc4030_dma_memory_rw);
break;
} else if (strcmp(nd->model, "?") == 0) {
fprintf(stderr, "qemu: Supported NICs: dp83932\n");
exit(1);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
exit(1);
}
}
/* SCSI adapter */
esp_init(0x80002000, 0,
rc4030_dma_read, rc4030_dma_write, dmas[0],
rc4030[5], &esp_reset);
/* Floppy */
if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
fprintf(stderr, "qemu: too many floppy drives\n");
exit(1);
}
for (n = 0; n < MAX_FD; n++) {
fds[n] = drive_get(IF_FLOPPY, 0, n);
}
fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
/* Real time clock */
rtc_init(1980);
s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL);
cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
/* Keyboard (i8042) */
i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
/* Serial ports */
if (serial_hds[0])
serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
if (serial_hds[1])
serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
/* Parallel port */
if (parallel_hds[0])
parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
/* Sound card */
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
#ifdef HAS_AUDIO
audio_init(i8259);
#endif
/* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
ds1225y_init(0x80009000, "nvram");
/* LED indicator */
jazz_led_init(0x8000f000);
}
void main (void)
{
unsigned int ADC_Result[64];
volatile unsigned int ADC_Result_Average;
unsigned char i;
unsigned int ADC_Result_sum;
//Stop Watchdog Timer
WDT_hold(__MSP430_BASEADDRESS_WDT_A__);
//Initialize the ADC10 Module
/*
* Base Address for the ADC10 Module
* Use internal ADC10 bit as sample/hold signal to start conversion
* USE MODOSC 5MHZ Digital Oscillator as clock source
* Use default clock divider of 1
*/
ADC10_init(__MSP430_BASEADDRESS_ADC10_A__,
ADC10_SAMPLEHOLDSOURCE_SC,
ADC10_CLOCKSOURCE_ADC10OSC,
ADC10_CLOCKDIVIDER_1);
ADC10_enable(__MSP430_BASEADDRESS_ADC10_A__);
/*
* Base Address for the ADC10 Module
* Sample/hold for 16 clock cycles
* Enable Multiple Sampling
*/
ADC10_setupSamplingTimer(__MSP430_BASEADDRESS_ADC10_A__,
ADC10_CYCLEHOLD_16_CYCLES,
ADC10_MULTIPLESAMPLESENABLE);
//Configure Memory Buffer
/*
* Base Address for the ADC10 Module
* Use input A1
* Use positive reference of AVcc
* Use negative reference of AVss
*/
ADC10_memoryConfigure(__MSP430_BASEADDRESS_ADC10_A__,
ADC10_INPUT_A1,
ADC10_VREFPOS_AVCC,
ADC10_VREFNEG_AVSS);
//Initialize and Setup DMA Channel 0
/*
* Base Address for the DMA Module
* Configure DMA channel 0
* Configure channel for repeated single transfer
* DMA interrupt flag will be set after every 64 transfers
* Use DMA Trigger Source 24 (ADC10IFG)
* Transfer Word-to-Word
* Trigger upon Rising Edge of Trigger Source Signal
*/
DMA_init(__MSP430_BASEADDRESS_DMAX_3__,
DMA_CHANNEL_0,
DMA_TRANSFER_REPEATED_SINGLE,
64,
DMA_TRIGGERSOURCE_24,
DMA_SIZE_SRCWORD_DSTWORD,
DMA_TRIGGER_RISINGEDGE);
/*
* Base Address for the DMA Module
* Configure DMA channel 0
* Use ADC10 Memory Buffer as source
* Increment destination address after every transfer
*/
DMA_setSrcAddress(__MSP430_BASEADDRESS_DMAX_3__,
DMA_CHANNEL_0,
ADC10_getMemoryAddressForDMA(__MSP430_BASEADDRESS_ADC10_A__),
DMA_DIRECTION_UNCHANGED);
/*
* Base Address for the DMA Module
* Configure DMA channel 0
* Use ADC_Result[0] as destination
* Increment destination address after every transfer
*/
DMA_setDstAddress(__MSP430_BASEADDRESS_DMAX_3__,
DMA_CHANNEL_0,
(unsigned long)&ADC_Result[0],
DMA_DIRECTION_INCREMENT);
//Enable DMA channel 0 interrupt
DMA_enableInterrupt(__MSP430_BASEADDRESS_DMAX_3__,
DMA_CHANNEL_0);
//Enable transfers on DMA channel 0
DMA_enableTransfers(__MSP430_BASEADDRESS_DMAX_3__,
DMA_CHANNEL_0);
while (1)
{
//Enable and Start the conversion
//in Repeated Single-Channel Conversion Mode
ADC10_startConversion(__MSP430_BASEADDRESS_ADC10_A__,
ADC10_REPEATED_SINGLECHANNEL);
__bis_SR_register(CPUOFF + GIE); //LPM0, ADC10_ISR will force exit
__no_operation(); //For debug only
//Clear accumulate register
ADC_Result_sum = 0x0;
for (i = 0; i < 64; i++){
ADC_Result_sum += ADC_Result[i];
}
//Average of 64 conversions results
ADC_Result_Average = ADC_Result_sum >> 6;
//SET BREAKPOINT HERE to be able to watch ADC_Result_Average
//Delay before next 64 conversions
__delay_cycles(50000);
}
}
int main(void) {
xil_printf("Starting\r\n");
int Status;
int i;
u32 start_time;
u32 end_time;
u32 return_val[ACTUAL_READS];
// Initialize DMA
Status = DMA_init(DMA_DEV_ID);
if (Status != XST_SUCCESS) {
xil_printf("XAxiDma_init: Failed %d\r\n", Status);
return XST_FAILURE;
}
// Initialize PE
Status = XNeedlemanwunsch_Initialize(&PE, PE_DEV_ID);
if (Status != XST_SUCCESS) {
xil_printf("XNeedlemanwunsch_Initialize: Failed %d\r\n", Status);
return XST_FAILURE;
}
XNeedlemanwunsch_DisableAutoRestart(&PE);
// Initialize timer with maximum value so we can see how far down it
// goes. It should last about 12 seconds before hitting zero.
Timer_init(TIMER_DEV_ID);
XScuTimer_LoadTimer(&Timer, TIMER_MAX);
XScuTimer_SetPrescaler(&Timer, TIMER_PRESCALE-1);
start_time = TIMER_MAX;
// Flush caches
Xil_DCacheFlushRange((INTPTR)&ref_genome, sizeof(ref_genome));
XScuTimer_Start(&Timer);
for (i=0; i<ACTUAL_READS; i++) {
DMA_send();
writeRead(0, i);
while(!XNeedlemanwunsch_IsIdle(&PE) && !XNeedlemanwunsch_IsReady(&PE)) {
xil_printf("Waiting for idle/ready\r\n");
}
XNeedlemanwunsch_Start(&PE);
//if (XNeedlemanwunsch_IsIdle(&PE) || XNeedlemanwunsch_IsReady(&PE)) {
//xil_printf("Is still idle/ready\r\n");
//}
while(!XNeedlemanwunsch_IsDone(&PE) /*&& !XNeedlemanwunsch_IsIdle(&PE) && !XNeedlemanwunsch_IsReady(&PE)*/) {
}
return_val[i] = XNeedlemanwunsch_Get_return(&PE);
}
XScuTimer_Stop(&Timer);
end_time = XScuTimer_GetCounterValue(&Timer);
xil_printf("Done\r\n");
for (i=0; i<ACTUAL_READS; i++) {
xil_printf("read %d best fit at %d\r\n", i, return_val[i]);
}
print_time(start_time, end_time);
return 0;
}
CSL_Status configSdCard(CSL_MMCSDOpMode opMode) {
CSL_Status status;
Uint16 actCard;
Uint16 clockDiv;
Uint16 rca;
/* Get the clock divider value for the current CPU frequency */
clockDiv = computeClkRate();
/* Initialize MMCSD CSL module */
status = MMC_init();
status = SYS_setEBSR(CSL_EBSR_FIELD_SP0MODE, CSL_EBSR_SP0MODE_0);
status |= SYS_setEBSR(CSL_EBSR_FIELD_SP1MODE, CSL_EBSR_SP1MODE_0);
if (CSL_SOK != status) {
printf("SYS_setEBSR failed\n");
return (status);
}
/* Open MMCSD CSL module */
#ifdef C5515_EZDSP
mmcsdHandle = MMC_open(&pMmcsdContObj, CSL_MMCSD1_INST,
opMode, &status);
#else
mmcsdHandle = MMC_open(&pMmcsdContObj, CSL_MMCSD1_INST, opMode, &status);
#endif
if (mmcsdHandle == NULL) {
printf("MMC_open Failed\n");
return (status);
}
/* Configure the DMA in case of operating mode is set to DMA */
if (opMode == CSL_MMCSD_OPMODE_DMA) {
/* Initialize Dma */
status = DMA_init();
if (status != CSL_SOK) {
printf("DMA_init Failed!\n");
return (status);
}
/* Open Dma channel for MMCSD write */
dmaWrHandle = DMA_open(CSL_DMA_CHAN0, &dmaWrChanObj, &status);
if ((dmaWrHandle == NULL) || (status != CSL_SOK)) {
printf("DMA_open for MMCSD Write Failed!\n");
return (status);
}
/* Open Dma channel for MMCSD read */
dmaRdHandle = DMA_open(CSL_DMA_CHAN1, &dmaRdChanObj, &status);
if ((dmaRdHandle == NULL) || (status != CSL_SOK)) {
printf("DMA_open for MMCSD Read Failed!\n");
return (status);
}
/* Set the DMA handle for MMC read */
status = MMC_setDmaHandle(mmcsdHandle, dmaWrHandle, dmaRdHandle);
if (status != CSL_SOK) {
printf("API: MMC_setDmaHandle for MMCSD Failed\n");
return (status);
}
}
/* Reset the SD card */
status = MMC_sendGoIdle(mmcsdHandle);
if (status != CSL_SOK) {
printf("MMC_sendGoIdle Failed\n");
return (status);
}
/* Check for the card */
status = MMC_selectCard(mmcsdHandle, &mmcCardObj);
if ((status == CSL_ESYS_BADHANDLE) || (status == CSL_ESYS_INVPARAMS)) {
printf("MMC_selectCard Failed\n");
return (status);
}
/* Verify whether the SD card is detected or not */
if (mmcCardObj.cardType == CSL_SD_CARD) {
printf("SD Card detected\n");
/* Check if the card is high capacity card */
if (mmcsdHandle->cardObj->sdHcDetected == TRUE) {
printf("SD card is High Capacity Card\n");
printf("Memory Access will use Block Addressing\n");
} else {
printf("SD card is Standard Capacity Card\n");
printf("Memory Access will use Byte Addressing\n");
}
} else {
if (mmcCardObj.cardType == CSL_CARD_NONE) {
printf("No Card detected\n");
} else {
printf("SD Card not detected\n");
}
printf("Please Insert SD Card\n");
return (CSL_ESYS_FAIL);
}
/* Set the init clock */
status = MMC_sendOpCond(mmcsdHandle, 70);
if (status != CSL_SOK) {
printf("MMC_sendOpCond Failed\n");
return (status);
}
/* Send the card identification Data */
status = SD_sendAllCID(mmcsdHandle, &sdCardIdObj);
if (status != CSL_SOK) {
printf("SD_sendAllCID Failed\n");
return (status);
}
/* Set the Relative Card Address */
status = SD_sendRca(mmcsdHandle, &mmcCardObj, &rca);
if (status != CSL_SOK) {
printf("SD_sendRca Failed\n");
return (status);
}
/* Read the SD Card Specific Data */
status = SD_getCardCsd(mmcsdHandle, &sdCardCsdObj);
if (status != CSL_SOK) {
printf("SD_getCardCsd Failed\n");
return (status);
}
/* Set the card type in internal data structures */
status = MMC_setCardType(&mmcCardObj, CSL_SD_CARD);
if (status != CSL_SOK) {
printf("MMC_setCardType Failed\n");
return (status);
}
/* Set the card pointer in internal data structures */
status = MMC_setCardPtr(mmcsdHandle, &mmcCardObj);
if (status != CSL_SOK) {
printf("MMC_setCardPtr Failed\n");
return (status);
}
/* Get the number of cards */
status = MMC_getNumberOfCards(mmcsdHandle, &actCard);
if (status != CSL_SOK) {
printf("MMC_getNumberOfCards Failed\n");
return (status);
}
/* Set clock for read-write access */
status = MMC_sendOpCond(mmcsdHandle, clockDiv);
if (status != CSL_SOK) {
printf("MMC_sendOpCond Failed\n");
return (status);
}
/* Set Endian mode for read and write operations */
status = MMC_setEndianMode(mmcsdHandle, CSL_MMCSD_ENDIAN_LITTLE,
CSL_MMCSD_ENDIAN_LITTLE);
if (status != CSL_SOK) {
printf("MMC_setEndianMode Failed\n");
return (status);
}
/* Set block length for the memory card
* For high capacity cards setting the block length will have
* no effect
*/
status = MMC_setBlockLength(mmcsdHandle, CSL_MMCSD_BLOCK_LENGTH);
if (status != CSL_SOK) {
printf("MMC_setBlockLength Failed\n");
return (status);
}
return (status);
}
int main()
{
int which_to_update = 6; // start greater than 5 so we get data
uint32_t data[5]; // Array to hold ADC data
// Initialize all the things
LED_init();
systick_init(400000); // Timer goes off 10 times per second
USART2_init();
USART3_init();
button_init();
ADC_init();
servo_init();
DMA_init();
/* Enable interrupts */
__asm (" cpsie i \n" );
/* Main program loop */
while(1)
{
// State specific behavior (every time)
switch (mode_state) {
case CONFIGURE_S:
// Don't do anything
break;
case COMMAND_S:
{
/* Send in two cases:
* a) we're not waiting for a packet
* b) the update flag is set (every second, because sometimes packets get dropped
* and we don't want to wait forever)
*
* When we send a byte, we'll send whichever is next in the sequence (the current one
* is stored in the local variable (in main) which_to_update). When it goes over 5,
* we read in all the data for the next round of packets.
*/
if (!waiting_to_recv_packet || send_update_f) {
// if (send_update_f) {
if (which_to_update > 5) { // finished updating
ADC_read(data);
which_to_update = 1;
}
// We will be waiting for a packet back, so set this ahead of time
waiting_to_recv_packet=1;
// A new packet will be inbound, so reset the offset to 0 (in case it got messed up before)
recv_offset = 0;
update_server(which_to_update, data);
which_to_update++;
send_update_f = 0;
}
break;
}
case CLIENT_S:
{
/*
* Update the servos on the high tick of this flag. That is set in systick, and happens 10 times
* per second
*/
if (update_servos_from_server_f) {
// We're about to receive a response packet, so we reset the recv_offset to 0
recv_offset = 0;
waiting_to_recv_packet = 1;
update_servos();
update_servos_from_server_f = 0;
}
break;
}
default:
break;
}
// Every time, regardless of state:
// If we received a packet, print it
if (received_new_packet) {
// switch (recv_msg.pingmsg.type) {
// case TYPE_PING:
// print_string("[PING,id=");
// printUnsignedDecimal(recv_msg.pingmsg.id);
// print_string("]\n");
// break;
// case TYPE_UPDATE:
// print_string("[UPDATE,id=");
// printUnsignedDecimal(recv_msg.respmsg.id);
// print_string(",average=");
// printUnsignedDecimal(recv_msg.respmsg.average);
// print_string(",{");
// for (int i=0; i<CLASS_SIZE_MAX; i++) {
// print_string(" ");
// printUnsignedDecimal(recv_msg.respmsg.values[i]);
// }
// print_string("}]\n\r");
// break;
// default:
// break;
// }
// Reset the flag
received_new_packet = 0;
// If we're in client mode, set the servo values to those from the server
if (mode_state == CLIENT_S) {
if (recv_msg.respmsg.type == TYPE_UPDATE) {
for (int i=1; i<=5; i++)
servo_update(i, recv_msg.respmsg.values[i]);
}
}
}
// After switching states, update leds
if (update_leds_f) {
switch (mode_state) {
case CONFIGURE_S:
LED_update(LED_BLUE_ON|LED_ORANGE_OFF);
// Configuration:
// $$$ (escape sequence)
// set ip dhcp 1 (get IP address with dhcp)
// set ip host 172.16.1.10 (set remote IP)
// set ip remote 8004
// set wlan join 1 (try to connect to stored access point)
// set wlan auth 4 (set to WPA2-PSK)
// set wlan phrase ENGS62wifi
// set wlan ssid ENGS62
// save
// reboot
break;
case CLIENT_S:
LED_update(LED_BLUE_OFF|LED_ORANGE_ON);
break;
case COMMAND_S:
LED_update(LED_BLUE_ON|LED_ORANGE_ON);
waiting_to_recv_packet = 0;
break;
}
update_leds_f = 0;
}
// If in debug mode, print ADC data to the console
if (DEBUG && test_flag)
{
test_flag = 0;
uint32_t data[5];
// Initialize the data array to 0 for clarity
for (int i=0; i<5; i++) {
data[i] = 0;
}
ADC_read(data);
for (int i=0; i<5; i++) {
printUnsignedDecimal((uint16_t)data[i]);
print_string("\n");
print_string("\r");
}
print_string("-----------\n");
}
}
/* We'll never reach this line */
return 0;
}
