static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp, u8 *lane_count) { u8 data; /* * For DP rev.1.1, Maximum number of Main Link lanes * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes */ exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); *lane_count = DPCD_MAX_LANE_COUNT(data); }
static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, u8 *lane_count) { u8 data; /* * For DP rev.1.1, Maximum number of Main Link lanes * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes */ drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); *lane_count = DPCD_MAX_LANE_COUNT(data); }
static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp, u8 *lane_count) { u8 data; int retval; /* * For DP rev.1.1, Maximum number of Main Link lanes * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes */ retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_MAX_LANE_CNT, &data); if (retval < 0) return retval; *lane_count = DPCD_MAX_LANE_COUNT(data); return 0; }