static void gen2_emit_target(struct intel_batchbuffer *batch,
struct igt_buf *dst)
{
uint32_t tiling;
tiling = 0;
if (dst->tiling != I915_TILING_NONE)
tiling = BUF_3D_TILED_SURFACE;
if (dst->tiling == I915_TILING_Y)
tiling |= BUF_3D_TILE_WALK_Y;
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst->stride));
OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
OUT_BATCH(COLR_BUF_ARGB8888 |
DSTORG_HORT_BIAS(0x8) |
DSTORG_VERT_BIAS(0x8));
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
OUT_BATCH(0);
OUT_BATCH(0); /* ymin, xmin */
OUT_BATCH(DRAW_YMAX(igt_buf_height(dst) - 1) |
DRAW_XMAX(igt_buf_width(dst) - 1));
OUT_BATCH(0); /* yorig, xorig */
}
static void i915_emit_composite_setup(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
int op = intel->i915_render_state.op;
PicturePtr mask_picture = intel->render_mask_picture;
PicturePtr dest_picture = intel->render_dest_picture;
PixmapPtr mask = intel->render_mask;
PixmapPtr dest = intel->render_dest;
Bool is_solid_src, is_solid_mask;
int tex_count, t;
intel->needs_render_state_emit = FALSE;
IntelEmitInvarientState(scrn);
intel->last_3d = LAST_3D_RENDER;
is_solid_src = intel->render_source_is_solid;
is_solid_mask = intel->render_mask_is_solid;
tex_count = 0;
tex_count += ! is_solid_src;
tex_count += mask && ! is_solid_mask;
assert(intel->in_batch_atomic);
if (tex_count != 0) {
OUT_BATCH(_3DSTATE_MAP_STATE | (3 * tex_count));
OUT_BATCH((1 << tex_count) - 1);
for (t = 0; t < tex_count; t++) {
OUT_RELOC_PIXMAP(intel->texture[t], I915_GEM_DOMAIN_SAMPLER, 0, 0);
OUT_BATCH(intel->mapstate[3*t + 1]);
OUT_BATCH(intel->mapstate[3*t + 2]);
}
OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * tex_count));
OUT_BATCH((1 << tex_count) - 1);
for (t = 0; t < tex_count; t++) {
OUT_BATCH(intel->samplerstate[3*t + 0]);
OUT_BATCH(intel->samplerstate[3*t + 1]);
OUT_BATCH(intel->samplerstate[3*t + 2]);
}
}
if (is_solid_src) {
OUT_BATCH (_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH (intel->render_source_solid);
}
if (mask && is_solid_mask) {
OUT_BATCH (_3DSTATE_DFLT_SPEC_CMD);
OUT_BATCH (intel->render_mask_solid);
}
/* BUF_INFO is an implicit flush, so avoid if the target has not changed.
* XXX However for reasons unfathomed, correct rendering in KDE requires
* at least a MI_FLUSH | INHIBIT_RENDER_CACHE_FLUSH here.
*/
if (1 || dest != intel->render_current_dest) {
uint32_t tiling_bits;
intel_batch_do_flush(scrn);
if (intel_pixmap_tiled(dest)) {
tiling_bits = BUF_3D_TILED_SURFACE;
if (intel_get_pixmap_private(dest)->tiling
== I915_TILING_Y)
tiling_bits |= BUF_3D_TILE_WALK_Y;
} else
tiling_bits = 0;
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
BUF_3D_PITCH(intel_pixmap_pitch(dest)));
OUT_RELOC_PIXMAP(dest, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
OUT_BATCH(intel->i915_render_state.dst_format);
/* draw rect is unconditional */
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
OUT_BATCH(0x00000000);
OUT_BATCH(0x00000000); /* ymin, xmin */
OUT_BATCH(DRAW_YMAX(dest->drawable.height - 1) |
DRAW_XMAX(dest->drawable.width - 1));
/* yorig, xorig (relate to color buffer?) */
OUT_BATCH(0x00000000);
intel->render_current_dest = dest;
}
{
uint32_t ss2;
ss2 = ~0;
t = 0;
if (! is_solid_src) {
ss2 &= ~S2_TEXCOORD_FMT(t, TEXCOORDFMT_NOT_PRESENT);
ss2 |= S2_TEXCOORD_FMT(t,
intel_transform_is_affine(intel->transform[t]) ?
TEXCOORDFMT_2D : TEXCOORDFMT_4D);
t++;
}
if (mask && ! is_solid_mask) {
ss2 &= ~S2_TEXCOORD_FMT(t, TEXCOORDFMT_NOT_PRESENT);
ss2 |= S2_TEXCOORD_FMT(t,
intel_transform_is_affine(intel->transform[t]) ?
TEXCOORDFMT_2D : TEXCOORDFMT_4D);
t++;
}
if (intel->needs_render_ca_pass) {
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) | 0);
OUT_BATCH(ss2);
} else {
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) | I1_LOAD_S(6) | 1);
OUT_BATCH(ss2);
OUT_BATCH(i915_get_blend_cntl(op, mask_picture, dest_picture->format));
}
}
if (! intel->needs_render_ca_pass)
i915_composite_emit_shader(intel, op);
}
BOOL copybox3d( GMABitMap_t *bm_dst, GMABitMap_t *bm_src,
ULONG dst_x,ULONG dst_y,ULONG dst_width, ULONG dst_height,
ULONG src_x,ULONG src_y,ULONG src_width, ULONG src_height )
{
uint32_t dst_format;
uint32_t src_format;
if( !copybox3d_supported() )
{
return FALSE;
}
// buffers in gfx memory ?
if( ! (bm_src->fbgfx && bm_src->fbgfx) )
{
return FALSE;
}
// Max texture size, src and dst must be differend (at least if overlaps)
if( bm_src->pitch/4 > 2048 || bm_src->height > 2048 || bm_dst == bm_src )
{
return FALSE;
}
// src pitch must be long aligmented.
if( bm_src->pitch & 0x3 )
{
bug("[IntelGMA] copybox3d: ERROR bm_src->pitch=%d/n",bm_src->pitch);
return FALSE;
}
if(bm_src->bpp == 4)
{
src_format = MAPSURF_32BIT | MT_32BIT_ARGB8888;
}
else if(bm_src->bpp == 2)
{
src_format = MAPSURF_16BIT | MT_16BIT_RGB565;
}
else
{
bug("[IntelGMA] copybox3d: ERROR src_bpp=%d/n",bm_src->bpp);
return FALSE;
}
if(bm_dst->bpp == 4)
{
dst_format = COLOR_BUF_ARGB8888;
}
else if(bm_dst->bpp == 2)
{
dst_format = COLOR_BUF_RGB565;
}
else
{
bug("[IntelGMA] copybox3d: ERROR dst_bpp=%d/n",bm_dst->bpp);
return FALSE;
}
D(bug("[IntelGMA:HW] %s()\n", __func__));
LOCK_HW
START_RING(72);
/* invariant state */
OUT_RING( _3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0 );
OUT_RING( _3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
IAB_SRC_FACTOR_SHIFT) |
IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
IAB_DST_FACTOR_SHIFT) );
OUT_RING( _3DSTATE_DFLT_DIFFUSE_CMD );
OUT_RING( 0 );
OUT_RING( _3DSTATE_DFLT_SPEC_CMD );
OUT_RING( 0 );
OUT_RING( _3DSTATE_DFLT_Z_CMD );
OUT_RING( 0 );
OUT_RING( _3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7) );
OUT_RING( _3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D );
OUT_RING( _3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff) );
OUT_RING( _3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2 );
OUT_RING( 0x00000000 ); /* Disable texture coordinate wrap-shortest */
OUT_RING( (1 << S4_POINT_WIDTH_SHIFT) |
S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE |
S4_VFMT_XY );
OUT_RING( 0x00000000 ); /* Stencil. */
OUT_RING( _3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT );
OUT_RING( _3DSTATE_SCISSOR_RECT_0_CMD );
OUT_RING( 0 );
OUT_RING( 0 );
OUT_RING( _3DSTATE_DEPTH_SUBRECT_DISABLE );
OUT_RING( _3DSTATE_LOAD_INDIRECT | 0 ); /* disable indirect state */
OUT_RING( 0 );
OUT_RING( _3DSTATE_STIPPLE );
OUT_RING( 0x00000000 );
OUT_RING( _3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0 );
/* samler state */
#define TEX_COUNT 1
OUT_RING( _3DSTATE_MAP_STATE | (3 * TEX_COUNT) );
OUT_RING( (1 << TEX_COUNT) - 1 );
// Source buffer
OUT_RING( bm_src->framebuffer );
OUT_RING( src_format |
(bm_src->height - 1) << MS3_HEIGHT_SHIFT |
(bm_src->pitch/bm_src->bpp - 1) << MS3_WIDTH_SHIFT );
OUT_RING( (bm_src->pitch/4 -1) << MS4_PITCH_SHIFT );
OUT_RING( _3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT) );
OUT_RING( (1 << TEX_COUNT) - 1 );
OUT_RING( MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
FILTER_NEAREST << SS2_MIN_FILTER_SHIFT );
OUT_RING( TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
0 << SS3_TEXTUREMAP_INDEX_SHIFT );
OUT_RING( 0x00000000 );
/* render target state */
// Destination buffer
OUT_RING( _3DSTATE_BUF_INFO_CMD );
OUT_RING( BUF_3D_ID_COLOR_BACK | bm_dst->pitch );
OUT_RING( bm_dst->framebuffer );
OUT_RING( _3DSTATE_DST_BUF_VARS_CMD );
OUT_RING( dst_format |
DSTORG_HORT_BIAS(0x8) |
DSTORG_VERT_BIAS(0x8) );
/* draw rect is unconditional */
OUT_RING( _3DSTATE_DRAW_RECT_CMD );
OUT_RING( 0x00000000 );
OUT_RING( 0x00000000 ); // ymin, xmin
OUT_RING( DRAW_YMAX(dst_y + dst_height - 1) |
DRAW_XMAX(dst_x + dst_width - 1) );
/* yorig, xorig (relate to color buffer?) */
OUT_RING( 0x00000000 );
/* texfmt */
OUT_RING( _3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2 );
OUT_RING( (4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT) );
OUT_RING( ~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) );
OUT_RING( S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT );
/* pixel shader */
OUT_RING( _3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2) );
/* decl FS_T0 */
OUT_RING( D0_DCL |
GET_UREG_TYPE(FS_T0) << D0_TYPE_SHIFT |
GET_UREG_NR(FS_T0) << D0_NR_SHIFT |
((GET_UREG_TYPE(FS_T0) != GET_UREG_TYPE_S) ? D0_CHANNEL_ALL : 0) );
OUT_RING( 0 );
OUT_RING( 0 );
/* decl FS_S0 */
OUT_RING( D0_DCL |
(GET_UREG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
(GET_UREG_NR(FS_S0) << D0_NR_SHIFT) |
((GET_UREG_TYPE(FS_S0) != GET_UREG_TYPE_S) ? D0_CHANNEL_ALL : 0) );
OUT_RING( 0 );
OUT_RING( 0 );
/* texld(FS_OC, FS_S0, FS_T0 */
OUT_RING( T0_TEXLD |
(GET_UREG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
(GET_UREG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
(GET_UREG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT) );
OUT_RING( (GET_UREG_TYPE(FS_T0) << T1_ADDRESS_GET_UREG_TYPE_SHIFT) |
(GET_UREG_NR(FS_T0) << T1_ADDRESS_GET_UREG_NR_SHIFT) );
OUT_RING( 0 );
// rectangle
// 3--x
// | |
// 2--1
OUT_RING( PRIM3D_RECTLIST | (3*4 - 1) );
OUT_RING( pack_float( dst_x + dst_width) );
OUT_RING( pack_float( dst_y + dst_height) );
OUT_RING( pack_float(src_x + src_width) );
OUT_RING( pack_float(src_y + src_height) );
OUT_RING( pack_float( dst_x + 0 ) );
OUT_RING( pack_float( dst_y +dst_height) );
OUT_RING( pack_float(src_x + 0) );
OUT_RING( pack_float(src_y + src_height) );
OUT_RING( pack_float( dst_x + 0 ) );
OUT_RING( pack_float( dst_y + 0 ) );
OUT_RING( pack_float(src_x + 0) );
OUT_RING( pack_float(src_y + 0) );
ADVANCE_RING();
DO_FLUSH();
UNLOCK_HW
return TRUE;
}
static void i830_emit_composite_state(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
uint32_t vf2, tiling_bits;
uint32_t texcoordfmt = 0;
intel->needs_render_state_emit = FALSE;
IntelEmitInvarientState(scrn);
intel->last_3d = LAST_3D_RENDER;
assert(intel->in_batch_atomic);
if (intel_pixmap_tiled(intel->render_dest)) {
tiling_bits = BUF_3D_TILED_SURFACE;
if (intel_get_pixmap_private(intel->render_dest)->tiling
== I915_TILING_Y)
tiling_bits |= BUF_3D_TILE_WALK_Y;
} else
tiling_bits = 0;
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
BUF_3D_PITCH(intel_pixmap_pitch(intel->render_dest)));
OUT_RELOC_PIXMAP(intel->render_dest,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
OUT_BATCH(intel->render_dest_format);
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
OUT_BATCH(0);
OUT_BATCH(0); /* ymin, xmin */
OUT_BATCH(DRAW_YMAX(intel->render_dest->drawable.height - 1) |
DRAW_XMAX(intel->render_dest->drawable.width - 1));
OUT_BATCH(0); /* yorig, xorig */
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(2) | I1_LOAD_S(3) | I1_LOAD_S(8) | 2);
if (intel->render_mask)
vf2 = 2 << 12; /* 2 texture coord sets */
else
vf2 = 1 << 12;
OUT_BATCH(vf2); /* number of coordinate sets */
OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
OUT_BATCH(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | intel->
s8_blendctl | S8_ENABLE_COLOR_BUFFER_WRITE);
OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
LOAD_TEXTURE_BLEND_STAGE(0) | 1);
OUT_BATCH(intel->cblend);
OUT_BATCH(intel->ablend);
OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
/* We have to explicitly say we don't want write disabled */
OUT_BATCH(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
DISABLE_DITHER | ENABLE_COLOR_WRITE | DISABLE_DEPTH_WRITE);
if (intel_transform_is_affine(intel->render_source_picture->transform))
texcoordfmt |= (TEXCOORDFMT_2D << 0);
else
texcoordfmt |= (TEXCOORDFMT_3D << 0);
if (intel->render_mask) {
if (intel_transform_is_affine
(intel->render_mask_picture->transform))
texcoordfmt |= (TEXCOORDFMT_2D << 2);
else
texcoordfmt |= (TEXCOORDFMT_3D << 2);
}
OUT_BATCH(_3DSTATE_VERTEX_FORMAT_2_CMD | texcoordfmt);
i830_texture_setup(intel->render_source_picture, intel->render_source, 0);
if (intel->render_mask) {
i830_texture_setup(intel->render_mask_picture,
intel->render_mask, 1);
}
}
static void
copy(int fd, uint32_t dst, uint32_t src)
{
uint32_t batch[1024], *b = batch;
struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
struct drm_i915_gem_exec_object2 obj[3];
struct drm_i915_gem_execbuffer2 exec;
uint32_t handle;
int ret;
/* invariant state */
*b++ = (_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
*b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
IAB_SRC_FACTOR_SHIFT) |
IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
IAB_DST_FACTOR_SHIFT));
*b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
*b++ = (0);
*b++ = (_3DSTATE_DFLT_SPEC_CMD);
*b++ = (0);
*b++ = (_3DSTATE_DFLT_Z_CMD);
*b++ = (0);
*b++ = (_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
*b++ = (_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
*b++ = (_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
*b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
*b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
*b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE |
S4_VFMT_XY);
*b++ = (0x00000000); /* Stencil. */
*b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
*b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
*b++ = (0);
*b++ = (0);
*b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
*b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
*b++ = (0);
*b++ = (_3DSTATE_STIPPLE);
*b++ = (0x00000000);
*b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
/* samler state */
#define TEX_COUNT 1
*b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
*b++ = ((1 << TEX_COUNT) - 1);
*b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
*b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 |
MS3_TILED_SURFACE |
(HEIGHT - 1) << MS3_HEIGHT_SHIFT |
(WIDTH - 1) << MS3_WIDTH_SHIFT);
*b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
*b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
*b++ = ((1 << TEX_COUNT) - 1);
*b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
*b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
0 << SS3_TEXTUREMAP_INDEX_SHIFT);
*b++ = (0x00000000);
/* render target state */
*b++ = (_3DSTATE_BUF_INFO_CMD);
*b++ = (BUF_3D_ID_COLOR_BACK | BUF_3D_TILED_SURFACE | WIDTH*4);
*b = fill_reloc(r++, b-batch, dst,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
b++;
*b++ = (_3DSTATE_DST_BUF_VARS_CMD);
*b++ = (COLR_BUF_ARGB8888 |
DSTORG_HORT_BIAS(0x8) |
DSTORG_VERT_BIAS(0x8));
/* draw rect is unconditional */
*b++ = (_3DSTATE_DRAW_RECT_CMD);
*b++ = (0x00000000);
*b++ = (0x00000000); /* ymin, xmin */
*b++ = (DRAW_YMAX(HEIGHT - 1) |
DRAW_XMAX(WIDTH - 1));
/* yorig, xorig (relate to color buffer?) */
*b++ = (0x00000000);
/* texfmt */
*b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
*b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
*b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
*b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
/* pixel shader */
*b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
/* decl FS_T0 */
*b++ = (D0_DCL |
REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
REG_NR(FS_T0) << D0_NR_SHIFT |
((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
*b++ = (0);
*b++ = (0);
/* decl FS_S0 */
*b++ = (D0_DCL |
(REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
(REG_NR(FS_S0) << D0_NR_SHIFT) |
((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
*b++ = (0);
*b++ = (0);
/* texld(FS_OC, FS_S0, FS_T0 */
*b++ = (T0_TEXLD |
(REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
(REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
(REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
*b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
(REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
*b++ = (0);
*b++ = (PRIM3D_RECTLIST | (3*4 - 1));
*b++ = pack_float(WIDTH);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(WIDTH);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(0);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(0);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(0);
*b++ = pack_float(0);
*b++ = pack_float(0);
*b++ = pack_float(0);
*b++ = MI_BATCH_BUFFER_END;
if ((b - batch) & 1)
*b++ = 0;
igt_assert(b - batch <= 1024);
handle = gem_create(fd, 4096);
gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
igt_assert(r-reloc == 2);
obj[0].handle = dst;
obj[0].relocation_count = 0;
obj[0].relocs_ptr = 0;
obj[0].alignment = 0;
obj[0].offset = 0;
obj[0].flags = 0;
obj[0].rsvd1 = 0;
obj[0].rsvd2 = 0;
obj[1].handle = src;
obj[1].relocation_count = 0;
obj[1].relocs_ptr = 0;
obj[1].alignment = 0;
obj[1].offset = 0;
obj[1].flags = 0;
obj[1].rsvd1 = 0;
obj[1].rsvd2 = 0;
obj[2].handle = handle;
obj[2].relocation_count = 2;
obj[2].relocs_ptr = (uintptr_t)reloc;
obj[2].alignment = 0;
obj[2].offset = 0;
obj[2].flags = 0;
obj[2].rsvd1 = obj[2].rsvd2 = 0;
exec.buffers_ptr = (uintptr_t)obj;
exec.buffer_count = 3;
exec.batch_start_offset = 0;
exec.batch_len = (b-batch)*sizeof(batch[0]);
exec.DR1 = exec.DR4 = 0;
exec.num_cliprects = 0;
exec.cliprects_ptr = 0;
exec.flags = 0;
i915_execbuffer2_set_context_id(exec, 0);
exec.rsvd2 = 0;
ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
while (ret && errno == EBUSY) {
drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
}
igt_assert_eq(ret, 0);
gem_close(fd, handle);
}
