tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
tti_mod TTI modifiers list
*/
DIB tti_dib = { DEV_TTI, 1, { &tti } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_KSR, 0), SERIAL_IN_WAIT };
REG tti_reg[] = {
{ ORDATAD (BUF, tti_unit.buf, 8, "last data item processed") },
{ FLDATAD (DONE, dev_done, INT_V_TTI, "device done flag") },
{ FLDATAD (ENABLE, int_enable, INT_V_TTI, "interrupt enable flag") },
{ FLDATAD (INT, int_req, INT_V_TTI, "interrupt pending flag") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval (if 0, the keyboard is polled synchronously with the clock)"), PV_LEFT+REG_NZ },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev, NULL },
{ 0 }
};
DEVICE tti_dev = {
"TTI", &tti_unit, tti_reg, tti_mod,
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) },
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) },
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) }
};
REG rk_reg[] = {
{ ORDATAD (RKSTA, rk_sta, 12, "status") },
{ ORDATAD (RKCMD, rk_cmd, 12, "disk command") },
{ ORDATAD (RKDA, rk_da, 12, "disk address") },
{ ORDATAD (RKMA, rk_ma, 12, "current memory address") },
{ FLDATAD (BUSY, rk_busy, 0, "control busy flag") },
{ FLDATAD (INT, int_req, INT_V_RK, "interrupt pending flag") },
{ DRDATAD (STIME, rk_swait, 24, "seek time, per cylinder"), PV_LEFT },
{ DRDATAD (RTIME, rk_rwait, 24, "rotational delay"), PV_LEFT },
{ FLDATAD (STOP_IOE, rk_stopioe, 0, "stop on I/O error") },
{ ORDATA (DEVNUM, rk_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB rk_mod[] = {
{ UNIT_HWLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_HWLK, UNIT_HWLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
&set_dev, &show_dev, NULL },
{ 0 }
};
DEVICE rk_dev = {
{ GRDATAD (MXS0, msgxs0, DEV_RDX, 16, 0, "message packet extended status 0") },
{ GRDATAD (MXS1, msgxs1, DEV_RDX, 16, 0, "message packet extended status 1") },
{ GRDATAD (MXS2, msgxs2, DEV_RDX, 16, 0, "message packet extended status 2") },
{ GRDATAD (MXS3, msgxs3, DEV_RDX, 16, 0, "message packet extended status 3") },
{ GRDATAD (MSX4, msgxs4, DEV_RDX, 16, 0, "message packet extended status 4") },
{ GRDATAD (WADL, wchadl, DEV_RDX, 16, 0, "write char packet low address") },
{ GRDATAD (WADH, wchadh, DEV_RDX, 16, 0, "write char packet high address") },
{ GRDATAD (WLNT, wchlnt, DEV_RDX, 16, 0, "write char packet length") },
{ GRDATAD (WOPT, wchopt, DEV_RDX, 16, 0, "write char packet options") },
{ GRDATAD (WXOPT, wchxopt, DEV_RDX, 16, 0, "write char packet extended options") },
{ FLDATAD (INT, IREQ (TS), INT_V_TS, "interrupt pending") },
{ FLDATAD (ATTN, ts_qatn, 0, "attention message pending") },
{ FLDATAD (BOOT, ts_bcmd, 0, "boot request pending") },
{ FLDATAD (OWNC, ts_ownc, 0, "if set, tape owns command buffer") },
{ FLDATAD (OWNM, ts_ownm, 0, "if set, tape owns message buffer") },
{ DRDATAD (TIME, ts_time, 24, "delay"), PV_LEFT + REG_NZ },
{ DRDATAD (POS, ts_unit.pos, T_ADDR_W, "position"), PV_LEFT + REG_RO },
{ GRDATA (DEVADDR, ts_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, ts_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB ts_mod[] = {
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable tape drive" },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED",
NULL, NULL, NULL, "Write lock tape drive" },
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL, "Set/Display tape format (SIMH, E11, TPC, P7B)" },
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL, "Set/Display capacity" },
DIB tti_dib = {
IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr,
1, IVCL (TTI), VEC_TTI, { NULL }
};
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), SERIAL_IN_WAIT };
REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 8, "last data item processed") },
{ HRDATAD (CSR, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, IREQ (TTI), INT_V_TTI, "interrupt pending flag") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (ERR, tti_csr, CSR_V_ERR, "device error flag (CSR<15>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ 0 }
};
DEVICE tto_dev = {
"TTO", tto_unit, tto_reg, tto_mod,
4, 10, 31, 1, 16, 8,
NULL, NULL, &tto_reset,
NULL, NULL, NULL,
NULL, 0, 0, NULL, NULL, NULL, &tto_help, NULL, NULL,
&tto_description
};
/* TODR and TMR data structures */
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */
REG clk_reg[] = {
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
#if defined (SIM_ASYNCH_IO)
{ DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT },
{ DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT },
{ DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT },
#endif
{ NULL }
};
DEVICE clk_dev = {
"TODR", &clk_unit, clk_reg, NULL,
1, 0, 8, 4, 0, 32,
NULL, NULL, &clk_reset,
NULL, &clk_attach, &clk_detach,
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
{ HRDATAD (RXCS, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, tti_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ 0 }
};
DEVICE tti_dev = {
"TTI", &tti_unit, tti_reg, tti_mod,
1, 10, 31, 1, 16, 8,
NULL, NULL, &tti_reset,
NULL, NULL, NULL,
{ FLDATAD (NEXINT, nexus_req[IPL_UBA], TR_UBA, "") },
{ FLDATAD (AIIP, uba_aiip, 0, "adapter interrupt in progress") },
{ FLDATAD (UIIP, uba_uiip, 0, "Unibus interrupt in progress") },
{ HRDATAD (FMER, uba_fmer, 32, "failing map register") },
{ HRDATAD (FUBAR, uba_fubar, 32, "failing Unibus address") },
{ HRDATAD (BRSVR0, uba_svr[0], 32, "diagnostic register 0") },
{ HRDATAD (BRSVR1, uba_svr[1], 32, "diagnostic register 1") },
{ HRDATAD (BRSVR2, uba_svr[2], 32, "diagnostic register 2") },
{ HRDATAD (BRSVR3, uba_svr[3], 32, "diagnostic register 3") },
{ HRDATAD (BRRVR4, uba_rvr[0], 32, "vector register 0") },
{ HRDATAD (BRRVR5, uba_rvr[1], 32, "vector register 1") },
{ HRDATAD (BRRVR6, uba_rvr[2], 32, "vector register 2") },
{ HRDATAD (BRRVR7, uba_rvr[3], 32, "vector register 3") },
{ BRDATAD (DPR, uba_dpr, 16, 32, 16, "number data paths") },
{ BRDATAD (MAP, uba_map, 16, 32, 496, "Unibus map registers") },
{ DRDATAD (AITIME, uba_aitime, 24, "adapter init time"), PV_LEFT + REG_NZ },
{ DRDATAD (UITIME, uba_uitime, 24, "Unibus init time"), PV_LEFT + REG_NZ },
{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
{ NULL }
};
MTAB uba_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_UBA, "NEXUS", NULL,
NULL, &show_nexus, NULL, "Display nexus" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace, NULL, "Display IO address space assignments" },
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon, NULL, "Enable/Display autoconfiguration" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
&set_autocon, NULL, NULL, "Disable autoconfiguration" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
static void raise_disk3_interrupt(void);
static int32 disk3dev(const int32 port, const int32 io, const int32 data);
/* static uint8 DISK3_Read(const uint32 Addr); */
static uint8 DISK3_Write(const uint32 Addr, uint8 cData);
static UNIT disk3_unit[] = {
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, DISK3_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, DISK3_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, DISK3_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, DISK3_CAPACITY) }
};
static REG disk3_reg[] = {
{ DRDATAD (NTRACKS, ntracks, 10,
"Number of tracks"), },
{ DRDATAD (NHEADS, nheads, 8,
"Number of heads"), },
{ DRDATAD (NSECTORS, nsectors, 8,
"Number of sectors per track"), },
{ DRDATAD (SECTSIZE, sectsize, 11,
"Sector size not including pre/postamble"), },
{ HRDATAD (SEL_DRIVE, disk3_info_data.sel_drive, 3,
"Currently selected drive"), },
{ HRDATAD (MODE, disk3_info_data.mode, 8,
"Mode (0xFF=absolute, 0x00=logical)"), },
{ HRDATAD (RETRIES, disk3_info_data.retries, 8,
"Number of retries to attempt"), },
{ HRDATAD (NDRIVES, disk3_info_data.ndrives, 8,
"Number of drives attached to the controller"), },
{ HRDATAD (LINK_ADDR, disk3_info_data.link_addr, 32,
lp62_unit LPT unit
lp62_reg LPT register list
*/
DIB lp62_dib = { DEV_LPT, 2, &lp62_iors, { &lp62_65, &lp62_66 } };
UNIT lp62_unit = {
UDATA (&lp62_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 0), SERIAL_OUT_WAIT
};
REG lp62_reg[] = {
{ ORDATAD (BUF, lp62_unit.buf, 8, "last data item processed") },
{ FLDATAD (INT, int_hwre[API_LPT], INT_V_LPT, "interrupt pending flag") },
{ FLDATAD (DONE, int_hwre[API_LPT], INT_V_LPT, "device done flag") },
{ FLDATAD (SPC, int_hwre[API_LPTSPC], INT_V_LPTSPC, "spacing done flag") },
{ DRDATAD (BPTR, lp62_bp, 6, "print buffer pointer") },
{ ORDATA (STATE, lp62_spc, 6), REG_HRO },
{ FLDATA (OVRPR, lp62_ovrpr, 0), REG_HRO },
{ DRDATAD (POS, lp62_unit.pos, T_ADDR_W, "position in the output file"), PV_LEFT },
{ DRDATAD (TIME, lp62_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ FLDATAD (STOP_IOE, lp62_stopioe, 0, "stop on I/O error") },
{ BRDATAD (LBUF, lp62_buf, 8, 8, LP62_BSIZE, "line buffer") },
{ ORDATA (DEVNO, lp62_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB lp62_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },
{ 0 }
};
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO|
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) },
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO|
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) },
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO|
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) }
};
REG rs_reg[] = {
{ BRDATAD (CS1, rscs1, DEV_RDX, 16, RS_NUMDR, "control/status 1") },
{ BRDATAD (DA, rsda, DEV_RDX, 16, RS_NUMDR, "track/sector") },
{ BRDATAD (DS, rsds, DEV_RDX, 16, RS_NUMDR, "drive status") },
{ BRDATAD (ER, rser, DEV_RDX, 16, RS_NUMDR, "error status") },
{ BRDATAD (MR, rsmr, DEV_RDX, 16, RS_NUMDR, "maint register") },
{ BRDATAD (WLKS, rswlk, DEV_RDX, 6, RS_NUMDR, "write lock switches") },
{ DRDATAD (TIME, rs_wait, 24, "rotate time"), REG_NZ + PV_LEFT },
{ URDATAD (CAPAC, rs_unit[0].capac, 10, T_ADDR_W, 0,
RS_NUMDR, PV_LEFT | REG_HRO, "Capacity") },
{ FLDATAD (STOP_IOE, rs_stopioe, 0, "stop on I/O error") },
{ NULL }
};
MTAB rs_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "MASSBUS", NULL, NULL, &mba_show_num, NULL, "Display Massbus Address" },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL, NULL, NULL, "Write enable disk drive" },
{ UNIT_WLK, UNIT_WLK, "write lockable", "LOCKED", NULL, NULL, NULL, "Write lock disk drive" },
{ (UNIT_DTYPE|UNIT_ATT), (RS03_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RS03", NULL, NULL },
{ (UNIT_DTYPE|UNIT_ATT), (RS04_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RS04", NULL, NULL },
{ (UNIT_AUTO|UNIT_DTYPE|UNIT_ATT), (RS03_DTYPE << UNIT_V_DTYPE),
mctl_unit MCTL unit list
mctl_reg MCTL register list
mctl_mod MCTL modifier list
*/
#define IOLN_MEM 040
DIB mctl_dib = {
IOBA_AUTO, IOLN_MEM, &mctl_rd, &mctl_wr,
1, 0, 0, { NULL }
};
UNIT mctl_unit = { UDATA (NULL, 0, 0) };
REG mctl_reg[] = {
{ DRDATAD (COUNT, mctl_count, 16, "Memory Module Count") },
{ BRDATAD (CSR, mctl_csr, DEV_RDX, 16, MAX_MCTL_COUNT, "control/status registers") },
{ NULL }
};
DEVICE mctl_dev = {
"MCTL", &mctl_unit, mctl_reg, NULL,
1, DEV_RDX, 20, 1, DEV_RDX, 8,
NULL, NULL, &mctl_reset,
NULL, NULL, NULL,
&mctl_dib, DEV_QBUS, 0, NULL, NULL, NULL, NULL, NULL, NULL,
&mctl_description
};
/* I/O dispatch routines */
t_stat ng_show_scale(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat ng_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
const char *ng_description (DEVICE *dptr);
#define IOLN_NG 4
DIB ng_dib = {
IOBA_AUTO, IOLN_NG, &ng_rd, &ng_wr,
4, IVCL(NG), VEC_AUTO, {NULL}, IOLN_NG
};
UNIT ng_unit = {
UDATA (&ng_svc, 0, 0), NG_DELAY
};
REG ng_reg[] = {
{ DRDATAD (CYCLE, ng_unit.wait, 24, "NG cycle"), REG_NZ + PV_LEFT },
{ GRDATAD(TYPE, ng_type, 16, 16, 0, "Hardware type"), REG_FIT},
{ GRDATAD(SCALE, ng_scale, 16, 16, 0, "Hardware type"), REG_FIT},
{ NULL }
};
MTAB ng_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "TYPE", "TYPE={DAZZLE|LOGO}",
&ng_set_type, &ng_show_type, NULL, "Hardware Type" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "SCALE", "SCALE={1|2|4|8}",
&ng_set_scale, &ng_show_scale, NULL, "Pixel Scale Factor" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 020, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL, "Interrupt vector" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
dli_reg DLI register list
*/
#define IOLN_DL 010
DIB dli_dib = {
IOBA_AUTO, IOLN_DL * DLX_LINES, &dlx_rd, &dlx_wr,
2, IVCL (DLI), VEC_AUTO, { &dli_iack, &dlo_iack }, IOLN_DL,
};
UNIT dli_unit = { UDATA (&dli_svc, 0, 0), TMLN_SPD_9600_BPS };
REG dli_reg[] = {
{ BRDATA (BUF, dli_buf, DEV_RDX, 16, DLX_LINES) },
{ BRDATA (CSR, dli_csr, DEV_RDX, 16, DLX_LINES) },
{ DRDATAD (TIME, dli_unit.wait, 24, "input polling interval"), PV_LEFT },
{ GRDATA (IREQ, dli_ireq[DLI_RCI], DEV_RDX, DLX_LINES, 0) },
{ GRDATA (DSI, dli_ireq[DLI_DSI], DEV_RDX, DLX_LINES, 0) },
{ DRDATA (LINES, dlx_desc.lines, 6), REG_HRO },
{ GRDATA (DEVADDR, dli_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVIOLN, dli_dib.lnt, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, dli_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB dli_mod[] = {
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dlx_desc },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &dlx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
{ HRDATAD (RXCS, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, tti_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ 0 }
};
DEVICE tti_dev = {
"TTI", &tti_unit, tti_reg, tti_mod,
1, 10, 31, 1, 16, 8,
NULL, NULL, &tti_reset,
NULL, NULL, NULL,
ttix_unit TTIx unit descriptor
ttix_reg TTIx register list
ttix_mod TTIx modifiers list
*/
DIB ttix_dib = { DEV_KJ8, 8,
{ &ttix, &ttox, &ttix, &ttox, &ttix, &ttox, &ttix, &ttox } };
UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), SERIAL_IN_WAIT };
REG ttix_reg[] = {
{ BRDATAD (BUF, ttix_buf, 8, 8, TTX_LINES, "input buffer, lines 0 to 3") },
{ GRDATAD (DONE, dev_done, 8, TTX_LINES, INT_V_TTI1, "device done flag (line 0 rightmost)") },
{ GRDATAD (ENABLE, int_enable, 8, TTX_LINES, INT_V_TTI1, "interrupt enable flag") },
{ GRDATAD (INT, int_req, 8, TTX_LINES, INT_V_TTI1, "interrupt pending flag") },
{ DRDATAD (TIME, ttix_unit.wait, 24, "initial polling interval"), REG_NZ + PV_LEFT },
{ DRDATAD (TPS, ttx_tps, 10, "polls per second after calibration"), REG_NZ + PV_LEFT },
{ ORDATA (DEVNUM, ttix_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB ttix_mod[] = {
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &tmxr_show_cstat, (void *) &ttx_desc },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
{ HRDATAD (CSR, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") },
{ FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};
DEVICE tti_dev = {
"TTI", &tti_unit, tti_reg, tti_mod,
1, 10, 31, 1, 16, 8,
NULL, NULL, &tti_reset,
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
extern DEVICE ptr_dev;
REG ptr_reg[] = {
{ GRDATAD (BUF, ptr_unit.buf, DEV_RDX, 8, 0, "last data item processed") },
{ GRDATAD (CSR, ptr_csr, DEV_RDX, 16, 0, "control/status register") },
{ FLDATAD (INT, int_req, INT_V_PTR, "interrupt pending flag") },
{ FLDATAD (ERR, ptr_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (BUSY, ptr_csr, CSR_V_BUSY, "busy flag (CSR<11>)") },
{ FLDATAD (DONE, ptr_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, ptr_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, ptr_unit.pos, T_ADDR_W, "position in the input file"), PV_LEFT },
{ DRDATAD (TIME, ptr_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ FLDATAD (STOP_IOE, ptr_stopioe, 0, "stop on I/O error") },
{ FLDATA (DEVDIS, ptr_dev.flags, DEV_V_DIS), REG_HRO },
{ GRDATA (DEVADDR, ptr_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, ptr_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB ptr_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ 0 }
};
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) }
};
#define FIF_NAME "IMSAI"
static const char* fif_description(DEVICE *dptr) {
return FIF_NAME;
}
static REG fif_reg[] = {
{ DRDATAD (DISK, current_disk, 4,
"Current selected disk") },
{ DRDATAD (DSKWL, warnLevelDSK, 32,
"Warn level register") },
{ BRDATAD (WARNATTACHED, warnAttached, 10, 32, NUM_OF_DSK,
"Count for selection of unattached disk register array"), REG_CIRC + REG_RO },
{ DRDATAD (WARNDSK11, warnDSK11, 4,
"Count of IN/OUT(9) on unattached disk register"), REG_RO },
{ NULL }
};
static MTAB fif_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE",
&set_iobase, &show_iobase, NULL, "Sets disk controller I/O base address" },
/* quiet, no warning messages */
{ UNIT_DSK_VERBOSE, 0, "QUIET", "QUIET",
NULL, NULL, NULL, "No verbose messages for unit " FIF_NAME "n" },
*/
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
REG ptr_reg[] = {
{ ORDATAD (BUF, ptr_unit.buf, 18, "last data item processed") },
{ FLDATA (UC, ptr_uc, UC_V) },
{ FLDATAD (DONE, iosta, IOS_V_PTR, "device done flag") },
{ FLDATAD (RPLS, cpls, CPLS_V_PTR, "return restart pulse flag") },
{ ORDATA (HOLD, ptr_hold, 9), REG_HRO },
{ ORDATA (STATE, ptr_state, 5), REG_HRO },
{ FLDATA (WAIT, ptr_wait, 0), REG_HRO },
{ DRDATAD (POS, ptr_unit.pos, T_ADDR_W, "position in the input file"), PV_LEFT },
{ DRDATAD (TIME, ptr_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ DRDATA (LEADER, ptr_leader, 6), REG_HRO },
{ FLDATAD (STOP_IOE, ptr_stopioe, 0, "stop on I/O error") },
{ DRDATA (SBSLVL, ptr_sbs, 4), REG_HRO },
{ NULL }
};
MTAB ptr_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "SBSLVL", "SBSLVL",
&dev_set_sbs, &dev_show_sbs, (void *) &ptr_sbs },
{ UNIT_ASCII, UNIT_ASCII, "ASCII", NULL, NULL },
{ UNIT_ASCII, 0, "FIODEC", NULL, NULL },
{ 0 }
};
