Beispiel #1
0
bool mtk_detect_key (unsigned short key)  /* key: HW keycode */
{
    unsigned short idx, bit, din;
    U32 just_rst;

    if (key >= KPD_NUM_KEYS)
        return false;

    if (key % 9 == 8)
        key = 8;
	
#if 0 //KPD_PWRKEY_USE_EINT 
    if (key == 8)
    {                         /* Power key */
        idx = KPD_PWRKEY_EINT_GPIO / 16;
        bit = KPD_PWRKEY_EINT_GPIO % 16;

        din = DRV_Reg16 (GPIO_DIN_BASE + (idx << 4)) & (1U << bit);
        din >>= bit;
        if (din == KPD_PWRKEY_GPIO_DIN)
        {
            print ("power key is pressed\n");
            return true;
        }
        return false;
    }
Beispiel #2
0
void MT6573_wdt_ModeSelection(kal_bool en, kal_bool auto_rstart, kal_bool IRQ )
{
	unsigned short tmp;
    
	tmp = DRV_Reg16(MT6573_WDT_MODE);
	tmp |= MT6573_WDT_MODE_KEY;
	
	// Bit 0 : Whether enable watchdog or not
	if(en == KAL_TRUE)
		tmp |= MT6573_WDT_MODE_ENABLE;
	else
		tmp &= ~MT6573_WDT_MODE_ENABLE;
	
	// Bit 4 : Whether enable auto-restart or not for counting value
	if(auto_rstart == KAL_TRUE)
		tmp |= MT6573_WDT_MODE_AUTORST;
	else
		tmp &= ~MT6573_WDT_MODE_AUTORST;

	// Bit 3 : TRUE for generating Interrupt (False for generating Reset) when WDT timer reaches zero
	if(IRQ == KAL_TRUE)
		tmp |= MT6573_WDT_RESET_IRQ;
	else
		tmp &= ~MT6573_WDT_RESET_IRQ;

	DRV_WriteReg16(MT6573_WDT_MODE,tmp);
}
Beispiel #3
0
unsigned int MT6573_wdt_CheckStatus(void)
{
	unsigned int status;
	
	status = DRV_Reg16(MT6573_WDT_STATUS);
	
	return status;
}
unsigned int mtk_wdt_check_status(void)
{
    unsigned int status;

    status = DRV_Reg16(MTK_WDT_STATUS);

    return status;
}
Beispiel #5
0
bool WDT_boot_check(void)
{
	if (WDT_INGORE_POWER_KEY == DRV_Reg16(MT6573_WDT_INTERNAL)) 
  	{
  		return true;
  	}
  	return false; 
}
Beispiel #6
0
unsigned int GPIO_ReadIO( unsigned int pin)
{
    unsigned int no;
    unsigned int remainder;
    unsigned short data;
    no = pin >>4;
    remainder = pin & 0xf ;

    data=DRV_Reg16(GPIO_DIN(no));   
    data=data &(1 << remainder);
    data=(data >> remainder);
    return (unsigned int)data;
}
Beispiel #7
0
BOOL mtk_detect_key(unsigned short key)	/* key: HW keycode */
{
/* Because 6572 FPGA doesn't include keypad HW,
 * add FPGA macro to avoid misjudgment 
 */
#ifdef MACH_FPGA
	return FALSE;
#else
	unsigned short idx, bit, din;

	if (key >= KPD_NUM_KEYS)
		return FALSE;

	if (key % 9 == 8)
		key = 8;

	if (key == 8)
    	{ /* Power key */
		if (1 == pmic_detect_powerkey())
		{
			//dbg_print ("power key is pressed\n");
			return TRUE;
		}
		return FALSE;
	}

#ifdef MT65XX_PMIC_RST_KEY
	if(key == MT65XX_PMIC_RST_KEY)
	{
		if (1 == pmic_detect_homekey())
		{
			printf("mtk detect key function pmic_detect_homekey pressed\n");
			return TRUE;
		}
		return FALSE;
	}
#endif

	idx = key / 16;
	bit = key % 16;

	din = DRV_Reg16(KP_MEM1 + (idx << 2)) & (1U << bit);
	if (!din) {
		printf("key %d is pressed\n", key);
		return TRUE;
	}
	return FALSE;
#endif
}
Beispiel #8
0
BOOL mtk_detect_key(unsigned short key)	/* key: HW keycode */
{
#ifdef MACH_FPGA /* FPGA doesn't include keypad HW */
	return FALSE;
#else
	unsigned short idx, bit, din;

	if (key >= KPD_NUM_KEYS)
		return FALSE;
#if 0
	if (key % 9 == 8)
		key = 8;
#endif
	if (key == MTK_PMIC_PWR_KEY)
    	{ /* Power key */
		if (1 == pmic_detect_powerkey())
		{
			//dbg_print ("power key is pressed\n");
			return TRUE;
		}
		return FALSE;
	}

#ifdef MTK_PMIC_RST_KEY
	if (key == MTK_PMIC_RST_KEY)
	{
		if (1 == pmic_detect_homekey())
		{
			printf("mtk detect key function pmic_detect_homekey pressed\n");
			return TRUE;
		}
		return FALSE;
	}
#endif

	idx = key / 16;
	bit = key % 16;

	din = DRV_Reg16(KP_MEM1 + (idx << 2)) & (1U << bit);
	if (!din) {
		printf("key %d is pressed\n", key);
		return TRUE;
	}
	return FALSE;
#endif /* MACH_FPGA */
}
Beispiel #9
0
BOOL mtk_detect_key(unsigned short key)	/* key: HW keycode */
{
	unsigned short idx, bit, din;

	if (key >= KPD_NUM_KEYS)
		return FALSE;

	if (key % 9 == 8)
		key = 8;

    if (key == 8)
    {                         /* Power key */
        if (1 == pmic_detect_powerkey())
        {
            //dbg_print ("power key is pressed\n");
            return TRUE;
        }
        return FALSE;
    }    

#ifdef MT65XX_PMIC_RST_KEY

	if (key == MT65XX_PMIC_RST_KEY) 
	{
		//printf("mtk detect key pmic_detect_homekey= %d\n" ,pmic_detect_homekey());	
		if (0 == pmic_detect_homekey()) //LINE<20120502><homekey pressed>wangyanhui
		{
			printf("mtk detect key function pmic_detect_homekey pressed\n");
			return TRUE;
		}
		// return FALSE; //LINE<20120502><for PR1 board>wangyanhui
	}
#endif

	idx = key / 16;
	bit = key % 16;

	din = DRV_Reg16(KP_MEM1 + (idx << 2)) & (1U << bit);
	if (!din) {
	printf("key %d is pressed\n", key);
		return TRUE;
	}
	return FALSE;
}
static void mtk_wdt_mode_config(BOOL debug_en, 
                         BOOL irq, 
                         BOOL ext_en, 
                         BOOL ext_pol, 
                         BOOL wdt_en )
{
    unsigned short tmp;

    tmp = DRV_Reg16(MTK_WDT_MODE);
    tmp |= MTK_WDT_MODE_KEY;

    // Bit 0 : Whether enable watchdog or not
    if(wdt_en == TRUE)
        tmp |= MTK_WDT_MODE_ENABLE;
    else
        tmp &= ~MTK_WDT_MODE_ENABLE;

    // Bit 1 : Configure extern reset signal polarity.
    if(ext_pol == TRUE)
        tmp |= MTK_WDT_MODE_EXT_POL;
    else
        tmp &= ~MTK_WDT_MODE_EXT_POL;

    // Bit 2 : Whether enable external reset signal
    if(ext_en == TRUE)
        tmp |= MTK_WDT_MODE_EXTEN;
    else
        tmp &= ~MTK_WDT_MODE_EXTEN;

    // Bit 3 : Whether generating interrupt instead of reset signal
    if(irq == TRUE)
        tmp |= MTK_WDT_MODE_IRQ;
    else
        tmp &= ~MTK_WDT_MODE_IRQ;

    // Bit 6 : Whether enable debug module reset
    if(debug_en == TRUE)
        tmp |= MTK_WDT_MODE_DEBUG_EN;
    else
        tmp &= ~MTK_WDT_MODE_DEBUG_EN;

    DRV_WriteReg16(MTK_WDT_MODE,tmp);
}
/**************************************************************************
 *  Handle Flash Information Sent From Flash Tool
 **************************************************************************/
void handle_pl_info (void)
{
    DM_PL_INFO_PACKET plip = {0};
    DM_ENTRY_LOG ();
    plip.pattern = DM_PL_INFO_PKT_PATN;
    plip.chip = DRV_Reg16 (APHW_CODE);

    // fill _DM_FLASH_INFO according to NAND exported info.         
    plip.flash_info.man_code = nand_maf_id;
    plip.flash_info.dev_id = g_nand_chip.id;
    plip.flash_info.dev_code = nand_dev_id;
    plip.flash_info.dev_size = g_nand_chip.chipsize;
    plip.flash_info.page_size = g_nand_chip.page_size;
    plip.flash_info.spare_size = g_nand_chip.oobsize;

    // fill dm descriptor according to NAND exported info.          
    dm_ctx.block_size = g_nand_chip.erasesize;
    dm_ctx.page_size = g_nand_chip.page_size;
    dm_ctx.spare_size = g_nand_chip.oobsize;

    DM_LOG ("----------------------------------------\n");
    DM_LOG ("g_nand_chip.page_shift    = %x\n", g_nand_chip.page_shift);
    DM_LOG ("g_nand_chip.page_size     = %x\n", g_nand_chip.page_size);
    DM_LOG ("g_nand_chip.ChipID        = %x\n", g_nand_chip.ChipID);
    DM_LOG ("g_nand_chip.chips_name    = %x\n", g_nand_chip.chips_name);
    DM_LOG ("g_nand_chip.chipsize      = %x\n", g_nand_chip.chipsize);
    DM_LOG ("g_nand_chip.erasesize     = %x\n", g_nand_chip.erasesize);
    DM_LOG ("g_nand_chip.mfr           = %x\n", g_nand_chip.mfr);
    DM_LOG ("g_nand_chip.id            = %x\n", g_nand_chip.id);
    DM_LOG ("g_nand_chip.name          = %x\n", g_nand_chip.name);
    DM_LOG ("g_nand_chip.numchips      = %x\n", g_nand_chip.numchips);
    DM_LOG ("g_nand_chip.oobblock      = %x\n", g_nand_chip.oobblock);
    DM_LOG ("g_nand_chip.oobsize       = %x\n", g_nand_chip.oobsize);
    DM_LOG ("g_nand_chip.eccsize       = %x\n", g_nand_chip.eccsize);
    DM_LOG ("g_nand_chip.bus16         = %x\n", g_nand_chip.bus16);
    DM_LOG ("g_nand_chip.nand_ecc_mode = %x\n", g_nand_chip.nand_ecc_mode);
    DM_LOG ("----------------------------------------\n");

    dm_ctx.img_info.pkt_size = dm_ctx.page_size + dm_ctx.spare_size;
    mt_usbtty_putcn (DM_SZ_PL_INFO_PKT, (u8 *) & plip, TRUE);
}
void mtk_wdt_init(void)
{
    unsigned short interval_val = DRV_Reg16(MTK_WDT_INTERVAL);
    mtk_wdt_mode_config(FALSE, FALSE, FALSE, FALSE, FALSE);
    printf("UB wdt init\n");

    /* Update interval register value and check reboot flag */
    if( (interval_val & RGU_TRIGGER_RESET_MASK) == IS_POWER_ON_RESET )
        is_rgu_trigger_rst = 0; // Power off and power on reset
    else
        is_rgu_trigger_rst = 1; // RGU trigger reset

    interval_val &= ~(RGU_TRIGGER_RESET_MASK|MAGIC_NUM_MASK);
    interval_val |= (U_BOOT_MAGIC|IS_POWER_ON_RESET);

    /* Write back INTERVAL REG */
    DRV_WriteReg(MTK_WDT_INTERVAL, interval_val);
	/* Setting timeout 10s */
	mtk_wdt_set_time_out_value(10);
	mtk_wdt_mode_config(TRUE, FALSE, FALSE, FALSE, TRUE);
	mtk_wdt_restart();
	
}
Beispiel #13
0
static void slp_dump_pm_regs(void)
{
    /* PLL registers */
    
    printf("CLKSQ_CON0           0x%x = 0x%x\n", CLKSQ_CON0             , DRV_Reg16(CLKSQ_CON0));
    printf("PLL_CON1             0x%x = 0x%x\n", PLL_CON1               , DRV_Reg16(PLL_CON1));
    printf("PLL_CON2             0x%x = 0x%x\n", PLL_CON2               , DRV_Reg16(PLL_CON2));
    printf("ARMPLL_CON0          0x%x = 0x%x\n", ARMPLL_CON0            , DRV_Reg16(ARMPLL_CON0));
    printf("MAINPLL_CON0         0x%x = 0x%x\n", MAINPLL_CON0           , DRV_Reg16(MAINPLL_CON0));
    printf("IPLL_CON0            0x%x = 0x%x\n", IPLL_CON0              , DRV_Reg16(IPLL_CON0));
    printf("UPLL_CON0            0x%x = 0x%x\n", UPLL_CON0              , DRV_Reg16(UPLL_CON0));
    printf("MDPLL_CON0           0x%x = 0x%x\n", MDPLL_CON0             , DRV_Reg16(MDPLL_CON0));
    printf("WPLL_CON0            0x%x = 0x%x\n", WPLL_CON0              , DRV_Reg16(WPLL_CON0));
    printf("AUDPLL_CON0          0x%x = 0x%x\n", AUDPLL_CON0            , DRV_Reg16(AUDPLL_CON0));
    printf("MEMPLL_CON0          0x%x = 0x%x\n", MEMPLL_CON0            , DRV_Reg16(MEMPLL_CON0));
    
    /* TOPCKGEN/PERICFG registers */
    
    printf("TOP_CKMUXSEL         0x%x = 0x%x\n", TOP_CKMUXSEL           , DRV_Reg32(TOP_CKMUXSEL));
    printf("TOP_DCMCTL           0x%x = 0x%x\n", TOP_DCMCTL             , DRV_Reg32(TOP_DCMCTL));
    printf("TOP_MISC             0x%x = 0x%x\n", TOP_MISC               , DRV_Reg32(TOP_MISC));
    printf("TOP_CKCTL            0x%x = 0x%x\n", TOP_CKCTL              , DRV_Reg32(TOP_CKCTL));
    printf("GLOBALCON_PDN0       0x%x = 0x%x\n", PERI_GLOBALCON_PDN0    , DRV_Reg32(PERI_GLOBALCON_PDN0));
    printf("GLOBALCON_PDN1       0x%x = 0x%x\n", PERI_GLOBALCON_PDN1    , DRV_Reg32(PERI_GLOBALCON_PDN1));
    printf("GLOBALCON_DCMCTL     0x%x = 0x%x\n", PERI_GLOBALCON_DCMCTL  , DRV_Reg32(PERI_GLOBALCON_DCMCTL));
    
    /* SLPCTRL registers */
    
    printf("SC_CLK_SETTLE        0x%x = 0x%x\n", SC_CLK_SETTLE          , DRV_Reg32(SC_CLK_SETTLE));
    printf("SC_PWR_SETTLE        0x%x = 0x%x\n", SC_PWR_SETTLE          , DRV_Reg32(SC_PWR_SETTLE));
    printf("SC_PWR_CON0          0x%x = 0x%x\n", SC_PWR_CON0            , DRV_Reg32(SC_PWR_CON0));
    printf("SC_PWR_CON1          0x%x = 0x%x\n", SC_PWR_CON1            , DRV_Reg32(SC_PWR_CON1));
    printf("SC_PWR_CON2          0x%x = 0x%x\n", SC_PWR_CON2            , DRV_Reg32(SC_PWR_CON2));
    printf("SC_PWR_CON3          0x%x = 0x%x\n", SC_PWR_CON3            , DRV_Reg32(SC_PWR_CON3));
    printf("SC_PWR_CON4          0x%x = 0x%x\n", SC_PWR_CON4            , DRV_Reg32(SC_PWR_CON4));
    printf("SC_PWR_CON5          0x%x = 0x%x\n", SC_PWR_CON5            , DRV_Reg32(SC_PWR_CON5));
    printf("SC_PWR_CON6          0x%x = 0x%x\n", SC_PWR_CON6            , DRV_Reg32(SC_PWR_CON6));
    printf("SC_PWR_CON7          0x%x = 0x%x\n", SC_PWR_CON7            , DRV_Reg32(SC_PWR_CON7));
    printf("SC_PWR_CON8          0x%x = 0x%x\n", SC_PWR_CON8            , DRV_Reg32(SC_PWR_CON8));
    printf("SC_PWR_CON9          0x%x = 0x%x\n", SC_PWR_CON9            , DRV_Reg32(SC_PWR_CON9));
    printf("SC_CLK_CON           0x%x = 0x%x\n", SC_CLK_CON             , DRV_Reg32(SC_CLK_CON));
    printf("SC_MD_CLK_CON        0x%x = 0x%x\n", SC_MD_CLK_CON          , DRV_Reg32(SC_MD_CLK_CON));
    printf("SC_MD_INTF_CON       0x%x = 0x%x\n", SC_MD_INTF_CON         , DRV_Reg32(SC_MD_INTF_CON));
    printf("SC_MD_INTF_STS       0x%x = 0x%x\n", SC_MD_INTF_STS         , DRV_Reg32(SC_MD_INTF_STS));
    printf("SC_TMR_PWR           0x%x = 0x%x\n", SC_TMR_PWR             , DRV_Reg32(SC_TMR_PWR));
    printf("SC_DBG_CON           0x%x = 0x%x\n", SC_DBG_CON             , DRV_Reg32(SC_DBG_CON));
    printf("SC_PERI_CON          0x%x = 0x%x\n", SC_PERI_CON            , DRV_Reg32(SC_PERI_CON));
    printf("SC_STATE             0x%x = 0x%x\n", SC_STATE               , DRV_Reg32(SC_STATE));
    printf("SC_PWR_STA           0x%x = 0x%x\n", SC_PWR_STA             , DRV_Reg32(SC_PWR_STA));
    printf("SC_APMCU_PWRCTL      0x%x = 0x%x\n", SC_APMCU_PWRCTL        , DRV_Reg32(SC_APMCU_PWRCTL));
    printf("SC_AP_DVFS_CON       0x%x = 0x%x\n", SC_AP_DVFS_CON         , DRV_Reg32(SC_AP_DVFS_CON));
    printf("SC_AP_STANBY_EXT     0x%x = 0x%x\n", SC_AP_STANBY_EXT       , DRV_Reg32(SC_AP_STANBY_EXT));
    printf("SC_TIMER_CON         0x%x = 0x%x\n", SC_TIMER_CON           , DRV_Reg32(SC_TIMER_CON));
    printf("SC_TIMER_CMD         0x%x = 0x%x\n", SC_TIMER_CMD           , DRV_Reg32(SC_TIMER_CMD));
    printf("SC_TIMER_STA         0x%x = 0x%x\n", SC_TIMER_STA           , DRV_Reg32(SC_TIMER_STA));
    printf("SC_FINAL_PAUSE       0x%x = 0x%x\n", SC_FINAL_PAUSE         , DRV_Reg32(SC_FINAL_PAUSE));
    printf("SC_PAUSE             0x%x = 0x%x\n", SC_PAUSE               , DRV_Reg32(SC_PAUSE));
    printf("SC_DBG_WAKEUP        0x%x = 0x%x\n", SC_DBG_WAKEUP          , DRV_Reg32(SC_DBG_WAKEUP));
    printf("SC_WAKEUP_SRC        0x%x = 0x%x\n", SC_WAKEUP_SRC          , DRV_Reg32(SC_WAKEUP_SRC));
    printf("SC_WAKEUP_EVENT_MASK 0x%x = 0x%x\n", SC_WAKEUP_EVENT_MASK   , DRV_Reg32(SC_WAKEUP_EVENT_MASK));
    printf("SC_ISR_MASK          0x%x = 0x%x\n", SC_ISR_MASK            , DRV_Reg32(SC_ISR_MASK));
    printf("SC_ISR_STATUS        0x%x = 0x%x\n", SC_ISR_STATUS          , DRV_Reg32(SC_ISR_STATUS));
}
PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
	SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;

	
	if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0)
	{
		return PVRSRV_OK;
	}

	PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks"));

#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) && defined(CONFIG_PM_RUNTIME)
	{
		
		int res = pm_runtime_get_sync(&gpsPVRLDMDev->dev);
		if (res < 0)
		{
			PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: pm_runtime_get_sync failed (%d)", -res));
			return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
		}
	}
#endif


	//disable_clock(MT65XX_PDN_MM_MFG_HALF, "MFG");
	//disable_clock(MT65XX_PDN_MM_MFG, "MFG");
	//disable_clock(MT65XX_PDN_MM_G3D, "MFG");

#if USE_SYS_CLOCK
    #if !defined(MTK_CLK_CTRL)
	DRV_WriteReg16(PLL_CON11, DRV_Reg16(PLL_CON11)|0x0C00); // F3D_CK_SEL
    #endif
	DRV_WriteReg32(MMSYS2_CONFG_BASE + 0x0504, 0x4); // MFG_CORE_CK_SEL DCM
#else
    #if !defined(MTK_CLK_CTRL)
	DRV_WriteReg16(PLL_CON11, DRV_Reg16(PLL_CON11)|0x0C00); // F3D_CK_SEL
    #endif
	DRV_WriteReg32(MMSYS2_CONFG_BASE + 0x0504, 0x6); // MFG_CORE_CK_SEL DCM
#endif

	//DRV_WriteReg32(MMSYS2_CONFG_BASE+0x400, DRV_Reg32(MMSYS2_CONFG_BASE+0x400)|0x4);
	enable_clock(MT65XX_PDN_MM_G3D, "MFG");
	enable_clock(MT65XX_PDN_MM_MFG, "MFG");
	enable_clock(MT65XX_PDN_MM_MFG_HALF, "MFG");
	DRV_WriteReg32(MMSYS2_CONFG_BASE+0x400, DRV_Reg32(MMSYS2_CONFG_BASE+0x400)|0x4);


#if defined(MTK_USE_GDC)
	SysInitGDC();
#endif

#if 0
	DRV_WriteReg16(0xF0007404, 0x6);
	DRV_WriteReg16(0xF0007400, 0x4800);
	DRV_WriteReg16(0xF0007400, 0x0800);
	DRV_WriteReg16(0xF0007400, 0x8800);
	while(DRV_Reg16(0xF0007404) & 0x8000){}
	PVRSRVReleasePrintf("MainPLL: 0x%x", DRV_Reg16(0xF0007410));

	DRV_WriteReg16(0xF0007404, 0x15);
	DRV_WriteReg16(0xF0007400, 0x4800);
	DRV_WriteReg16(0xF0007400, 0x0800);
	DRV_WriteReg16(0xF0007400, 0x8800);
	while(DRV_Reg16(0xF0007404) & 0x8000){}
	PVRSRVReleasePrintf("MEMPLL: 0x%x", DRV_Reg16(0xF0007410));
#endif

	SysEnableSGXInterrupts(psSysData);

	atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);

#else	
	PVR_UNREFERENCED_PARAMETER(psSysData);
#endif
	return PVRSRV_OK;
}
Beispiel #15
0
kal_uint16 mtk_cpe_one_shot_handler(kal_uint16 path1, kal_uint16 path2, kal_uint16 path3)
{
    kal_uint16 count, try_count, ret;
    
    DRV_WriteReg16(CA9_ROSC_CON0, 0x8);  // reset the overflow bit of CA9 frequency meter
    DRV_WriteReg16(CA9_ROSC_CON0, 0x4);  // reset the circuit of CA9 frequency meter
    
    DRV_WriteReg16(CA9_ROSC_MON_CTRL_0, 0x0);   // switch back to CA9 control
    
    DRV_WriteReg16(CA9_ROSC_CON3, path1);  // CA9 ROSC delay path selection [15:0]
    DRV_WriteReg16(CA9_ROSC_CON4, path2);  // CA9 ROSC delay path selection [31:16]
    DRV_WriteReg16(CA9_ROSC_CON5, path3);  // CA9 ROSC delay path selection [47:32]
    
    ret = DRV_Reg16(CA9_ROSC_CON6); // CA9 ROSC toggle count during window is high
    cpe_dprintk("[before toggling] the CA9 frequency meter value is %d\n", ret);
    
    DRV_WriteReg16(CA9_ROSC_CON0, 0x5);  // enable ROSC to start
    
    DRV_WriteReg16(CA9_ROSC_CON1, 0x44); // frequency meter window duration
    DRV_WriteReg16(CA9_ROSC_CON2, 0x1);  // frequency meter clock divider
    
    DRV_WriteReg16(CA9_ROSC_CON0, 0x7);  // reload window duration, enable ROSC to start and start to count
    
    try_count = 5;
    ret = DRV_Reg16(CA9_ROSC_CON6); // CA9 ROSC toggle count during window is high
    while (ret == 0 && try_count--)
    {
        ret = DRV_Reg16(CA9_ROSC_CON6); // CA9 ROSC toggle count during window is high
        udelay(10);
    }
    
    try_count = 5;
    while (try_count--)
    {
        while (1)
        {
            ret = DRV_Reg16(CA9_ROSC_CON6); // CA9 ROSC toggle count during window is high
            udelay(10);
            
            if (ret == DRV_Reg16(CA9_ROSC_CON6)) break;
        }
        
        ret = DRV_Reg16(CA9_ROSC_CON_STATUS);
        if ((ret & CA9_FQMTR_BUSY) == 0)
        {
            break;
        }
        else
        {
            udelay(10);
        }
    }
    
    ret = DRV_Reg16(CA9_ROSC_CON_STATUS);
    if ((ret & CA9_FQMTR_OVERFLOW) == CA9_FQMTR_OVERFLOW)
        cpe_dprintk("overflow condition occurred\n");
    
    count = DRV_Reg16(CA9_ROSC_CON6); // CA9 ROSC toggle count during window is high
    cpe_dprintk("[after  toggling] the CA9 frequency meter value is %d\n", count);
    
    DRV_WriteReg16(CA9_ROSC_MON_CTRL_0, 0x0);   // switch back to CA9 control
    
    DRV_WriteReg16(CA9_ROSC_CON0, 0x8);  // disable ROSC and reset the overflow bit of CA9 frequency meter
    DRV_WriteReg16(CA9_ROSC_CON0, 0x4);  // reset the circuit of CA9 frequency meter
    
    return count;
}