dsi_s_1080p_5_gpio_requested = true;
return 0;
fail:
return err;
}
static u8 panel_internal[] = {0x51, 0x0f, 0xff};
static struct tegra_dsi_cmd dsi_s_1080p_5_init_cmd[] = {
DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xb0, 0x04),
DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_NO_OP, 0x0),
DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_NO_OP, 0x0),
DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xd6, 0x01),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_internal),
DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0x53, 0x04),
DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0),
DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0),
DSI_DLY_MS(10),
DSI_SEND_FRAME(7),
};
static struct tegra_dsi_cmd dsi_s_1080p_5_suspend_cmd[] = {
DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_OFF, 0x0),
DSI_DLY_MS(50),
DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_ENTER_SLEEP_MODE, 0x0),
DSI_DLY_MS(10),
};
static struct tegra_dsi_out dsi_s_1080p_5_pdata = {
static struct tegra_dsi_cmd dsi_init_cmd[] = {
DSI_CMD_SHORT(0x05, 0x11, 0x00),
DSI_DLY_MS(150),
#if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
DSI_CMD_SHORT(0x15, 0x35, 0x00),
#endif
DSI_CMD_SHORT(0x05, 0x29, 0x00),
DSI_DLY_MS(20),
};
u8 password_array[] = {0xb9, 0xff, 0x83, 0x92};
static struct tegra_dsi_cmd dsi_init_cmd_1506[] = {
DSI_CMD_SHORT(0x05, 0x11, 0x00),
DSI_DLY_MS(150),
DSI_CMD_LONG(0x39, password_array),
DSI_DLY_MS(10),
DSI_CMD_SHORT(0x15, 0xd4, 0x0c),
DSI_DLY_MS(10),
DSI_CMD_SHORT(0x15, 0xba, 0x11),
DSI_DLY_MS(10),
#if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
DSI_CMD_SHORT(0x15, 0x35, 0x00),
#endif
DSI_CMD_SHORT(0x05, 0x29, 0x00),
DSI_DLY_MS(20),
};
static struct tegra_dsi_cmd dsi_early_suspend_cmd[] = {
DSI_CMD_SHORT(0x05, 0x28, 0x00),
DSI_DLY_MS(20),
static u8 panel_ce6[] = {0x75, 0x03, 0x0, 0x07};
static u8 panel_ce7[] = {0x76, 0x07, 0x0, 0x06};
static u8 panel_ce8[] = {0x77, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f};
static u8 panel_ce9[] = {0x78, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40};
static u8 panel_ce10[] = {
0x79, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40};
static u8 panel_ce11[] = {0x7a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
static u8 panel_ce12[] = {0x7b, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
static u8 panel_ce13[] = {0x7c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
#endif
static struct tegra_dsi_cmd dsi_init_cmd[] = {
DSI_DLY_MS(20),
DSI_GPIO_SET(0, 1), /* use dummy gpio */
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_dsi_config),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_disp_ctrl1),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_disp_ctrl2),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_internal_clk),
/* panel power control 1 */
DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc1, 0x0),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_pwr_ctrl3),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_pwr_ctrl4),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_red),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_red),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_green),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_green),
180, 181, 182, 183, 184, 185, 186, 187,
188, 189, 190, 191, 192, 193, 194, 195,
196, 197, 198, 200, 201, 202, 203, 204,
205, 206, 207, 208, 209, 210, 211, 212,
213, 214, 215, 217, 218, 219, 220, 221,
222, 223, 224, 225, 226, 227, 228, 229,
230, 231, 232, 234, 235, 236, 237, 238,
239, 240, 241, 242, 243, 244, 245, 246,
248, 249, 250, 251, 252, 253, 254, 255,
};
u8 fbuf_mode_sel[] = {0x10, 0x00, 0x2A}; /* left-right */
u8 mipi_if_sel[] = {0x10, 0x01, 0x01}; /* cmd mode */
static struct tegra_dsi_cmd dsi_s_wqxga_10_1_init_cmd[] = {
#if DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, fbuf_mode_sel),
DSI_DLY_MS(20),
DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_NO_OP, 0x0),
DSI_DLY_MS(20),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, mipi_if_sel),
DSI_DLY_MS(20),
DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_NO_OP, 0x0),
DSI_DLY_MS(20),
DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM,
DSI_DCS_SET_TEARING_EFFECT_ON, 0x0),
DSI_DLY_MS(20),
#endif
DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0),
DSI_DLY_MS(120),
DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0),
DSI_DLY_MS(20),
{0, 0, 0},
},
},
.sd_brightness = &sd_brightness,
.use_vpulse2 = true,
};
static u8 ce[] = {0xCE, 0x5D, 0x40, 0x48, 0x56, 0x67, 0x78,
0x88, 0x98, 0xA7, 0xB5, 0xC3, 0xD1, 0xDE,
0xE9, 0xF2, 0xFA, 0xFF, 0x05, 0x00, 0x04,
0x04, 0x00, 0x20};
static struct tegra_dsi_cmd dsi_j_qxga_8_9_init_cmd[] = {
DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xB0, 0x04),
DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, ce),
DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xD6, 0x01),
DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xB0, 0x03),
DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0, CMD_NOT_CLUBBED),
DSI_DLY_MS(120),
DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x53, 0x24, CMD_CLUBBED),
DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x55, 0x00, CMD_CLUBBED),
DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x35, 0x00, CMD_CLUBBED),
DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0, CMD_CLUBBED),
};
static struct tegra_dsi_cmd dsi_j_qxga_8_9_suspend_cmd[] = {
DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x51, 0x00, CMD_CLUBBED),
DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_OFF, 0x0, CMD_CLUBBED),
gpio_set_value(DSI_PANEL_RST_GPIO, 1);
mdelay(120);
/*if (avdd_lcd_3v0_2v8)
regulator_disable(avdd_lcd_3v0_2v8);
usleep_range(3000, 5000);
gpio_set_value(pluto_LCD_1V8_EN,0);*/
return 0;
}
static int dsi_auo_720p_5_postsuspend(void)
{
return 0;
}
static struct tegra_dsi_cmd NT35590_AUO_dsi_init_cmd[]= {
DSI_CMD_LONG(0x39,NT35590_AUO_Param1),
DSI_CMD_LONG(0x39,NT35590_AUO_Param2),
DSI_CMD_LONG(0x39,NT35590_AUO_Param3),
DSI_CMD_LONG(0x39,NT35590_AUO_Param4),
DSI_CMD_LONG(0x39,NT35590_AUO_Param5),
DSI_CMD_LONG(0x39,NT35590_AUO_Param6),
DSI_CMD_LONG(0x39,NT35590_AUO_Param7),
DSI_CMD_LONG(0x39,NT35590_AUO_Param8),
DSI_CMD_LONG(0x39,NT35590_AUO_Param9),
DSI_CMD_LONG(0x39,NT35590_AUO_Param10),
DSI_CMD_LONG(0x39,NT35590_AUO_Param11),
DSI_CMD_LONG(0x39,NT35590_AUO_Param12),
DSI_CMD_LONG(0x39,NT35590_AUO_Param13),
DSI_CMD_LONG(0x39,NT35590_AUO_Param14),
DSI_CMD_LONG(0x39,NT35590_AUO_Param15),
DSI_CMD_LONG(0x39,NT35590_AUO_Param16),
