static int dpi_init_display(struct omap_dss_device *dssdev)
{
struct platform_device *dsidev;
DSSDBG("init_display\n");
if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) &&
dpi.vdds_dsi_reg == NULL) {
struct regulator *vdds_dsi;
vdds_dsi = dss_get_vdds_dsi();
if (IS_ERR(vdds_dsi)) {
DSSERR("can't get VDDS_DSI regulator\n");
return PTR_ERR(vdds_dsi);
}
dpi.vdds_dsi_reg = vdds_dsi;
}
dsidev = dpi_get_dsidev(dpi.output.dispc_channel);
if (dsidev && dpi_verify_dsi_pll(dsidev)) {
dsidev = NULL;
DSSWARN("DSI PLL not operational\n");
}
if (dsidev)
DSSDBG("using DSI PLL for DPI clock\n");
dpi.dsidev = dsidev;
return 0;
}
static int hdmi_init_regulator(void)
{
int r;
struct regulator *reg;
if (hdmi.vdda_reg != NULL)
return 0;
reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
if (IS_ERR(reg)) {
DSSERR("can't get VDDA regulator\n");
return PTR_ERR(reg);
}
r = regulator_set_voltage(reg, 1800000, 1800000);
if (r) {
devm_regulator_put(reg);
DSSWARN("can't set the regulator voltage\n");
return r;
}
hdmi.vdda_reg = reg;
return 0;
}
static int dpi_set_mode(struct omap_overlay_manager *mgr)
{
struct omap_video_timings *t = &dpi.timings;
int lck_div = 0, pck_div = 0;
unsigned long fck = 0;
unsigned long pck;
int r = 0;
if (dpi.dsidev)
r = dpi_set_dsi_clk(mgr->id, t->pixel_clock * 1000, &fck,
&lck_div, &pck_div);
else
r = dpi_set_dispc_clk(t->pixel_clock * 1000, &fck,
&lck_div, &pck_div);
if (r)
return r;
pck = fck / lck_div / pck_div / 1000;
if (pck != t->pixel_clock) {
DSSWARN("Could not find exact pixel clock. "
"Requested %d kHz, got %lu kHz\n",
t->pixel_clock, pck);
t->pixel_clock = pck;
}
dss_mgr_set_timings(mgr, t);
return 0;
}
static int dpi_set_mode(struct omap_dss_device *dssdev)
{
struct omap_video_timings *t = &dssdev->panel.timings;
unsigned long pck = 0;
unsigned long cache_req_pck = 0;
bool is_tft;
int r = 0;
dispc_set_pol_freq(dssdev->channel, dssdev->panel.config,
dssdev->panel.acbi, dssdev->panel.acb);
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
r = dpi_set_dsi_clk(dssdev->channel, is_tft,
t->pixel_clock * 1000, &pck);
DSSDBG("dpi_set_mode: dpi_set_dsi_clk=%d\n",r);
#else /* #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL */
cache_req_pck = dss_get_cache_req_pck();
if (cache_req_pck)
r = dpi_set_dispc_clk(dssdev->channel, is_tft,
cache_req_pck, &pck);
else
r = dpi_set_dispc_clk(dssdev->channel, is_tft,
t->pixel_clock * 1000, &pck);
#endif /* CONFIG_OMAP2_DSS_USE_DSI_PLL */
if (r)
return r;
pck /= 1000;
if (pck != t->pixel_clock) {
DSSWARN("Could not find exact pixel clock. "
"Requested %d kHz, got %lu kHz\n",
t->pixel_clock, pck);
t->pixel_clock = pck;
}
DSSDBG("dpi_set_mode: pixel_clock = %d\n", t->pixel_clock);
dispc_set_lcd_timings(dssdev->channel, t);
return 0;
}
static void dpi_init_pll(void)
{
struct platform_device *dsidev;
if (dpi.dsidev)
return;
dsidev = dpi_get_dsidev(dpi.output.dispc_channel);
if (!dsidev)
return;
if (dpi_verify_dsi_pll(dsidev)) {
DSSWARN("DSI PLL not operational\n");
return;
}
dpi.dsidev = dsidev;
}
static int dpi_set_mode(struct omap_dss_device *dssdev)
{
struct omap_video_timings *t = &dssdev->panel.timings;
int lck_div, pck_div;
unsigned long fck;
unsigned long pck;
bool is_tft;
int r = 0;
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
dssdev->panel.acbi, dssdev->panel.acb);
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000, &fck,
&lck_div, &pck_div);
#else
r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000, &fck,
&lck_div, &pck_div);
#endif
if (r)
goto err0;
pck = fck / lck_div / pck_div / 1000;
if (pck != t->pixel_clock) {
DSSWARN("Could not find exact pixel clock. "
"Requested %d kHz, got %lu kHz\n",
t->pixel_clock, pck);
t->pixel_clock = pck;
}
dispc_set_lcd_timings(dssdev->manager->id, t);
err0:
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
return r;
}
static int dpi_set_mode(struct omap_display *display)
{
struct omap_panel *panel = display->panel;
int lck_div, pck_div;
unsigned long fck;
unsigned long pck;
bool is_tft;
int r = 0;
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
dispc_set_pol_freq(panel);
is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
r = dpi_set_dsi_clk(is_tft, panel->timings.pixel_clock * 1000,
&fck, &lck_div, &pck_div);
#else
r = dpi_set_dispc_clk(is_tft, panel->timings.pixel_clock * 1000,
&fck, &lck_div, &pck_div);
#endif
if (r)
goto err0;
pck = fck / lck_div / pck_div / 1000;
if (pck != panel->timings.pixel_clock) {
DSSWARN("Could not find exact pixel clock. "
"Requested %d kHz, got %lu kHz\n",
panel->timings.pixel_clock, pck);
panel->timings.pixel_clock = pck;
}
dispc_set_lcd_timings(&panel->timings);
err0:
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
return r;
}
/*
* Return a hardcoded channel for the DPI output. This should work for
* current use cases, but this can be later expanded to either resolve
* the channel in some more dynamic manner, or get the channel as a user
* parameter.
*/
static enum omap_channel dpi_get_channel(void)
{
switch (omapdss_get_version()) {
case OMAPDSS_VER_OMAP24xx:
case OMAPDSS_VER_OMAP34xx_ES1:
case OMAPDSS_VER_OMAP34xx_ES3:
case OMAPDSS_VER_OMAP3630:
case OMAPDSS_VER_AM35xx:
return OMAP_DSS_CHANNEL_LCD;
case OMAPDSS_VER_OMAP4430_ES1:
case OMAPDSS_VER_OMAP4430_ES2:
case OMAPDSS_VER_OMAP4:
return OMAP_DSS_CHANNEL_LCD2;
case OMAPDSS_VER_OMAP5:
return OMAP_DSS_CHANNEL_LCD3;
default:
DSSWARN("unsupported DSS version\n");
return OMAP_DSS_CHANNEL_LCD;
}
}
static int dpi_set_mode(struct omap_dss_device *dssdev)
{
struct omap_video_timings *t = &dssdev->panel.timings;
int lck_div = 0, pck_div = 0;
unsigned long fck = 0;
unsigned long pck;
bool is_tft;
int r = 0;
dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
dssdev->panel.acbi, dssdev->panel.acb);
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
if (dpi_use_dsi_pll(dssdev))
r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
&fck, &lck_div, &pck_div);
else
r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
&fck, &lck_div, &pck_div);
if (r)
return r;
pck = fck / lck_div / pck_div / 1000;
if (pck != t->pixel_clock) {
DSSWARN("Could not find exact pixel clock. "
"Requested %d kHz, got %lu kHz\n",
t->pixel_clock, pck);
t->pixel_clock = pck;
}
dispc_set_lcd_timings(dssdev->manager->id, t);
return 0;
}
int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
{
struct omap_video_timings *t = &dssdev->panel.timings;
struct dss_clock_info dss_cinfo;
struct dispc_clock_info dispc_cinfo;
u16 lck_div, pck_div;
unsigned long fck;
unsigned long pck;
int r;
if (dssdev->manager == NULL) {
DSSERR("failed to enable display: no manager\n");
return -ENODEV;
}
r = omap_dss_start_device(dssdev);
if (r) {
DSSERR("failed to start device\n");
goto err_start_dev;
}
r = regulator_enable(sdi.vdds_sdi_reg);
if (r)
goto err_reg_enable;
r = dss_runtime_get();
if (r)
goto err_get_dss;
r = dispc_runtime_get();
if (r)
goto err_get_dispc;
sdi_basic_init(dssdev);
/* */
dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
dssdev->panel.acbi, dssdev->panel.acb);
r = dss_calc_clock_div(1, t->pixel_clock * 1000,
&dss_cinfo, &dispc_cinfo);
if (r)
goto err_calc_clock_div;
fck = dss_cinfo.fck;
lck_div = dispc_cinfo.lck_div;
pck_div = dispc_cinfo.pck_div;
pck = fck / lck_div / pck_div / 1000;
if (pck != t->pixel_clock) {
DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
"got %lu kHz\n",
t->pixel_clock, pck);
t->pixel_clock = pck;
}
dispc_mgr_set_lcd_timings(dssdev->manager->id, t);
r = dss_set_clock_div(&dss_cinfo);
if (r)
goto err_set_dss_clock_div;
r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
if (r)
goto err_set_dispc_clock_div;
dss_sdi_init(dssdev->phy.sdi.datapairs);
r = dss_sdi_enable();
if (r)
goto err_sdi_enable;
mdelay(2);
r = dss_mgr_enable(dssdev->manager);
if (r)
goto err_mgr_enable;
return 0;
err_mgr_enable:
dss_sdi_disable();
err_sdi_enable:
err_set_dispc_clock_div:
err_set_dss_clock_div:
err_calc_clock_div:
dispc_runtime_put();
err_get_dispc:
dss_runtime_put();
err_get_dss:
regulator_disable(sdi.vdds_sdi_reg);
err_reg_enable:
omap_dss_stop_device(dssdev);
err_start_dev:
return r;
}
static int sdi_display_enable(struct omap_display *display)
{
struct dispc_clock_info cinfo;
u16 lck_div, pck_div;
unsigned long fck;
struct omap_panel *panel = display->panel;
unsigned long pck;
int r;
if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
DSSERR("display already enabled\n");
return -EINVAL;
}
twl4030_enable_regulator(RES_VAUX1);
sdi_pad_config(display, 1);
/* In case of skip_init sdi_init has already enabled the clocks */
if (!sdi.skip_init)
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
sdi_basic_init();
/* 15.5.9.1.2 */
panel->config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
dispc_set_pol_freq(panel);
if (!sdi.skip_init)
r = dispc_calc_clock_div(1, panel->timings.pixel_clock * 1000,
&cinfo);
else
r = dispc_get_clock_div(&cinfo);
if (r)
goto err0;
fck = cinfo.fck;
lck_div = cinfo.lck_div;
pck_div = cinfo.pck_div;
pck = fck / lck_div / pck_div / 1000;
if (pck != panel->timings.pixel_clock) {
DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
"got %lu kHz\n",
panel->timings.pixel_clock, pck);
panel->timings.pixel_clock = pck;
}
dispc_set_lcd_timings(&panel->timings);
r = dispc_set_clock_div(&cinfo);
if (r)
goto err1;
if (!sdi.skip_init) {
dss_sdi_init(display->hw_config.u.sdi.datapairs);
r = dss_sdi_enable();
if (r)
goto err1;
mdelay(2);
}
dispc_enable_lcd_out(1);
r = panel->enable(display);
if (r)
goto err2;
display->state = OMAP_DSS_DISPLAY_ACTIVE;
sdi.skip_init = 0;
return 0;
err2:
dispc_enable_lcd_out(0);
err1:
err0:
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
twl4030_disable_regulator(RES_VAUX1);
return r;
}
static int sdi_display_enable(struct omap_dss_device *dssdev)
{
struct sdi_device *sdi = dssdev_to_sdi(dssdev);
struct videomode *vm = &sdi->vm;
unsigned long fck;
struct dispc_clock_info dispc_cinfo;
unsigned long pck;
int r;
if (!sdi->output.dispc_channel_connected) {
DSSERR("failed to enable display: no output/manager\n");
return -ENODEV;
}
r = regulator_enable(sdi->vdds_sdi_reg);
if (r)
goto err_reg_enable;
r = dispc_runtime_get(sdi->dss->dispc);
if (r)
goto err_get_dispc;
/* 15.5.9.1.2 */
vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE;
r = sdi_calc_clock_div(sdi, vm->pixelclock, &fck, &dispc_cinfo);
if (r)
goto err_calc_clock_div;
sdi->mgr_config.clock_info = dispc_cinfo;
pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
if (pck != vm->pixelclock) {
DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
vm->pixelclock, pck);
vm->pixelclock = pck;
}
dss_mgr_set_timings(&sdi->output, vm);
r = dss_set_fck_rate(sdi->dss, fck);
if (r)
goto err_set_dss_clock_div;
sdi_config_lcd_manager(sdi);
/*
* LCLK and PCLK divisors are located in shadow registers, and we
* normally write them to DISPC registers when enabling the output.
* However, SDI uses pck-free as source clock for its PLL, and pck-free
* is affected by the divisors. And as we need the PLL before enabling
* the output, we need to write the divisors early.
*
* It seems just writing to the DISPC register is enough, and we don't
* need to care about the shadow register mechanism for pck-free. The
* exact reason for this is unknown.
*/
dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel,
&sdi->mgr_config.clock_info);
dss_sdi_init(sdi->dss, sdi->datapairs);
r = dss_sdi_enable(sdi->dss);
if (r)
goto err_sdi_enable;
mdelay(2);
r = dss_mgr_enable(&sdi->output);
if (r)
goto err_mgr_enable;
return 0;
err_mgr_enable:
dss_sdi_disable(sdi->dss);
err_sdi_enable:
err_set_dss_clock_div:
err_calc_clock_div:
dispc_runtime_put(sdi->dss->dispc);
err_get_dispc:
regulator_disable(sdi->vdds_sdi_reg);
err_reg_enable:
return r;
}
static int sdi_display_enable(struct omap_dss_device *dssdev)
{
struct omap_dss_device *out = &sdi.output;
struct omap_video_timings *t = &sdi.timings;
unsigned long fck;
struct dispc_clock_info dispc_cinfo;
unsigned long pck;
int r;
if (out == NULL || out->manager == NULL) {
DSSERR("failed to enable display: no output/manager\n");
return -ENODEV;
}
r = regulator_enable(sdi.vdds_sdi_reg);
if (r)
goto err_reg_enable;
r = dispc_runtime_get();
if (r)
goto err_get_dispc;
/* 15.5.9.1.2 */
t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
r = sdi_calc_clock_div(t->pixel_clock * 1000, &fck, &dispc_cinfo);
if (r)
goto err_calc_clock_div;
sdi.mgr_config.clock_info = dispc_cinfo;
pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000;
if (pck != t->pixel_clock) {
DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
"got %lu kHz\n",
t->pixel_clock, pck);
t->pixel_clock = pck;
}
dss_mgr_set_timings(out->manager, t);
r = dss_set_fck_rate(fck);
if (r)
goto err_set_dss_clock_div;
sdi_config_lcd_manager(dssdev);
/*
* LCLK and PCLK divisors are located in shadow registers, and we
* normally write them to DISPC registers when enabling the output.
* However, SDI uses pck-free as source clock for its PLL, and pck-free
* is affected by the divisors. And as we need the PLL before enabling
* the output, we need to write the divisors early.
*
* It seems just writing to the DISPC register is enough, and we don't
* need to care about the shadow register mechanism for pck-free. The
* exact reason for this is unknown.
*/
dispc_mgr_set_clock_div(out->manager->id, &sdi.mgr_config.clock_info);
dss_sdi_init(sdi.datapairs);
r = dss_sdi_enable();
if (r)
goto err_sdi_enable;
mdelay(2);
r = dss_mgr_enable(out->manager);
if (r)
goto err_mgr_enable;
return 0;
err_mgr_enable:
dss_sdi_disable();
err_sdi_enable:
err_set_dss_clock_div:
err_calc_clock_div:
dispc_runtime_put();
err_get_dispc:
regulator_disable(sdi.vdds_sdi_reg);
err_reg_enable:
return r;
}
int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
{
struct omap_video_timings *t = &dssdev->panel.timings;
struct dss_clock_info dss_cinfo;
struct dispc_clock_info dispc_cinfo;
u16 lck_div, pck_div;
unsigned long fck;
unsigned long pck;
int r;
r = omap_dss_start_device(dssdev);
if (r) {
DSSERR("failed to start device\n");
goto err0;
}
r = regulator_enable(sdi.vdds_sdi_reg);
if (r)
goto err1;
/* In case of skip_init sdi_init has already enabled the clocks */
if (!sdi.skip_init)
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
sdi_basic_init();
/* 15.5.9.1.2 */
dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
dssdev->panel.acb);
if (!sdi.skip_init) {
r = dss_calc_clock_div(1, t->pixel_clock * 1000,
&dss_cinfo, &dispc_cinfo);
} else {
r = dss_get_clock_div(&dss_cinfo);
r = dispc_get_clock_div(&dispc_cinfo);
}
if (r)
goto err2;
fck = dss_cinfo.fck;
lck_div = dispc_cinfo.lck_div;
pck_div = dispc_cinfo.pck_div;
pck = fck / lck_div / pck_div / 1000;
if (pck != t->pixel_clock) {
DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
"got %lu kHz\n",
t->pixel_clock, pck);
t->pixel_clock = pck;
}
dispc_set_lcd_timings(t);
r = dss_set_clock_div(&dss_cinfo);
if (r)
goto err2;
r = dispc_set_clock_div(&dispc_cinfo);
if (r)
goto err2;
if (!sdi.skip_init) {
dss_sdi_init(dssdev->phy.sdi.datapairs);
r = dss_sdi_enable();
if (r)
goto err1;
mdelay(2);
}
dssdev->manager->enable(dssdev->manager);
sdi.skip_init = 0;
return 0;
err2:
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
regulator_disable(sdi.vdds_sdi_reg);
err1:
omap_dss_stop_device(dssdev);
err0:
return r;
}
static int dpi_set_mode(struct omap_dss_device *dssdev)
{
struct omap_video_timings *t = &dssdev->panel.timings;
int lck_div = 0, pck_div = 0;
unsigned long fck = 0;
unsigned long pck = 0;
bool is_tft;
int r = 0, lcd_channel_ix = 0;
int use_dsi_for_hdmi = 0;
if (strncmp("hdmi", dssdev->name, 4) == 0)
use_dsi_for_hdmi = 1;
if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2)
lcd_channel_ix = 1;
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2)
dispc_set_pol_freq(OMAP_DSS_CHANNEL_LCD2, dssdev->panel.config,
dssdev->panel.acbi, dssdev->panel.acb);
else
dispc_set_pol_freq(OMAP_DSS_CHANNEL_LCD, dssdev->panel.config,
dssdev->panel.acbi, dssdev->panel.acb);
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
if (use_dsi_for_hdmi)
r = dpi_set_dsi_clk(lcd_channel_ix, is_tft,
t->pixel_clock * 1000,
&fck, &lck_div, &pck_div);
else
r = dpi_set_dispc_clk(lcd_channel_ix, is_tft,
t->pixel_clock * 1000,
&fck, &lck_div, &pck_div);
if (r)
goto err0;
if (!cpu_is_omap44xx())
pck = fck / lck_div / pck_div / 1000;
else
pck = 0;
if (pck != t->pixel_clock) {
DSSWARN("Could not find exact pixel clock. "
"Requested %d kHz, got %lu kHz\n",
t->pixel_clock, pck);
t->pixel_clock = pck;
}
if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2)
dispc_set_lcd_timings(OMAP_DSS_CHANNEL_LCD2, t);
else
dispc_set_lcd_timings(OMAP_DSS_CHANNEL_LCD, t);
err0:
if (cpu_is_omap44xx() && use_dsi_for_hdmi) {
dss_select_clk_source_dsi(lcd_channel_ix, false, false);
dsi_pll_uninit(lcd_channel_ix);
}
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
return r;
}
static int sdi_display_enable(struct omap_dss_device *dssdev)
{
struct omap_video_timings *t = &dssdev->panel.timings;
struct dss_clock_info dss_cinfo;
struct dispc_clock_info dispc_cinfo;
u16 lck_div, pck_div;
unsigned long fck;
unsigned long pck;
int r;
r = omap_dss_start_device(dssdev);
if (r) {
DSSERR("failed to start device\n");
goto err0;
}
if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
DSSERR("dssdev already enabled\n");
r = -EINVAL;
goto err1;
}
/* In case of skip_init sdi_init has already enabled the clocks */
if (!sdi.skip_init)
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
sdi_basic_init();
/* 15.5.9.1.2 */
dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
/* TODO: update for LCD2 here */
dispc_set_pol_freq(OMAP_DSS_CHANNEL_LCD, dssdev->panel.config,
dssdev->panel.acbi, dssdev->panel.acb);
if (!sdi.skip_init) {
r = dss_calc_clock_div(1, t->pixel_clock * 1000,
&dss_cinfo, &dispc_cinfo);
} else {
r = dss_get_clock_div(&dss_cinfo);
r = dispc_get_clock_div(&dispc_cinfo);
}
if (r)
goto err2;
fck = dss_cinfo.fck;
lck_div = dispc_cinfo.lck_div;
pck_div = dispc_cinfo.pck_div;
pck = fck / lck_div / pck_div / 1000;
if (pck != t->pixel_clock) {
DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
"got %lu kHz\n",
t->pixel_clock, pck);
t->pixel_clock = pck;
}
/* TODO: if needed, add LCD2 support here*/
dispc_set_lcd_timings(OMAP_DSS_CHANNEL_LCD, t);
r = dss_set_clock_div(&dss_cinfo);
if (r)
goto err2;
r = dispc_set_clock_div(&dispc_cinfo);
if (r)
goto err2;
if (!sdi.skip_init) {
dss_sdi_init(dssdev->phy.sdi.datapairs);
r = dss_sdi_enable();
if (r)
goto err1;
mdelay(2);
}
/* TODO: change here if LCD2 support is needed */
dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD, 1);
if (dssdev->driver->enable) {
r = dssdev->driver->enable(dssdev);
if (r)
goto err3;
}
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
sdi.skip_init = 0;
return 0;
err3:
/* TODO: change here if LCD2 support is needed */
dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD, 0);
err2:
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
err1:
omap_dss_stop_device(dssdev);
err0:
return r;
}
