/* start dvfs, wait for finish */
void pmu_dvfs_start_to_finish(void)
{
reg_val = readl(CCU_CPU_AHB_APB) | (1 << 31);
writel(reg_val, CCU_CPU_AHB_APB);
while(PmuReg->PmuSta.DvfsBusy == 1);
DVFS_DBG("%s: finished\n", __func__);
}
/* init pmu dvfs hardware configuration */
int __init pmu_dvfs_hw_init(void)
{
PmuReg = (__pmu_reg_list_t *)SW_VA_PMU_IO_BASE;
/* dvfs off */
pmu_dvfs_disable();
/* enable ccu pll6 */
__ccu_pll6_enable();
/* set ahb clock source */
__ccu_ahb_from_pll6();
/* set pll stable time */
pmu_dvfs_pll_stable_time_init();
/* config axi clock level */
pmu_dvfs_axi_clk_level_cfg();
/* enable axi auto switch*/
pmu_dvfs_axi_auto_swt_enable();
/* debug clk output for pll1 */
writel(0x3E008000,SW_VA_SRAM_IO_BASE+0x90); // PIOB4 OUTPUT=PLL1/8
/* init V-F table/index/range/valid bit */
pmu_dvfs_VF_cfg();
/*
**************************************
* cpu vdd value
*
* 0x08---------0.9v
* 0x0c---------1.0v
* 0x10---------1.1v
* 0x14---------1.2v
* 0x16---------1.25v
* 0x18---------1.3v
* 0x1c---------1.4v
* 0x20---------1.5v
* 0x24---------1.6v
**************************************
*/
/* change voltage independently; cpuvdd=0x1c, corevdd=0x16 */
//pmu_vtchg_independent(0x1c,0x16);
/* dvfs irq init */
pmu_dvfs_irq_init();
/* pmu_dvfs_config */
pmu_dvfs_config();
/* enable twi dvfs mode */
pmu_dvfs_mode_enable();
/* enable dvfs */
pmu_dvfs_enable();
/* clear pending */
pmu_dvfs_clear_pending();
/* sleep 50ms */
msleep(50);
DVFS_DBG("%s: finished\n", __func__);
return 0;
}
/**************************************vd regulator functions***************************************/
static void dvfs_volt_up_delay(struct vd_node *vd,int new_volt, int old_volt)
{
int u_time;
if(new_volt<=old_volt)
return;
if(vd->volt_time_flag>0)
u_time=regulator_set_voltage_time(vd->regulator,old_volt,new_volt);
else
u_time=-1;
if(u_time<0)// regulator is not suported time,useing default time
{
DVFS_DBG("%s:vd %s is not suported getting delay time,so we use default\n",
__FUNCTION__,vd->name);
u_time=((new_volt) - (old_volt)) >> 9;
}
