static void CompletionDescHandler()
{
int qid;
uint32_t status;
status = 0;
/* Init to lowest prioirty */
qid = 0;
//PRINT_INFO("--->now into CompletionDescHandler()\n");
/* Mask only one counter per queue */
while ( (status |= ( DX_HAL_ReadCcRegister(DX_CC_REG_OFFSET(CRY_KERNEL,DSCRPTR_COMPLETION_STATUS)) & BITMASK(MAX_COMPLETION_COUNTERS))) ) {
/* Loop will start at highest prioirty */
qid = (qid + 1 ) & (MAX_COMPLETION_COUNTERS-1);
if (status & BITMASK_AT(1, qid)) {
/* Read completion counter register. Counter is cleared once we read it ! */
gCompletionCount[qid] += DX_HAL_ReadCcRegister(DX_CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_COMPLETION_COUNTER0) +
qid*sizeof(uint32_t));
/* status still set, but engine completion counter was already handled */
if ( gCompletionCount[qid] == 0 ) {
status = status & ~(BITMASK_AT(1, qid));
continue;
}
/* Get completion info from fifo, if not already done so */
if ( gCompletionCtx[qid] == COMPLETION_INVALID ) {
CompletionFifoRemove(qid, &gTaskId[qid], &gCompletionCtx[qid], &gExpectedAxiWrites[qid]);
}
/* Actual bus values of AXI IDs for queues (0-3) DMA are 8, 9, A, B */
gAxiWriteCompleted[qid] += DX_CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP8, VALUE,
DX_HAL_ReadCcRegister(DX_CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP8) +
QID_TO_AXI_ID(qid)*sizeof(uint32_t)));
if ( gAxiWriteCompleted[qid] >= gExpectedAxiWrites[qid] ) {
gAxiWriteCompleted[qid] -= gExpectedAxiWrites[qid];
gCompletionCtx[qid] = COMPLETION_INVALID;
gCompletionCount[qid]--;
}
} /* if (status & BITMASK_AT(1, qid)) */
} /* while ( (status = ( READ_REGISTER... */
}
/*!
* This function initializes the completion counter event, clears the
* state structure and sets completion counter "0" as the first available
* counter to be used when calling "AllocCounter".
*
* \return int one of the error codes defined in err.h
*/
int InitCompletionPlat(void)
{
uint8_t dummy;
int qid;
/* Clear completion fifo */
for ( qid=0; qid < MAX_NUM_HW_QUEUES; qid++ ) {
/* Clear FIFO head/tail */
gCompletionFifoHead[qid] = 0;
gCompletionFifoTail[qid] = 0;
/* The global AXI write counter is reset only once */
gAxiWriteCompleted[qid] = 0;
gCompletionCount[qid] = 0;
gExpectedAxiWrites[qid] = 0;
gCompletionCtx[qid] = COMPLETION_INVALID;
DX_PAL_MemSetZero( gCompletionFifo, MAX_NUM_HW_QUEUES*COMPLETION_FIFO_LEN );
/* Clear all past AXI completion counters */
/* Actual bus values of AXI IDs for queues (0-3) DMA are 8, 9, A, B */
dummy = DX_HAL_ReadCcRegister(DX_CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP8) + QID_TO_AXI_ID(qid)*sizeof(uint32_t));
DX_PAL_LOG_DEBUG("Initial AXI_MON_COMP%d value=0x%08X\n", (int)qid, (unsigned int)dummy);
dummy = dummy; /*avoid compiler warning*/
}
return DX_RET_OK;
}
/*!
* Busy wait upon Interrupt Request Register (IRR) signals.
* This function notifys for any CC interrupt, it is the caller responsiblity
* to verify and prompt the expected case interupt source.
*
* @param[in] data - input data for future use
* \return uint32_t The IRR value.
*/
uint32_t DX_HAL_WaitInterrupt(uint32_t data)
{
uint32_t irr = 0;
/* busy wait upon IRR signal */
while ( !(irr = DX_HAL_ReadCcRegister(DX_CC_REG_OFFSET(HOST_RGF, HOST_RGF_IRR))) );
return irr;
}
