void I2CStop(eI2C_CHANNEL i2cPort)
{
int timeout;
I2CReg_t * pReg;
pReg = I2CPORT(i2cPort);
timeout = 200000; // timeout must long enogh,that will suit some slow suitation.
pReg->I2C_LCMR |=( I2C_LCMR_RESUME | I2C_LCMR_STOP);
while (((pReg->I2C_LCMR & I2C_LCMR_STOP) != 0) && (timeout > 0))
{
Delay10cyc(1);
timeout--;
}
pReg->I2C_LCMR = 0x4;
}
void __sramlocalfunc __ddr_reconfig(int mode)
{
#if 1
int i, n, bakdatr;
volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
// __cpuc_flush_kern_all();
// __cpuc_flush_user_all();
local_flush_tlb_all();
n=temp[0];
barrier();
n=temp[1024];
barrier();
n=temp[1024*2];
barrier();
n=temp[1024*3];
barrier();
n= pSCU_Reg->CRU_SOFTRST_CON[0];
dsb();
pDDR_Reg->DLLCR09[0] &=~0x3c000;
pDDR_Reg->DLLCR09[1] &=~0x3c000;
pDDR_Reg->DLLCR09[2] &=~0x3c000;
pDDR_Reg->DLLCR09[3] &=~0x3c000;
pDDR_Reg->DLLCR09[0] |=0x4000; //set 90-18
pDDR_Reg->DLLCR09[1] |=0x4000;
pDDR_Reg->DLLCR09[2] |=0x4000;
pDDR_Reg->DLLCR09[3] |=0x4000;
n=pGRF_Reg->GRF_OS_REG[2]; // *(unsigned long volatile *)(0xf50080d8);
pDDR_Reg->CCR &= ~HOSTEN; //ddr3 400m 4us 4*6*rank+1;
pDDR_Reg->DCR = (pDDR_Reg->DCR & (~((0x1<<24) | (0x1<<13) | (0xF<<27) | (0x1<<31)))) | ((0x1<<13) | (0x2<<27) | (0x1<<31)); //enter Self Refresh
while(pDDR_Reg->DCR &(0x1<<31)); //may done soon
ddrReg_Save();
#if 1
#if 1
//DO_INT Must be cleared before ddrReg_Save
pSCU_Reg->CRU_SOFTRST_CON[2] |= ((0x3<<15) | (0x3<<11) |(0x3<<8));
pSCU_Reg->CRU_SOFTRST_CON[0] |= (0x7f<<18);
dsb();
Delay10cyc(100);
pSCU_Reg->CRU_SOFTRST_CON[2] &= ~((0x3<<15) | (0x3<<11) | (0x3<<8));
// if((mode >>12)&0xfff)
// *(unsigned long volatile *)(0xf50080ac) =mode &0xfff;
pDDR_Reg->PQCR[0] =0x0e03f000;
pDDR_Reg->PQCR[1] =(mode ==0) ?0x0e000000 : 0x0e00f000;
// pDDR_Reg->PQCR[2] =0x0e00f000;
ddrReg_Restore();
pDDR_Reg->MMGCR =((mode&0xf) ==0) ?0 : 2;
pSCU_Reg->CRU_SOFTRST_CON[0] &=~(0x7F<<18);
dsb();
Delay10cyc(200); //need 1024 cycles, worst case assume ddr @200MHZ, cpu at @1GHZ, need 5120 cycles delay
// if((pDDR_Reg->DRR) &0x0f000000)
// while(1);
#else
cru_gatecon[0] =pSCU_Reg->CRU_CLKGATE_CON[0];
cru_gatecon[1] =pSCU_Reg->CRU_CLKGATE_CON[1];
cru_gatecon[3] =pSCU_Reg->CRU_CLKGATE_CON[3];
pSCU_Reg->CRU_CLKGATE_CON[0] |=/*(2<<19)*/(3<<9);
pSCU_Reg->CRU_CLKGATE_CON[1] |=(1<<6);
pSCU_Reg->CRU_CLKGATE_CON[3] |=((1<<1) |(0xf<<10) |(0xf<<14));
pSCU_Reg->CRU_SOFTRST_CON[2] |=(1<<9);// ((0x1<<15) | (0x3<<11) | (0x3<<8));
dsb();
Delay10cyc(100);
pSCU_Reg->CRU_SOFTRST_CON[0] |= (0x7f<<18);
Delay10cyc(100);
pSCU_Reg->CRU_SOFTRST_CON[2] &= ~((0x1<<15) | (0x3<<11) | (0x3<<8));
if((mode >>12)&0xfff)
*(unsigned long volatile *)(0xf50080ac) =mode &0xfff;
pDDR_Reg->PQCR[0] =0x0e03f000;
pDDR_Reg->PQCR[1] =0x0e01f000;
pDDR_Reg->PQCR[2] =0x0e00f000;
ddrReg_Restore();
pDDR_Reg->MMGCR =(mode ==0) ?0:2;
dsb();
pSCU_Reg->CRU_SOFTRST_CON[0] &=~(0x7F<<18);
dsb();
Delay10cyc(100);
pSCU_Reg->CRU_CLKGATE_CON[0]=cru_gatecon[0];
pSCU_Reg->CRU_CLKGATE_CON[1]=cru_gatecon[1];
pSCU_Reg->CRU_CLKGATE_CON[3]=cru_gatecon[3];
Delay10cyc(200); //need 1024 cycles, worst case assume ddr @200MHZ, cpu at @1GHZ, need 5120 cycles delay
#endif
pDDR_Reg->DCR |= DO_INIT;
while(pGRF_Reg->GRF_MEM_STATUS[2] & 0x1) //wait init ok
Delay10cyc(1);
pDDR_Reg->DRR |=(1<<31);
Delay10cyc(10);
pDDR_Reg->CCR |= DTT; //ddr3 400m 4us 4*6*rank+1;
Delay10cyc(100);
while(pGRF_Reg->GRF_MEM_STATUS[2] & 0x1) //wait dtt ok
Delay10cyc(1);
if(pGRF_Reg->GRF_MEM_STATUS[2] & 0x2)
while(1);
pDDR_Reg->DRR &=~(1<<31);
pDDR_Reg->DLLCR09[0] &=~0x3c000;
pDDR_Reg->DLLCR09[1] &=~0x3c000;
pDDR_Reg->DLLCR09[2] &=~0x3c000;
pDDR_Reg->DLLCR09[3] &=~0x3c000;
pDDR_Reg->DLLCR09[0] |=0x10000; //set 90+18
pDDR_Reg->DLLCR09[1] |=0x10000;
pDDR_Reg->DLLCR09[2] |=0x10000;
pDDR_Reg->DLLCR09[3] |=0x10000;
pDDR_Reg->DCR &=~DO_INIT;
pDDR_Reg->CCR |= HOSTEN; //enable host port
dsb();
#endif
#endif
}
