static UINT16 READ_EA_16(m68000_base_device *m68k, int ea)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
switch (mode)
{
case 0: // Dn
{
return (UINT16)(REG_D(m68k)[reg]);
}
case 2: // (An)
{
UINT32 ea = REG_A(m68k)[reg];
return m68ki_read_16(m68k, ea);
}
case 3: // (An)+
{
UINT32 ea = EA_AY_PI_16(m68k);
return m68ki_read_16(m68k, ea);
}
case 4: // -(An)
{
UINT32 ea = EA_AY_PD_16(m68k);
return m68ki_read_16(m68k, ea);
}
case 5: // (d16, An)
{
UINT32 ea = EA_AY_DI_16(m68k);
return m68ki_read_16(m68k, ea);
}
case 6: // (An) + (Xn) + d8
{
UINT32 ea = EA_AY_IX_16(m68k);
return m68ki_read_16(m68k, ea);
}
case 7:
{
switch (reg)
{
case 0: // (xxx).W
{
UINT32 ea = (UINT32)OPER_I_16(m68k);
return m68ki_read_16(m68k, ea);
}
case 1: // (xxx).L
{
UINT32 d1 = OPER_I_16(m68k);
UINT32 d2 = OPER_I_16(m68k);
UINT32 ea = (d1 << 16) | d2;
return m68ki_read_16(m68k, ea);
}
case 2: // (d16, PC)
{
UINT32 ea = EA_PCDI_16(m68k);
return m68ki_read_16(m68k, ea);
}
case 3: // (PC) + (Xn) + d8
{
UINT32 ea = EA_PCIX_16(m68k);
return m68ki_read_16(m68k, ea);
}
case 4: // #<data>
{
return OPER_I_16(m68k);
}
default: fatalerror("M68kFPU: READ_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k));
}
break;
}
default: fatalerror("M68kFPU: READ_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k));
}
return 0;
}
static void WRITE_EA_16(m68000_base_device *m68k, int ea, UINT16 data)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
switch (mode)
{
case 0: // Dn
{
REG_D(m68k)[reg] = data;
break;
}
case 2: // (An)
{
UINT32 ea = REG_A(m68k)[reg];
m68ki_write_16(m68k, ea, data);
break;
}
case 3: // (An)+
{
UINT32 ea = EA_AY_PI_16(m68k);
m68ki_write_16(m68k, ea, data);
break;
}
case 4: // -(An)
{
UINT32 ea = EA_AY_PD_16(m68k);
m68ki_write_16(m68k, ea, data);
break;
}
case 5: // (d16, An)
{
UINT32 ea = EA_AY_DI_16(m68k);
m68ki_write_16(m68k, ea, data);
break;
}
case 6: // (An) + (Xn) + d8
{
UINT32 ea = EA_AY_IX_16(m68k);
m68ki_write_16(m68k, ea, data);
break;
}
case 7:
{
switch (reg)
{
case 1: // (xxx).W
{
UINT32 d1 = OPER_I_16(m68k);
UINT32 d2 = OPER_I_16(m68k);
UINT32 ea = (d1 << 16) | d2;
m68ki_write_16(m68k, ea, data);
break;
}
case 2: // (d16, PC)
{
UINT32 ea = EA_PCDI_16(m68k);
m68ki_write_16(m68k, ea, data);
break;
}
default: fatalerror("M68kFPU: WRITE_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k));
}
break;
}
default: fatalerror("M68kFPU: WRITE_EA_16: unhandled mode %d, reg %d, data %08X at %08X\n", mode, reg, data, REG_PC(m68k));
}
}
static void WRITE_EA_8(m68ki_cpu_core *m68k, int ea, UINT8 data)
{
int mode = (ea >> 3) & 0x7;
int reg = (ea & 0x7);
switch (mode)
{
case 0: // Dn
{
REG_D[reg] = data;
break;
}
case 2: // (An)
{
UINT32 ea = REG_A[reg];
m68ki_write_8(m68k, ea, data);
break;
}
case 3: // (An)+
{
UINT32 ea = EA_AY_PI_8(m68k);
m68ki_write_8(m68k, ea, data);
break;
}
case 4: // -(An)
{
UINT32 ea = EA_AY_PD_8(m68k);
m68ki_write_8(m68k, ea, data);
break;
}
case 5: // (d16, An)
{
UINT32 ea = EA_AY_DI_8(m68k);
m68ki_write_8(m68k, ea, data);
break;
}
case 6: // (An) + (Xn) + d8
{
UINT32 ea = EA_AY_IX_8(m68k);
m68ki_write_8(m68k, ea, data);
break;
}
case 7:
{
switch (reg)
{
case 1: // (xxx).B
{
UINT32 d1 = OPER_I_16(m68k);
UINT32 d2 = OPER_I_16(m68k);
UINT32 ea = (d1 << 16) | d2;
m68ki_write_8(m68k, ea, data);
break;
}
case 2: // (d16, PC)
{
UINT32 ea = EA_PCDI_16(m68k);
m68ki_write_8(m68k, ea, data);
break;
}
default: fatalerror("MC68040: WRITE_EA_8: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
}
break;
}
default: fatalerror("MC68040: WRITE_EA_8: unhandled mode %d, reg %d, data %08X at %08X\n", mode, reg, data, REG_PC);
}
}